1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip USBDP Combo PHY with Samsung IP block driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __PHY_ROCKCHIP_USBDP_H_ 9*4882a593Smuzhiyun #define __PHY_ROCKCHIP_USBDP_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bits.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* RK3588 USBDP PHY Register Definitions */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define UDPHY_PCS 0x4000 16*4882a593Smuzhiyun #define UDPHY_PMA 0x8000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* VO0 GRF Registers */ 19*4882a593Smuzhiyun #define RK3588_GRF_VO0_CON0 0x0000 20*4882a593Smuzhiyun #define RK3588_GRF_VO0_CON2 0x0008 21*4882a593Smuzhiyun #define DP_SINK_HPD_CFG BIT(11) 22*4882a593Smuzhiyun #define DP_SINK_HPD_SEL BIT(10) 23*4882a593Smuzhiyun #define DP_AUX_DIN_SEL BIT(9) 24*4882a593Smuzhiyun #define DP_AUX_DOUT_SEL BIT(8) 25*4882a593Smuzhiyun #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) 26*4882a593Smuzhiyun #define DP_LANE_SEL_ALL GENMASK(7, 0) 27*4882a593Smuzhiyun #define PHY_AUX_DP_DATA_POL_NORMAL 0 28*4882a593Smuzhiyun #define PHY_AUX_DP_DATA_POL_INVERT 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* PMA CMN Registers */ 31*4882a593Smuzhiyun #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ 32*4882a593Smuzhiyun #define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) 33*4882a593Smuzhiyun #define CMN_DP_LANE_EN_N(n) BIT(n) 34*4882a593Smuzhiyun #define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) 35*4882a593Smuzhiyun #define CMN_DP_LANE_EN_ALL GENMASK(3, 0) 36*4882a593Smuzhiyun #define PHY_LANE_MUX_USB 0 37*4882a593Smuzhiyun #define PHY_LANE_MUX_DP 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ 40*4882a593Smuzhiyun #define CMN_DP_TX_LINK_BW GENMASK(6, 5) 41*4882a593Smuzhiyun #define CMN_DP_TX_LANE_SWAP_EN BIT(2) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ 44*4882a593Smuzhiyun #define CMN_ROPLL_SSC_EN BIT(1) 45*4882a593Smuzhiyun #define CMN_LCPLL_SSC_EN BIT(0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ 48*4882a593Smuzhiyun #define CMN_ANA_LCPLL_LOCK_DONE BIT(7) 49*4882a593Smuzhiyun #define CMN_ANA_LCPLL_AFC_DONE BIT(6) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ 52*4882a593Smuzhiyun #define CMN_ANA_ROPLL_LOCK_DONE BIT(1) 53*4882a593Smuzhiyun #define CMN_ANA_ROPLL_AFC_DONE BIT(0) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ 56*4882a593Smuzhiyun #define CMN_DP_INIT_RSTN BIT(3) 57*4882a593Smuzhiyun #define CMN_DP_CMN_RSTN BIT(2) 58*4882a593Smuzhiyun #define CMN_CDR_WTCHDG_EN BIT(1) 59*4882a593Smuzhiyun #define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ 62*4882a593Smuzhiyun #define LN_ANA_TX_SER_TXCLK_INV BIT(1) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ 65*4882a593Smuzhiyun #define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ 68*4882a593Smuzhiyun #define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71