1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * omap_control_phy.h - Header file for the PHY part of control module.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6*4882a593Smuzhiyun * Author: Kishon Vijay Abraham I <kishon@ti.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __OMAP_CONTROL_PHY_H__
10*4882a593Smuzhiyun #define __OMAP_CONTROL_PHY_H__
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun enum omap_control_phy_type {
13*4882a593Smuzhiyun OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
14*4882a593Smuzhiyun OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
15*4882a593Smuzhiyun OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
16*4882a593Smuzhiyun OMAP_CTRL_TYPE_PCIE, /* RX TX control of ACSPCIE */
17*4882a593Smuzhiyun OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
18*4882a593Smuzhiyun OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct omap_control_phy {
22*4882a593Smuzhiyun struct device *dev;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun u32 __iomem *otghs_control;
25*4882a593Smuzhiyun u32 __iomem *power;
26*4882a593Smuzhiyun u32 __iomem *power_aux;
27*4882a593Smuzhiyun u32 __iomem *pcie_pcs;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct clk *sys_clk;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun enum omap_control_phy_type type;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun enum omap_control_usb_mode {
35*4882a593Smuzhiyun USB_MODE_UNDEFINED = 0,
36*4882a593Smuzhiyun USB_MODE_HOST,
37*4882a593Smuzhiyun USB_MODE_DEVICE,
38*4882a593Smuzhiyun USB_MODE_DISCONNECT,
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define OMAP_CTRL_DEV_PHY_PD BIT(0)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define OMAP_CTRL_DEV_AVALID BIT(0)
44*4882a593Smuzhiyun #define OMAP_CTRL_DEV_BVALID BIT(1)
45*4882a593Smuzhiyun #define OMAP_CTRL_DEV_VBUSVALID BIT(2)
46*4882a593Smuzhiyun #define OMAP_CTRL_DEV_SESSEND BIT(3)
47*4882a593Smuzhiyun #define OMAP_CTRL_DEV_IDDIG BIT(4)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
50*4882a593Smuzhiyun #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
53*4882a593Smuzhiyun #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
56*4882a593Smuzhiyun #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define OMAP_CTRL_PCIE_PCS_MASK 0xff
59*4882a593Smuzhiyun #define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 16
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define OMAP_CTRL_USB2_PHY_PD BIT(28)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define AM437X_CTRL_USB2_PHY_PD BIT(0)
64*4882a593Smuzhiyun #define AM437X_CTRL_USB2_OTG_PD BIT(1)
65*4882a593Smuzhiyun #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
66*4882a593Smuzhiyun #define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
69*4882a593Smuzhiyun void omap_control_phy_power(struct device *dev, int on);
70*4882a593Smuzhiyun void omap_control_usb_set_mode(struct device *dev,
71*4882a593Smuzhiyun enum omap_control_usb_mode mode);
72*4882a593Smuzhiyun void omap_control_pcie_pcs(struct device *dev, u8 delay);
73*4882a593Smuzhiyun #else
74*4882a593Smuzhiyun
omap_control_phy_power(struct device * dev,int on)75*4882a593Smuzhiyun static inline void omap_control_phy_power(struct device *dev, int on)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
omap_control_usb_set_mode(struct device * dev,enum omap_control_usb_mode mode)79*4882a593Smuzhiyun static inline void omap_control_usb_set_mode(struct device *dev,
80*4882a593Smuzhiyun enum omap_control_usb_mode mode)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
omap_control_pcie_pcs(struct device * dev,u8 delay)84*4882a593Smuzhiyun static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #endif /* __OMAP_CONTROL_PHY_H__ */
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