xref: /OK3568_Linux_fs/kernel/include/linux/pci-epc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun  * PCI Endpoint *Controller* (EPC) header file
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Texas Instruments
6*4882a593Smuzhiyun  * Author: Kishon Vijay Abraham I <kishon@ti.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef __LINUX_PCI_EPC_H
10*4882a593Smuzhiyun #define __LINUX_PCI_EPC_H
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/pci-epf.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun struct pci_epc;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun enum pci_epc_irq_type {
17*4882a593Smuzhiyun 	PCI_EPC_IRQ_UNKNOWN,
18*4882a593Smuzhiyun 	PCI_EPC_IRQ_LEGACY,
19*4882a593Smuzhiyun 	PCI_EPC_IRQ_MSI,
20*4882a593Smuzhiyun 	PCI_EPC_IRQ_MSIX,
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /**
24*4882a593Smuzhiyun  * struct pci_epc_ops - set of function pointers for performing EPC operations
25*4882a593Smuzhiyun  * @write_header: ops to populate configuration space header
26*4882a593Smuzhiyun  * @set_bar: ops to configure the BAR
27*4882a593Smuzhiyun  * @clear_bar: ops to reset the BAR
28*4882a593Smuzhiyun  * @map_addr: ops to map CPU address to PCI address
29*4882a593Smuzhiyun  * @unmap_addr: ops to unmap CPU address and PCI address
30*4882a593Smuzhiyun  * @set_msi: ops to set the requested number of MSI interrupts in the MSI
31*4882a593Smuzhiyun  *	     capability register
32*4882a593Smuzhiyun  * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
33*4882a593Smuzhiyun  *	     the MSI capability register
34*4882a593Smuzhiyun  * @set_msix: ops to set the requested number of MSI-X interrupts in the
35*4882a593Smuzhiyun  *	     MSI-X capability register
36*4882a593Smuzhiyun  * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
37*4882a593Smuzhiyun  *	     from the MSI-X capability register
38*4882a593Smuzhiyun  * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
39*4882a593Smuzhiyun  * @start: ops to start the PCI link
40*4882a593Smuzhiyun  * @stop: ops to stop the PCI link
41*4882a593Smuzhiyun  * @owner: the module owner containing the ops
42*4882a593Smuzhiyun  */
43*4882a593Smuzhiyun struct pci_epc_ops {
44*4882a593Smuzhiyun 	int	(*write_header)(struct pci_epc *epc, u8 func_no,
45*4882a593Smuzhiyun 				struct pci_epf_header *hdr);
46*4882a593Smuzhiyun 	int	(*set_bar)(struct pci_epc *epc, u8 func_no,
47*4882a593Smuzhiyun 			   struct pci_epf_bar *epf_bar);
48*4882a593Smuzhiyun 	void	(*clear_bar)(struct pci_epc *epc, u8 func_no,
49*4882a593Smuzhiyun 			     struct pci_epf_bar *epf_bar);
50*4882a593Smuzhiyun 	int	(*map_addr)(struct pci_epc *epc, u8 func_no,
51*4882a593Smuzhiyun 			    phys_addr_t addr, u64 pci_addr, size_t size);
52*4882a593Smuzhiyun 	void	(*unmap_addr)(struct pci_epc *epc, u8 func_no,
53*4882a593Smuzhiyun 			      phys_addr_t addr);
54*4882a593Smuzhiyun 	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
55*4882a593Smuzhiyun 	int	(*get_msi)(struct pci_epc *epc, u8 func_no);
56*4882a593Smuzhiyun 	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts,
57*4882a593Smuzhiyun 			    enum pci_barno, u32 offset);
58*4882a593Smuzhiyun 	int	(*get_msix)(struct pci_epc *epc, u8 func_no);
59*4882a593Smuzhiyun 	int	(*raise_irq)(struct pci_epc *epc, u8 func_no,
60*4882a593Smuzhiyun 			     enum pci_epc_irq_type type, u16 interrupt_num);
61*4882a593Smuzhiyun 	int	(*start)(struct pci_epc *epc);
62*4882a593Smuzhiyun 	void	(*stop)(struct pci_epc *epc);
63*4882a593Smuzhiyun 	const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
64*4882a593Smuzhiyun 						       u8 func_no);
65*4882a593Smuzhiyun 	struct module *owner;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /**
69*4882a593Smuzhiyun  * struct pci_epc_mem_window - address window of the endpoint controller
70*4882a593Smuzhiyun  * @phys_base: physical base address of the PCI address window
71*4882a593Smuzhiyun  * @size: the size of the PCI address window
72*4882a593Smuzhiyun  * @page_size: size of each page
73*4882a593Smuzhiyun  */
74*4882a593Smuzhiyun struct pci_epc_mem_window {
75*4882a593Smuzhiyun 	phys_addr_t	phys_base;
76*4882a593Smuzhiyun 	size_t		size;
77*4882a593Smuzhiyun 	size_t		page_size;
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /**
81*4882a593Smuzhiyun  * struct pci_epc_mem - address space of the endpoint controller
82*4882a593Smuzhiyun  * @window: address window of the endpoint controller
83*4882a593Smuzhiyun  * @bitmap: bitmap to manage the PCI address space
84*4882a593Smuzhiyun  * @pages: number of bits representing the address region
85*4882a593Smuzhiyun  * @lock: mutex to protect bitmap
86*4882a593Smuzhiyun  */
87*4882a593Smuzhiyun struct pci_epc_mem {
88*4882a593Smuzhiyun 	struct pci_epc_mem_window window;
89*4882a593Smuzhiyun 	unsigned long	*bitmap;
90*4882a593Smuzhiyun 	int		pages;
91*4882a593Smuzhiyun 	/* mutex to protect against concurrent access for memory allocation*/
92*4882a593Smuzhiyun 	struct mutex	lock;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /**
96*4882a593Smuzhiyun  * struct pci_epc - represents the PCI EPC device
97*4882a593Smuzhiyun  * @dev: PCI EPC device
98*4882a593Smuzhiyun  * @pci_epf: list of endpoint functions present in this EPC device
99*4882a593Smuzhiyun  * @ops: function pointers for performing endpoint operations
100*4882a593Smuzhiyun  * @windows: array of address space of the endpoint controller
101*4882a593Smuzhiyun  * @mem: first window of the endpoint controller, which corresponds to
102*4882a593Smuzhiyun  *       default address space of the endpoint controller supporting
103*4882a593Smuzhiyun  *       single window.
104*4882a593Smuzhiyun  * @num_windows: number of windows supported by device
105*4882a593Smuzhiyun  * @max_functions: max number of functions that can be configured in this EPC
106*4882a593Smuzhiyun  * @group: configfs group representing the PCI EPC device
107*4882a593Smuzhiyun  * @lock: mutex to protect pci_epc ops
108*4882a593Smuzhiyun  * @function_num_map: bitmap to manage physical function number
109*4882a593Smuzhiyun  * @notifier: used to notify EPF of any EPC events (like linkup)
110*4882a593Smuzhiyun  */
111*4882a593Smuzhiyun struct pci_epc {
112*4882a593Smuzhiyun 	struct device			dev;
113*4882a593Smuzhiyun 	struct list_head		pci_epf;
114*4882a593Smuzhiyun 	const struct pci_epc_ops	*ops;
115*4882a593Smuzhiyun 	struct pci_epc_mem		**windows;
116*4882a593Smuzhiyun 	struct pci_epc_mem		*mem;
117*4882a593Smuzhiyun 	unsigned int			num_windows;
118*4882a593Smuzhiyun 	u8				max_functions;
119*4882a593Smuzhiyun 	struct config_group		*group;
120*4882a593Smuzhiyun 	/* mutex to protect against concurrent access of EP controller */
121*4882a593Smuzhiyun 	struct mutex			lock;
122*4882a593Smuzhiyun 	unsigned long			function_num_map;
123*4882a593Smuzhiyun 	struct atomic_notifier_head	notifier;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /**
127*4882a593Smuzhiyun  * struct pci_epc_features - features supported by a EPC device per function
128*4882a593Smuzhiyun  * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
129*4882a593Smuzhiyun  * @msi_capable: indicate if the endpoint function has MSI capability
130*4882a593Smuzhiyun  * @msix_capable: indicate if the endpoint function has MSI-X capability
131*4882a593Smuzhiyun  * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
132*4882a593Smuzhiyun  * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
133*4882a593Smuzhiyun  * @bar_fixed_size: Array specifying the size supported by each BAR
134*4882a593Smuzhiyun  * @align: alignment size required for BAR buffer allocation
135*4882a593Smuzhiyun  */
136*4882a593Smuzhiyun struct pci_epc_features {
137*4882a593Smuzhiyun 	unsigned int	linkup_notifier : 1;
138*4882a593Smuzhiyun 	unsigned int	core_init_notifier : 1;
139*4882a593Smuzhiyun 	unsigned int	msi_capable : 1;
140*4882a593Smuzhiyun 	unsigned int	msix_capable : 1;
141*4882a593Smuzhiyun 	u8	reserved_bar;
142*4882a593Smuzhiyun 	u8	bar_fixed_64bit;
143*4882a593Smuzhiyun 	u64	bar_fixed_size[PCI_STD_NUM_BARS];
144*4882a593Smuzhiyun 	size_t	align;
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun #define pci_epc_create(dev, ops)    \
150*4882a593Smuzhiyun 		__pci_epc_create((dev), (ops), THIS_MODULE)
151*4882a593Smuzhiyun #define devm_pci_epc_create(dev, ops)    \
152*4882a593Smuzhiyun 		__devm_pci_epc_create((dev), (ops), THIS_MODULE)
153*4882a593Smuzhiyun 
epc_set_drvdata(struct pci_epc * epc,void * data)154*4882a593Smuzhiyun static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	dev_set_drvdata(&epc->dev, data);
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
epc_get_drvdata(struct pci_epc * epc)159*4882a593Smuzhiyun static inline void *epc_get_drvdata(struct pci_epc *epc)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	return dev_get_drvdata(&epc->dev);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun static inline int
pci_epc_register_notifier(struct pci_epc * epc,struct notifier_block * nb)165*4882a593Smuzhiyun pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	return atomic_notifier_chain_register(&epc->notifier, nb);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun struct pci_epc *
171*4882a593Smuzhiyun __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
172*4882a593Smuzhiyun 		      struct module *owner);
173*4882a593Smuzhiyun struct pci_epc *
174*4882a593Smuzhiyun __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
175*4882a593Smuzhiyun 		 struct module *owner);
176*4882a593Smuzhiyun void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
177*4882a593Smuzhiyun void pci_epc_destroy(struct pci_epc *epc);
178*4882a593Smuzhiyun int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
179*4882a593Smuzhiyun void pci_epc_linkup(struct pci_epc *epc);
180*4882a593Smuzhiyun void pci_epc_init_notify(struct pci_epc *epc);
181*4882a593Smuzhiyun void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
182*4882a593Smuzhiyun int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
183*4882a593Smuzhiyun 			 struct pci_epf_header *hdr);
184*4882a593Smuzhiyun int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
185*4882a593Smuzhiyun 		    struct pci_epf_bar *epf_bar);
186*4882a593Smuzhiyun void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
187*4882a593Smuzhiyun 		       struct pci_epf_bar *epf_bar);
188*4882a593Smuzhiyun int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
189*4882a593Smuzhiyun 		     phys_addr_t phys_addr,
190*4882a593Smuzhiyun 		     u64 pci_addr, size_t size);
191*4882a593Smuzhiyun void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
192*4882a593Smuzhiyun 			phys_addr_t phys_addr);
193*4882a593Smuzhiyun int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
194*4882a593Smuzhiyun int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
195*4882a593Smuzhiyun int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
196*4882a593Smuzhiyun 		     enum pci_barno, u32 offset);
197*4882a593Smuzhiyun int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
198*4882a593Smuzhiyun int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
199*4882a593Smuzhiyun 		      enum pci_epc_irq_type type, u16 interrupt_num);
200*4882a593Smuzhiyun int pci_epc_start(struct pci_epc *epc);
201*4882a593Smuzhiyun void pci_epc_stop(struct pci_epc *epc);
202*4882a593Smuzhiyun const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
203*4882a593Smuzhiyun 						    u8 func_no);
204*4882a593Smuzhiyun enum pci_barno
205*4882a593Smuzhiyun pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
206*4882a593Smuzhiyun enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
207*4882a593Smuzhiyun 					 *epc_features, enum pci_barno bar);
208*4882a593Smuzhiyun struct pci_epc *pci_epc_get(const char *epc_name);
209*4882a593Smuzhiyun void pci_epc_put(struct pci_epc *epc);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
212*4882a593Smuzhiyun 		     size_t size, size_t page_size);
213*4882a593Smuzhiyun int pci_epc_multi_mem_init(struct pci_epc *epc,
214*4882a593Smuzhiyun 			   struct pci_epc_mem_window *window,
215*4882a593Smuzhiyun 			   unsigned int num_windows);
216*4882a593Smuzhiyun void pci_epc_mem_exit(struct pci_epc *epc);
217*4882a593Smuzhiyun void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
218*4882a593Smuzhiyun 				     phys_addr_t *phys_addr, size_t size);
219*4882a593Smuzhiyun void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
220*4882a593Smuzhiyun 			   void __iomem *virt_addr, size_t size);
221*4882a593Smuzhiyun #endif /* __LINUX_PCI_EPC_H */
222