1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _LINUX_NVME_RDMA_H 7*4882a593Smuzhiyun #define _LINUX_NVME_RDMA_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun enum nvme_rdma_cm_fmt { 10*4882a593Smuzhiyun NVME_RDMA_CM_FMT_1_0 = 0x0, 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum nvme_rdma_cm_status { 14*4882a593Smuzhiyun NVME_RDMA_CM_INVALID_LEN = 0x01, 15*4882a593Smuzhiyun NVME_RDMA_CM_INVALID_RECFMT = 0x02, 16*4882a593Smuzhiyun NVME_RDMA_CM_INVALID_QID = 0x03, 17*4882a593Smuzhiyun NVME_RDMA_CM_INVALID_HSQSIZE = 0x04, 18*4882a593Smuzhiyun NVME_RDMA_CM_INVALID_HRQSIZE = 0x05, 19*4882a593Smuzhiyun NVME_RDMA_CM_NO_RSC = 0x06, 20*4882a593Smuzhiyun NVME_RDMA_CM_INVALID_IRD = 0x07, 21*4882a593Smuzhiyun NVME_RDMA_CM_INVALID_ORD = 0x08, 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun nvme_rdma_cm_msg(enum nvme_rdma_cm_status status)24*4882a593Smuzhiyunstatic inline const char *nvme_rdma_cm_msg(enum nvme_rdma_cm_status status) 25*4882a593Smuzhiyun { 26*4882a593Smuzhiyun switch (status) { 27*4882a593Smuzhiyun case NVME_RDMA_CM_INVALID_LEN: 28*4882a593Smuzhiyun return "invalid length"; 29*4882a593Smuzhiyun case NVME_RDMA_CM_INVALID_RECFMT: 30*4882a593Smuzhiyun return "invalid record format"; 31*4882a593Smuzhiyun case NVME_RDMA_CM_INVALID_QID: 32*4882a593Smuzhiyun return "invalid queue ID"; 33*4882a593Smuzhiyun case NVME_RDMA_CM_INVALID_HSQSIZE: 34*4882a593Smuzhiyun return "invalid host SQ size"; 35*4882a593Smuzhiyun case NVME_RDMA_CM_INVALID_HRQSIZE: 36*4882a593Smuzhiyun return "invalid host RQ size"; 37*4882a593Smuzhiyun case NVME_RDMA_CM_NO_RSC: 38*4882a593Smuzhiyun return "resource not found"; 39*4882a593Smuzhiyun case NVME_RDMA_CM_INVALID_IRD: 40*4882a593Smuzhiyun return "invalid IRD"; 41*4882a593Smuzhiyun case NVME_RDMA_CM_INVALID_ORD: 42*4882a593Smuzhiyun return "Invalid ORD"; 43*4882a593Smuzhiyun default: 44*4882a593Smuzhiyun return "unrecognized reason"; 45*4882a593Smuzhiyun } 46*4882a593Smuzhiyun } 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /** 49*4882a593Smuzhiyun * struct nvme_rdma_cm_req - rdma connect request 50*4882a593Smuzhiyun * 51*4882a593Smuzhiyun * @recfmt: format of the RDMA Private Data 52*4882a593Smuzhiyun * @qid: queue Identifier for the Admin or I/O Queue 53*4882a593Smuzhiyun * @hrqsize: host receive queue size to be created 54*4882a593Smuzhiyun * @hsqsize: host send queue size to be created 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun struct nvme_rdma_cm_req { 57*4882a593Smuzhiyun __le16 recfmt; 58*4882a593Smuzhiyun __le16 qid; 59*4882a593Smuzhiyun __le16 hrqsize; 60*4882a593Smuzhiyun __le16 hsqsize; 61*4882a593Smuzhiyun u8 rsvd[24]; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * struct nvme_rdma_cm_rep - rdma connect reply 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * @recfmt: format of the RDMA Private Data 68*4882a593Smuzhiyun * @crqsize: controller receive queue size 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun struct nvme_rdma_cm_rep { 71*4882a593Smuzhiyun __le16 recfmt; 72*4882a593Smuzhiyun __le16 crqsize; 73*4882a593Smuzhiyun u8 rsvd[28]; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /** 77*4882a593Smuzhiyun * struct nvme_rdma_cm_rej - rdma connect reject 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * @recfmt: format of the RDMA Private Data 80*4882a593Smuzhiyun * @sts: error status for the associated connect request 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun struct nvme_rdma_cm_rej { 83*4882a593Smuzhiyun __le16 recfmt; 84*4882a593Smuzhiyun __le16 sts; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* _LINUX_NVME_RDMA_H */ 88