1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mv643xx.h - MV-643XX Internal registers definition file. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2002 Momentum Computer, Inc. 6*4882a593Smuzhiyun * Author: Matthew Dharm <mdharm@momenco.com> 7*4882a593Smuzhiyun * Copyright 2002 GALILEO TECHNOLOGY, LTD. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_MV643XX_H 10*4882a593Smuzhiyun #define __ASM_MV643XX_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/types.h> 13*4882a593Smuzhiyun #include <linux/mv643xx_eth.h> 14*4882a593Smuzhiyun #include <linux/mv643xx_i2c.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /****************************************/ 17*4882a593Smuzhiyun /* Processor Address Space */ 18*4882a593Smuzhiyun /****************************************/ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* DDR SDRAM BAR and size registers */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MV64340_CS_0_BASE_ADDR 0x008 23*4882a593Smuzhiyun #define MV64340_CS_0_SIZE 0x010 24*4882a593Smuzhiyun #define MV64340_CS_1_BASE_ADDR 0x208 25*4882a593Smuzhiyun #define MV64340_CS_1_SIZE 0x210 26*4882a593Smuzhiyun #define MV64340_CS_2_BASE_ADDR 0x018 27*4882a593Smuzhiyun #define MV64340_CS_2_SIZE 0x020 28*4882a593Smuzhiyun #define MV64340_CS_3_BASE_ADDR 0x218 29*4882a593Smuzhiyun #define MV64340_CS_3_SIZE 0x220 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Devices BAR and size registers */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define MV64340_DEV_CS0_BASE_ADDR 0x028 34*4882a593Smuzhiyun #define MV64340_DEV_CS0_SIZE 0x030 35*4882a593Smuzhiyun #define MV64340_DEV_CS1_BASE_ADDR 0x228 36*4882a593Smuzhiyun #define MV64340_DEV_CS1_SIZE 0x230 37*4882a593Smuzhiyun #define MV64340_DEV_CS2_BASE_ADDR 0x248 38*4882a593Smuzhiyun #define MV64340_DEV_CS2_SIZE 0x250 39*4882a593Smuzhiyun #define MV64340_DEV_CS3_BASE_ADDR 0x038 40*4882a593Smuzhiyun #define MV64340_DEV_CS3_SIZE 0x040 41*4882a593Smuzhiyun #define MV64340_BOOTCS_BASE_ADDR 0x238 42*4882a593Smuzhiyun #define MV64340_BOOTCS_SIZE 0x240 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* PCI 0 BAR and size registers */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define MV64340_PCI_0_IO_BASE_ADDR 0x048 47*4882a593Smuzhiyun #define MV64340_PCI_0_IO_SIZE 0x050 48*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058 49*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY0_SIZE 0x060 50*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080 51*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY1_SIZE 0x088 52*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258 53*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY2_SIZE 0x260 54*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280 55*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY3_SIZE 0x288 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* PCI 1 BAR and size registers */ 58*4882a593Smuzhiyun #define MV64340_PCI_1_IO_BASE_ADDR 0x090 59*4882a593Smuzhiyun #define MV64340_PCI_1_IO_SIZE 0x098 60*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0 61*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY0_SIZE 0x0a8 62*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0 63*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY1_SIZE 0x0b8 64*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0 65*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY2_SIZE 0x2a8 66*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0 67*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY3_SIZE 0x2b8 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* SRAM base address */ 70*4882a593Smuzhiyun #define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* internal registers space base address */ 73*4882a593Smuzhiyun #define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Enables the CS , DEV_CS , PCI 0 and PCI 1 76*4882a593Smuzhiyun windows above */ 77*4882a593Smuzhiyun #define MV64340_BASE_ADDR_ENABLE 0x278 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /****************************************/ 80*4882a593Smuzhiyun /* PCI remap registers */ 81*4882a593Smuzhiyun /****************************************/ 82*4882a593Smuzhiyun /* PCI 0 */ 83*4882a593Smuzhiyun #define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0 84*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 85*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 86*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 87*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 88*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 89*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 90*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 91*4882a593Smuzhiyun #define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 92*4882a593Smuzhiyun /* PCI 1 */ 93*4882a593Smuzhiyun #define MV64340_PCI_1_IO_ADDR_REMAP 0x108 94*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 95*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 96*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 97*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 98*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 99*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 100*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 101*4882a593Smuzhiyun #define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 104*4882a593Smuzhiyun #define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 105*4882a593Smuzhiyun #define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 106*4882a593Smuzhiyun #define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 107*4882a593Smuzhiyun #define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 108*4882a593Smuzhiyun #define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 109*4882a593Smuzhiyun #define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 110*4882a593Smuzhiyun #define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /****************************************/ 113*4882a593Smuzhiyun /* CPU Control Registers */ 114*4882a593Smuzhiyun /****************************************/ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define MV64340_CPU_CONFIG 0x000 117*4882a593Smuzhiyun #define MV64340_CPU_MODE 0x120 118*4882a593Smuzhiyun #define MV64340_CPU_MASTER_CONTROL 0x160 119*4882a593Smuzhiyun #define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150 120*4882a593Smuzhiyun #define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158 121*4882a593Smuzhiyun #define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /****************************************/ 124*4882a593Smuzhiyun /* SMP RegisterS */ 125*4882a593Smuzhiyun /****************************************/ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define MV64340_SMP_WHO_AM_I 0x200 128*4882a593Smuzhiyun #define MV64340_SMP_CPU0_DOORBELL 0x214 129*4882a593Smuzhiyun #define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C 130*4882a593Smuzhiyun #define MV64340_SMP_CPU1_DOORBELL 0x224 131*4882a593Smuzhiyun #define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C 132*4882a593Smuzhiyun #define MV64340_SMP_CPU0_DOORBELL_MASK 0x234 133*4882a593Smuzhiyun #define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C 134*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR0 0x244 135*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR1 0x24c 136*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR2 0x254 137*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR3 0x25c 138*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR4 0x264 139*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR5 0x26c 140*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR6 0x274 141*4882a593Smuzhiyun #define MV64340_SMP_SEMAPHOR7 0x27c 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /****************************************/ 144*4882a593Smuzhiyun /* CPU Sync Barrier Register */ 145*4882a593Smuzhiyun /****************************************/ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 148*4882a593Smuzhiyun #define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 149*4882a593Smuzhiyun #define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 150*4882a593Smuzhiyun #define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /****************************************/ 153*4882a593Smuzhiyun /* CPU Access Protect */ 154*4882a593Smuzhiyun /****************************************/ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 157*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188 158*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 159*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198 160*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 161*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 162*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 163*4882a593Smuzhiyun #define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /****************************************/ 167*4882a593Smuzhiyun /* CPU Error Report */ 168*4882a593Smuzhiyun /****************************************/ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define MV64340_CPU_ERROR_ADDR_LOW 0x070 171*4882a593Smuzhiyun #define MV64340_CPU_ERROR_ADDR_HIGH 0x078 172*4882a593Smuzhiyun #define MV64340_CPU_ERROR_DATA_LOW 0x128 173*4882a593Smuzhiyun #define MV64340_CPU_ERROR_DATA_HIGH 0x130 174*4882a593Smuzhiyun #define MV64340_CPU_ERROR_PARITY 0x138 175*4882a593Smuzhiyun #define MV64340_CPU_ERROR_CAUSE 0x140 176*4882a593Smuzhiyun #define MV64340_CPU_ERROR_MASK 0x148 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /****************************************/ 179*4882a593Smuzhiyun /* CPU Interface Debug Registers */ 180*4882a593Smuzhiyun /****************************************/ 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360 183*4882a593Smuzhiyun #define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368 184*4882a593Smuzhiyun #define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370 185*4882a593Smuzhiyun #define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378 186*4882a593Smuzhiyun #define MV64340_PUNIT_MMASK 0x3e4 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /****************************************/ 189*4882a593Smuzhiyun /* Integrated SRAM Registers */ 190*4882a593Smuzhiyun /****************************************/ 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define MV64340_SRAM_CONFIG 0x380 193*4882a593Smuzhiyun #define MV64340_SRAM_TEST_MODE 0X3F4 194*4882a593Smuzhiyun #define MV64340_SRAM_ERROR_CAUSE 0x388 195*4882a593Smuzhiyun #define MV64340_SRAM_ERROR_ADDR 0x390 196*4882a593Smuzhiyun #define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8 197*4882a593Smuzhiyun #define MV64340_SRAM_ERROR_DATA_LOW 0x398 198*4882a593Smuzhiyun #define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0 199*4882a593Smuzhiyun #define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /****************************************/ 202*4882a593Smuzhiyun /* SDRAM Configuration */ 203*4882a593Smuzhiyun /****************************************/ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define MV64340_SDRAM_CONFIG 0x1400 206*4882a593Smuzhiyun #define MV64340_D_UNIT_CONTROL_LOW 0x1404 207*4882a593Smuzhiyun #define MV64340_D_UNIT_CONTROL_HIGH 0x1424 208*4882a593Smuzhiyun #define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408 209*4882a593Smuzhiyun #define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c 210*4882a593Smuzhiyun #define MV64340_SDRAM_ADDR_CONTROL 0x1410 211*4882a593Smuzhiyun #define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414 212*4882a593Smuzhiyun #define MV64340_SDRAM_OPERATION 0x1418 213*4882a593Smuzhiyun #define MV64340_SDRAM_MODE 0x141c 214*4882a593Smuzhiyun #define MV64340_EXTENDED_DRAM_MODE 0x1420 215*4882a593Smuzhiyun #define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 216*4882a593Smuzhiyun #define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 217*4882a593Smuzhiyun #define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438 218*4882a593Smuzhiyun #define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 219*4882a593Smuzhiyun #define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /****************************************/ 222*4882a593Smuzhiyun /* SDRAM Error Report */ 223*4882a593Smuzhiyun /****************************************/ 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun #define MV64340_SDRAM_ERROR_DATA_LOW 0x1444 226*4882a593Smuzhiyun #define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440 227*4882a593Smuzhiyun #define MV64340_SDRAM_ERROR_ADDR 0x1450 228*4882a593Smuzhiyun #define MV64340_SDRAM_RECEIVED_ECC 0x1448 229*4882a593Smuzhiyun #define MV64340_SDRAM_CALCULATED_ECC 0x144c 230*4882a593Smuzhiyun #define MV64340_SDRAM_ECC_CONTROL 0x1454 231*4882a593Smuzhiyun #define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /******************************************/ 234*4882a593Smuzhiyun /* Controlled Delay Line (CDL) Registers */ 235*4882a593Smuzhiyun /******************************************/ 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define MV64340_DFCDL_CONFIG0 0x1480 238*4882a593Smuzhiyun #define MV64340_DFCDL_CONFIG1 0x1484 239*4882a593Smuzhiyun #define MV64340_DLL_WRITE 0x1488 240*4882a593Smuzhiyun #define MV64340_DLL_READ 0x148c 241*4882a593Smuzhiyun #define MV64340_SRAM_ADDR 0x1490 242*4882a593Smuzhiyun #define MV64340_SRAM_DATA0 0x1494 243*4882a593Smuzhiyun #define MV64340_SRAM_DATA1 0x1498 244*4882a593Smuzhiyun #define MV64340_SRAM_DATA2 0x149c 245*4882a593Smuzhiyun #define MV64340_DFCL_PROBE 0x14a0 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /******************************************/ 248*4882a593Smuzhiyun /* Debug Registers */ 249*4882a593Smuzhiyun /******************************************/ 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define MV64340_DUNIT_DEBUG_LOW 0x1460 252*4882a593Smuzhiyun #define MV64340_DUNIT_DEBUG_HIGH 0x1464 253*4882a593Smuzhiyun #define MV64340_DUNIT_MMASK 0X1b40 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /****************************************/ 256*4882a593Smuzhiyun /* Device Parameters */ 257*4882a593Smuzhiyun /****************************************/ 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #define MV64340_DEVICE_BANK0_PARAMETERS 0x45c 260*4882a593Smuzhiyun #define MV64340_DEVICE_BANK1_PARAMETERS 0x460 261*4882a593Smuzhiyun #define MV64340_DEVICE_BANK2_PARAMETERS 0x464 262*4882a593Smuzhiyun #define MV64340_DEVICE_BANK3_PARAMETERS 0x468 263*4882a593Smuzhiyun #define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c 264*4882a593Smuzhiyun #define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0 265*4882a593Smuzhiyun #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 266*4882a593Smuzhiyun #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc 267*4882a593Smuzhiyun #define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /****************************************/ 270*4882a593Smuzhiyun /* Device interrupt registers */ 271*4882a593Smuzhiyun /****************************************/ 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun #define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0 274*4882a593Smuzhiyun #define MV64340_DEVICE_INTERRUPT_MASK 0x4d4 275*4882a593Smuzhiyun #define MV64340_DEVICE_ERROR_ADDR 0x4d8 276*4882a593Smuzhiyun #define MV64340_DEVICE_ERROR_DATA 0x4dc 277*4882a593Smuzhiyun #define MV64340_DEVICE_ERROR_PARITY 0x4e0 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun /****************************************/ 280*4882a593Smuzhiyun /* Device debug registers */ 281*4882a593Smuzhiyun /****************************************/ 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun #define MV64340_DEVICE_DEBUG_LOW 0x4e4 284*4882a593Smuzhiyun #define MV64340_DEVICE_DEBUG_HIGH 0x4e8 285*4882a593Smuzhiyun #define MV64340_RUNIT_MMASK 0x4f0 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /****************************************/ 288*4882a593Smuzhiyun /* PCI Slave Address Decoding registers */ 289*4882a593Smuzhiyun /****************************************/ 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun #define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08 292*4882a593Smuzhiyun #define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88 293*4882a593Smuzhiyun #define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08 294*4882a593Smuzhiyun #define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88 295*4882a593Smuzhiyun #define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c 296*4882a593Smuzhiyun #define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c 297*4882a593Smuzhiyun #define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c 298*4882a593Smuzhiyun #define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c 299*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10 300*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90 301*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10 302*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90 303*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18 304*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98 305*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14 306*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94 307*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 308*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 309*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c 310*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c 311*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 312*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 313*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24 314*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4 315*4882a593Smuzhiyun #define MV64340_PCI_0_CPU_BAR_SIZE 0xd28 316*4882a593Smuzhiyun #define MV64340_PCI_1_CPU_BAR_SIZE 0xda8 317*4882a593Smuzhiyun #define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 318*4882a593Smuzhiyun #define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 319*4882a593Smuzhiyun #define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c 320*4882a593Smuzhiyun #define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c 321*4882a593Smuzhiyun #define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c 322*4882a593Smuzhiyun #define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc 323*4882a593Smuzhiyun #define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 324*4882a593Smuzhiyun #define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 325*4882a593Smuzhiyun #define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 326*4882a593Smuzhiyun #define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 327*4882a593Smuzhiyun #define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c 328*4882a593Smuzhiyun #define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc 329*4882a593Smuzhiyun #define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c 330*4882a593Smuzhiyun #define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc 331*4882a593Smuzhiyun #define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 332*4882a593Smuzhiyun #define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 333*4882a593Smuzhiyun #define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 334*4882a593Smuzhiyun #define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 335*4882a593Smuzhiyun #define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C 336*4882a593Smuzhiyun #define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C 337*4882a593Smuzhiyun #define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 338*4882a593Smuzhiyun #define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 339*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 340*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 341*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 342*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 343*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 344*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 345*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 346*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 347*4882a593Smuzhiyun #define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 348*4882a593Smuzhiyun #define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 349*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c 350*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc 351*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 352*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 353*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 354*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 355*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 356*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 357*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c 358*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec 359*4882a593Smuzhiyun #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 360*4882a593Smuzhiyun #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 361*4882a593Smuzhiyun #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 362*4882a593Smuzhiyun #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 363*4882a593Smuzhiyun #define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 364*4882a593Smuzhiyun #define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 365*4882a593Smuzhiyun #define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 366*4882a593Smuzhiyun #define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 367*4882a593Smuzhiyun #define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c 368*4882a593Smuzhiyun #define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc 369*4882a593Smuzhiyun #define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 370*4882a593Smuzhiyun #define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 371*4882a593Smuzhiyun #define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44 372*4882a593Smuzhiyun #define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4 373*4882a593Smuzhiyun #define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48 374*4882a593Smuzhiyun #define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /***********************************/ 377*4882a593Smuzhiyun /* PCI Control Register Map */ 378*4882a593Smuzhiyun /***********************************/ 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun #define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 381*4882a593Smuzhiyun #define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 382*4882a593Smuzhiyun #define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C 383*4882a593Smuzhiyun #define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C 384*4882a593Smuzhiyun #define MV64340_PCI_0_COMMAND 0xc00 385*4882a593Smuzhiyun #define MV64340_PCI_1_COMMAND 0xc80 386*4882a593Smuzhiyun #define MV64340_PCI_0_MODE 0xd00 387*4882a593Smuzhiyun #define MV64340_PCI_1_MODE 0xd80 388*4882a593Smuzhiyun #define MV64340_PCI_0_RETRY 0xc04 389*4882a593Smuzhiyun #define MV64340_PCI_1_RETRY 0xc84 390*4882a593Smuzhiyun #define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 391*4882a593Smuzhiyun #define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 392*4882a593Smuzhiyun #define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38 393*4882a593Smuzhiyun #define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8 394*4882a593Smuzhiyun #define MV64340_PCI_0_ARBITER_CONTROL 0x1d00 395*4882a593Smuzhiyun #define MV64340_PCI_1_ARBITER_CONTROL 0x1d80 396*4882a593Smuzhiyun #define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 397*4882a593Smuzhiyun #define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 398*4882a593Smuzhiyun #define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c 399*4882a593Smuzhiyun #define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c 400*4882a593Smuzhiyun #define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 401*4882a593Smuzhiyun #define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 402*4882a593Smuzhiyun #define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 403*4882a593Smuzhiyun #define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 404*4882a593Smuzhiyun #define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 405*4882a593Smuzhiyun #define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 406*4882a593Smuzhiyun #define MV64340_PCI_0_P2P_CONFIG 0x1d14 407*4882a593Smuzhiyun #define MV64340_PCI_1_P2P_CONFIG 0x1d94 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 410*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 411*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 412*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 413*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 414*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 415*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 416*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 417*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 418*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 419*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 420*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 421*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 422*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 423*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 424*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 425*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 426*4882a593Smuzhiyun #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 429*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 430*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 431*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 432*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 433*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 434*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 435*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 436*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 437*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 438*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 439*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 440*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 441*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 442*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 443*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 444*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 445*4882a593Smuzhiyun #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun /****************************************/ 448*4882a593Smuzhiyun /* PCI Configuration Access Registers */ 449*4882a593Smuzhiyun /****************************************/ 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun #define MV64340_PCI_0_CONFIG_ADDR 0xcf8 452*4882a593Smuzhiyun #define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc 453*4882a593Smuzhiyun #define MV64340_PCI_1_CONFIG_ADDR 0xc78 454*4882a593Smuzhiyun #define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c 455*4882a593Smuzhiyun #define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 456*4882a593Smuzhiyun #define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun /****************************************/ 459*4882a593Smuzhiyun /* PCI Error Report Registers */ 460*4882a593Smuzhiyun /****************************************/ 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun #define MV64340_PCI_0_SERR_MASK 0xc28 463*4882a593Smuzhiyun #define MV64340_PCI_1_SERR_MASK 0xca8 464*4882a593Smuzhiyun #define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40 465*4882a593Smuzhiyun #define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0 466*4882a593Smuzhiyun #define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44 467*4882a593Smuzhiyun #define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4 468*4882a593Smuzhiyun #define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48 469*4882a593Smuzhiyun #define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8 470*4882a593Smuzhiyun #define MV64340_PCI_0_ERROR_COMMAND 0x1d50 471*4882a593Smuzhiyun #define MV64340_PCI_1_ERROR_COMMAND 0x1dd0 472*4882a593Smuzhiyun #define MV64340_PCI_0_ERROR_CAUSE 0x1d58 473*4882a593Smuzhiyun #define MV64340_PCI_1_ERROR_CAUSE 0x1dd8 474*4882a593Smuzhiyun #define MV64340_PCI_0_ERROR_MASK 0x1d5c 475*4882a593Smuzhiyun #define MV64340_PCI_1_ERROR_MASK 0x1ddc 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun /****************************************/ 478*4882a593Smuzhiyun /* PCI Debug Registers */ 479*4882a593Smuzhiyun /****************************************/ 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun #define MV64340_PCI_0_MMASK 0X1D24 482*4882a593Smuzhiyun #define MV64340_PCI_1_MMASK 0X1DA4 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun /*********************************************/ 485*4882a593Smuzhiyun /* PCI Configuration, Function 0, Registers */ 486*4882a593Smuzhiyun /*********************************************/ 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun #define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000 489*4882a593Smuzhiyun #define MV64340_PCI_STATUS_AND_COMMAND 0x004 490*4882a593Smuzhiyun #define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008 491*4882a593Smuzhiyun #define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun #define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010 494*4882a593Smuzhiyun #define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014 495*4882a593Smuzhiyun #define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018 496*4882a593Smuzhiyun #define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C 497*4882a593Smuzhiyun #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 498*4882a593Smuzhiyun #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 499*4882a593Smuzhiyun #define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c 500*4882a593Smuzhiyun #define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 501*4882a593Smuzhiyun #define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034 502*4882a593Smuzhiyun #define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C 503*4882a593Smuzhiyun /* capability list */ 504*4882a593Smuzhiyun #define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 505*4882a593Smuzhiyun #define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 506*4882a593Smuzhiyun #define MV64340_PCI_VPD_ADDR 0x048 507*4882a593Smuzhiyun #define MV64340_PCI_VPD_DATA 0x04c 508*4882a593Smuzhiyun #define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050 509*4882a593Smuzhiyun #define MV64340_PCI_MSI_MESSAGE_ADDR 0x054 510*4882a593Smuzhiyun #define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 511*4882a593Smuzhiyun #define MV64340_PCI_MSI_MESSAGE_DATA 0x05c 512*4882a593Smuzhiyun #define MV64340_PCI_X_COMMAND 0x060 513*4882a593Smuzhiyun #define MV64340_PCI_X_STATUS 0x064 514*4882a593Smuzhiyun #define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun /***********************************************/ 517*4882a593Smuzhiyun /* PCI Configuration, Function 1, Registers */ 518*4882a593Smuzhiyun /***********************************************/ 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun #define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110 521*4882a593Smuzhiyun #define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114 522*4882a593Smuzhiyun #define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118 523*4882a593Smuzhiyun #define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c 524*4882a593Smuzhiyun #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 525*4882a593Smuzhiyun #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun /***********************************************/ 528*4882a593Smuzhiyun /* PCI Configuration, Function 2, Registers */ 529*4882a593Smuzhiyun /***********************************************/ 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 532*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 533*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 534*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c 535*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 536*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun /***********************************************/ 539*4882a593Smuzhiyun /* PCI Configuration, Function 3, Registers */ 540*4882a593Smuzhiyun /***********************************************/ 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 543*4882a593Smuzhiyun #define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 544*4882a593Smuzhiyun #define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 545*4882a593Smuzhiyun #define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c 546*4882a593Smuzhiyun #define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220 547*4882a593Smuzhiyun #define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun /***********************************************/ 550*4882a593Smuzhiyun /* PCI Configuration, Function 4, Registers */ 551*4882a593Smuzhiyun /***********************************************/ 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun #define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 554*4882a593Smuzhiyun #define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 555*4882a593Smuzhiyun #define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 556*4882a593Smuzhiyun #define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c 557*4882a593Smuzhiyun #define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420 558*4882a593Smuzhiyun #define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun /****************************************/ 561*4882a593Smuzhiyun /* Messaging Unit Registers (I20) */ 562*4882a593Smuzhiyun /****************************************/ 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 565*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 566*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 567*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C 568*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 569*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 570*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 571*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C 572*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 573*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 574*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 575*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 576*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 577*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 578*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 579*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 580*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 581*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C 582*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 583*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 584*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 585*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 588*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 589*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 590*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C 591*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 592*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 593*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 594*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC 595*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 596*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 597*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 598*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 599*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 600*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 601*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 602*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 603*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 604*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC 605*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 606*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 607*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 608*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 611*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 612*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 613*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C 614*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 615*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 616*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 617*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C 618*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 619*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 620*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 621*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 622*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 623*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 624*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 625*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 626*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 627*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C 628*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 629*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 630*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 631*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC 632*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 633*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 634*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 635*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C 636*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 637*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 638*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 639*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC 640*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 641*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 642*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 643*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 644*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 645*4882a593Smuzhiyun #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 646*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 647*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 648*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 649*4882a593Smuzhiyun #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC 650*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 651*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 652*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 653*4882a593Smuzhiyun #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun /****************************************/ 656*4882a593Smuzhiyun /* Ethernet Unit Registers */ 657*4882a593Smuzhiyun /****************************************/ 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun /*******************************************/ 660*4882a593Smuzhiyun /* CUNIT Registers */ 661*4882a593Smuzhiyun /*******************************************/ 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun /* Address Decoding Register Map */ 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun #define MV64340_CUNIT_BASE_ADDR_REG0 0xf200 666*4882a593Smuzhiyun #define MV64340_CUNIT_BASE_ADDR_REG1 0xf208 667*4882a593Smuzhiyun #define MV64340_CUNIT_BASE_ADDR_REG2 0xf210 668*4882a593Smuzhiyun #define MV64340_CUNIT_BASE_ADDR_REG3 0xf218 669*4882a593Smuzhiyun #define MV64340_CUNIT_SIZE0 0xf204 670*4882a593Smuzhiyun #define MV64340_CUNIT_SIZE1 0xf20c 671*4882a593Smuzhiyun #define MV64340_CUNIT_SIZE2 0xf214 672*4882a593Smuzhiyun #define MV64340_CUNIT_SIZE3 0xf21c 673*4882a593Smuzhiyun #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 674*4882a593Smuzhiyun #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 675*4882a593Smuzhiyun #define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 676*4882a593Smuzhiyun #define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254 677*4882a593Smuzhiyun #define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258 678*4882a593Smuzhiyun #define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun /* Error Report Registers */ 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun #define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310 683*4882a593Smuzhiyun #define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314 684*4882a593Smuzhiyun #define MV64340_CUNIT_ERROR_ADDR 0xf318 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun /* Cunit Control Registers */ 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun #define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300 689*4882a593Smuzhiyun #define MV64340_CUNIT_CONFIG_REG 0xb40c 690*4882a593Smuzhiyun #define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun /* Cunit Debug Registers */ 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun #define MV64340_CUNIT_DEBUG_LOW 0xf340 695*4882a593Smuzhiyun #define MV64340_CUNIT_DEBUG_HIGH 0xf344 696*4882a593Smuzhiyun #define MV64340_CUNIT_MMASK 0xf380 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun /* MPSCs Clocks Routing Registers */ 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun #define MV64340_MPSC_ROUTING_REG 0xb400 701*4882a593Smuzhiyun #define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404 702*4882a593Smuzhiyun #define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun /* MPSCs Interrupts Registers */ 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun #define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) 707*4882a593Smuzhiyun #define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3)) 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun #define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) 710*4882a593Smuzhiyun #define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) 711*4882a593Smuzhiyun #define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) 712*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) 713*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) 714*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) 715*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) 716*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) 717*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) 718*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) 719*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) 720*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) 721*4882a593Smuzhiyun #define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun /* MPSC0 Registers */ 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun /***************************************/ 727*4882a593Smuzhiyun /* SDMA Registers */ 728*4882a593Smuzhiyun /***************************************/ 729*4882a593Smuzhiyun 730*4882a593Smuzhiyun #define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) 731*4882a593Smuzhiyun #define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) 732*4882a593Smuzhiyun #define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) 733*4882a593Smuzhiyun #define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) 734*4882a593Smuzhiyun #define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun #define MV64340_SDMA_CAUSE_REG 0xb800 737*4882a593Smuzhiyun #define MV64340_SDMA_MASK_REG 0xb880 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun /* BRG Interrupts */ 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun #define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) 742*4882a593Smuzhiyun #define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) 743*4882a593Smuzhiyun #define MV64340_BRG_CAUSE_REG 0xb834 744*4882a593Smuzhiyun #define MV64340_BRG_MASK_REG 0xb8b4 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun /****************************************/ 747*4882a593Smuzhiyun /* DMA Channel Control */ 748*4882a593Smuzhiyun /****************************************/ 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_CONTROL 0x840 751*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880 752*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_CONTROL 0x844 753*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884 754*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_CONTROL 0x848 755*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888 756*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_CONTROL 0x84C 757*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun 760*4882a593Smuzhiyun /****************************************/ 761*4882a593Smuzhiyun /* IDMA Registers */ 762*4882a593Smuzhiyun /****************************************/ 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800 765*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804 766*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808 767*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C 768*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810 769*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814 770*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818 771*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c 772*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820 773*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824 774*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828 775*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C 776*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 777*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 778*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 779*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C 780*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 781*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 782*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 783*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C 784*4882a593Smuzhiyun 785*4882a593Smuzhiyun /* IDMA Address Decoding Base Address Registers */ 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG0 0xa00 788*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG1 0xa08 789*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG2 0xa10 790*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG3 0xa18 791*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG4 0xa20 792*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG5 0xa28 793*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG6 0xa30 794*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_REG7 0xa38 795*4882a593Smuzhiyun 796*4882a593Smuzhiyun /* IDMA Address Decoding Size Address Register */ 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG0 0xa04 799*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG1 0xa0c 800*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG2 0xa14 801*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG3 0xa1c 802*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG4 0xa24 803*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG5 0xa2c 804*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG6 0xa34 805*4882a593Smuzhiyun #define MV64340_DMA_SIZE_REG7 0xa3C 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun /* IDMA Address Decoding High Address Remap and Access 808*4882a593Smuzhiyun Protection Registers */ 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun #define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60 811*4882a593Smuzhiyun #define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64 812*4882a593Smuzhiyun #define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68 813*4882a593Smuzhiyun #define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C 814*4882a593Smuzhiyun #define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80 815*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 816*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 817*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 818*4882a593Smuzhiyun #define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c 819*4882a593Smuzhiyun #define MV64340_DMA_ARBITER_CONTROL 0x860 820*4882a593Smuzhiyun #define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0 821*4882a593Smuzhiyun 822*4882a593Smuzhiyun /* IDMA Headers Retarget Registers */ 823*4882a593Smuzhiyun 824*4882a593Smuzhiyun #define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84 825*4882a593Smuzhiyun #define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun /* IDMA Interrupt Register */ 828*4882a593Smuzhiyun 829*4882a593Smuzhiyun #define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0 830*4882a593Smuzhiyun #define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4 831*4882a593Smuzhiyun #define MV64340_DMA_ERROR_ADDR 0x8c8 832*4882a593Smuzhiyun #define MV64340_DMA_ERROR_SELECT 0x8cc 833*4882a593Smuzhiyun 834*4882a593Smuzhiyun /* IDMA Debug Register ( for internal use ) */ 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun #define MV64340_DMA_DEBUG_LOW 0x8e0 837*4882a593Smuzhiyun #define MV64340_DMA_DEBUG_HIGH 0x8e4 838*4882a593Smuzhiyun #define MV64340_DMA_SPARE 0xA8C 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun /****************************************/ 841*4882a593Smuzhiyun /* Timer_Counter */ 842*4882a593Smuzhiyun /****************************************/ 843*4882a593Smuzhiyun 844*4882a593Smuzhiyun #define MV64340_TIMER_COUNTER0 0x850 845*4882a593Smuzhiyun #define MV64340_TIMER_COUNTER1 0x854 846*4882a593Smuzhiyun #define MV64340_TIMER_COUNTER2 0x858 847*4882a593Smuzhiyun #define MV64340_TIMER_COUNTER3 0x85C 848*4882a593Smuzhiyun #define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864 849*4882a593Smuzhiyun #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 850*4882a593Smuzhiyun #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c 851*4882a593Smuzhiyun 852*4882a593Smuzhiyun /****************************************/ 853*4882a593Smuzhiyun /* Watchdog registers */ 854*4882a593Smuzhiyun /****************************************/ 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun #define MV64340_WATCHDOG_CONFIG_REG 0xb410 857*4882a593Smuzhiyun #define MV64340_WATCHDOG_VALUE_REG 0xb414 858*4882a593Smuzhiyun 859*4882a593Smuzhiyun /****************************************/ 860*4882a593Smuzhiyun /* I2C Registers */ 861*4882a593Smuzhiyun /****************************************/ 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun #define MV64XXX_I2C_OFFSET 0xc000 864*4882a593Smuzhiyun #define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun /****************************************/ 867*4882a593Smuzhiyun /* GPP Interface Registers */ 868*4882a593Smuzhiyun /****************************************/ 869*4882a593Smuzhiyun 870*4882a593Smuzhiyun #define MV64340_GPP_IO_CONTROL 0xf100 871*4882a593Smuzhiyun #define MV64340_GPP_LEVEL_CONTROL 0xf110 872*4882a593Smuzhiyun #define MV64340_GPP_VALUE 0xf104 873*4882a593Smuzhiyun #define MV64340_GPP_INTERRUPT_CAUSE 0xf108 874*4882a593Smuzhiyun #define MV64340_GPP_INTERRUPT_MASK0 0xf10c 875*4882a593Smuzhiyun #define MV64340_GPP_INTERRUPT_MASK1 0xf114 876*4882a593Smuzhiyun #define MV64340_GPP_VALUE_SET 0xf118 877*4882a593Smuzhiyun #define MV64340_GPP_VALUE_CLEAR 0xf11c 878*4882a593Smuzhiyun 879*4882a593Smuzhiyun /****************************************/ 880*4882a593Smuzhiyun /* Interrupt Controller Registers */ 881*4882a593Smuzhiyun /****************************************/ 882*4882a593Smuzhiyun 883*4882a593Smuzhiyun /****************************************/ 884*4882a593Smuzhiyun /* Interrupts */ 885*4882a593Smuzhiyun /****************************************/ 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun #define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004 888*4882a593Smuzhiyun #define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c 889*4882a593Smuzhiyun #define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014 890*4882a593Smuzhiyun #define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c 891*4882a593Smuzhiyun #define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024 892*4882a593Smuzhiyun #define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034 893*4882a593Smuzhiyun #define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c 894*4882a593Smuzhiyun #define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044 895*4882a593Smuzhiyun #define MV64340_INTERRUPT0_MASK_0_LOW 0x054 896*4882a593Smuzhiyun #define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c 897*4882a593Smuzhiyun #define MV64340_INTERRUPT0_SELECT_CAUSE 0x064 898*4882a593Smuzhiyun #define MV64340_INTERRUPT1_MASK_0_LOW 0x074 899*4882a593Smuzhiyun #define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c 900*4882a593Smuzhiyun #define MV64340_INTERRUPT1_SELECT_CAUSE 0x084 901*4882a593Smuzhiyun 902*4882a593Smuzhiyun /****************************************/ 903*4882a593Smuzhiyun /* MPP Interface Registers */ 904*4882a593Smuzhiyun /****************************************/ 905*4882a593Smuzhiyun 906*4882a593Smuzhiyun #define MV64340_MPP_CONTROL0 0xf000 907*4882a593Smuzhiyun #define MV64340_MPP_CONTROL1 0xf004 908*4882a593Smuzhiyun #define MV64340_MPP_CONTROL2 0xf008 909*4882a593Smuzhiyun #define MV64340_MPP_CONTROL3 0xf00c 910*4882a593Smuzhiyun 911*4882a593Smuzhiyun /****************************************/ 912*4882a593Smuzhiyun /* Serial Initialization registers */ 913*4882a593Smuzhiyun /****************************************/ 914*4882a593Smuzhiyun 915*4882a593Smuzhiyun #define MV64340_SERIAL_INIT_LAST_DATA 0xf324 916*4882a593Smuzhiyun #define MV64340_SERIAL_INIT_CONTROL 0xf328 917*4882a593Smuzhiyun #define MV64340_SERIAL_INIT_STATUS 0xf32c 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun extern void mv64340_irq_init(unsigned int base); 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun /* Watchdog Platform Device, Driver Data */ 922*4882a593Smuzhiyun #define MV64x60_WDT_NAME "mv64x60_wdt" 923*4882a593Smuzhiyun 924*4882a593Smuzhiyun struct mv64x60_wdt_pdata { 925*4882a593Smuzhiyun int timeout; /* watchdog expiry in seconds, default 10 */ 926*4882a593Smuzhiyun int bus_clk; /* bus clock in MHz, default 133 */ 927*4882a593Smuzhiyun }; 928*4882a593Smuzhiyun 929*4882a593Smuzhiyun #endif /* __ASM_MV643XX_H */ 930