1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /* Primary function overlay window definitions
3*4882a593Smuzhiyun * and service functions used by LPDDR chips
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #ifndef __LINUX_MTD_PFOW_H
6*4882a593Smuzhiyun #define __LINUX_MTD_PFOW_H
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/mtd/qinfo.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /* PFOW registers addressing */
11*4882a593Smuzhiyun /* Address of symbol "P" */
12*4882a593Smuzhiyun #define PFOW_QUERY_STRING_P 0x0000
13*4882a593Smuzhiyun /* Address of symbol "F" */
14*4882a593Smuzhiyun #define PFOW_QUERY_STRING_F 0x0002
15*4882a593Smuzhiyun /* Address of symbol "O" */
16*4882a593Smuzhiyun #define PFOW_QUERY_STRING_O 0x0004
17*4882a593Smuzhiyun /* Address of symbol "W" */
18*4882a593Smuzhiyun #define PFOW_QUERY_STRING_W 0x0006
19*4882a593Smuzhiyun /* Identification info for LPDDR chip */
20*4882a593Smuzhiyun #define PFOW_MANUFACTURER_ID 0x0020
21*4882a593Smuzhiyun #define PFOW_DEVICE_ID 0x0022
22*4882a593Smuzhiyun /* Address in PFOW where prog buffer can be found */
23*4882a593Smuzhiyun #define PFOW_PROGRAM_BUFFER_OFFSET 0x0040
24*4882a593Smuzhiyun /* Size of program buffer in words */
25*4882a593Smuzhiyun #define PFOW_PROGRAM_BUFFER_SIZE 0x0042
26*4882a593Smuzhiyun /* Address command code register */
27*4882a593Smuzhiyun #define PFOW_COMMAND_CODE 0x0080
28*4882a593Smuzhiyun /* command data register */
29*4882a593Smuzhiyun #define PFOW_COMMAND_DATA 0x0084
30*4882a593Smuzhiyun /* command address register lower address bits */
31*4882a593Smuzhiyun #define PFOW_COMMAND_ADDRESS_L 0x0088
32*4882a593Smuzhiyun /* command address register upper address bits */
33*4882a593Smuzhiyun #define PFOW_COMMAND_ADDRESS_H 0x008a
34*4882a593Smuzhiyun /* number of bytes to be proggrammed lower address bits */
35*4882a593Smuzhiyun #define PFOW_DATA_COUNT_L 0x0090
36*4882a593Smuzhiyun /* number of bytes to be proggrammed higher address bits */
37*4882a593Smuzhiyun #define PFOW_DATA_COUNT_H 0x0092
38*4882a593Smuzhiyun /* command execution register, the only possible value is 0x01 */
39*4882a593Smuzhiyun #define PFOW_COMMAND_EXECUTE 0x00c0
40*4882a593Smuzhiyun /* 0x01 should be written at this address to clear buffer */
41*4882a593Smuzhiyun #define PFOW_CLEAR_PROGRAM_BUFFER 0x00c4
42*4882a593Smuzhiyun /* device program/erase suspend register */
43*4882a593Smuzhiyun #define PFOW_PROGRAM_ERASE_SUSPEND 0x00c8
44*4882a593Smuzhiyun /* device status register */
45*4882a593Smuzhiyun #define PFOW_DSR 0x00cc
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* LPDDR memory device command codes */
48*4882a593Smuzhiyun /* They are possible values of PFOW command code register */
49*4882a593Smuzhiyun #define LPDDR_WORD_PROGRAM 0x0041
50*4882a593Smuzhiyun #define LPDDR_BUFF_PROGRAM 0x00E9
51*4882a593Smuzhiyun #define LPDDR_BLOCK_ERASE 0x0020
52*4882a593Smuzhiyun #define LPDDR_LOCK_BLOCK 0x0061
53*4882a593Smuzhiyun #define LPDDR_UNLOCK_BLOCK 0x0062
54*4882a593Smuzhiyun #define LPDDR_READ_BLOCK_LOCK_STATUS 0x0065
55*4882a593Smuzhiyun #define LPDDR_INFO_QUERY 0x0098
56*4882a593Smuzhiyun #define LPDDR_READ_OTP 0x0097
57*4882a593Smuzhiyun #define LPDDR_PROG_OTP 0x00C0
58*4882a593Smuzhiyun #define LPDDR_RESUME 0x00D0
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Defines possible value of PFOW command execution register */
61*4882a593Smuzhiyun #define LPDDR_START_EXECUTION 0x0001
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Defines possible value of PFOW program/erase suspend register */
64*4882a593Smuzhiyun #define LPDDR_SUSPEND 0x0001
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Possible values of PFOW device status register */
67*4882a593Smuzhiyun /* access R - read; RC read & clearable */
68*4882a593Smuzhiyun #define DSR_DPS (1<<1) /* RC; device protect status
69*4882a593Smuzhiyun * 0 - not protected 1 - locked */
70*4882a593Smuzhiyun #define DSR_PSS (1<<2) /* R; program suspend status;
71*4882a593Smuzhiyun * 0-prog in progress/completed,
72*4882a593Smuzhiyun * 1- prog suspended */
73*4882a593Smuzhiyun #define DSR_VPPS (1<<3) /* RC; 0-Vpp OK, * 1-Vpp low */
74*4882a593Smuzhiyun #define DSR_PROGRAM_STATUS (1<<4) /* RC; 0-successful, 1-error */
75*4882a593Smuzhiyun #define DSR_ERASE_STATUS (1<<5) /* RC; erase or blank check status;
76*4882a593Smuzhiyun * 0-success erase/blank check,
77*4882a593Smuzhiyun * 1 blank check error */
78*4882a593Smuzhiyun #define DSR_ESS (1<<6) /* R; erase suspend status;
79*4882a593Smuzhiyun * 0-erase in progress/complete,
80*4882a593Smuzhiyun * 1 erase suspended */
81*4882a593Smuzhiyun #define DSR_READY_STATUS (1<<7) /* R; Device status
82*4882a593Smuzhiyun * 0-busy,
83*4882a593Smuzhiyun * 1-ready */
84*4882a593Smuzhiyun #define DSR_RPS (0x3<<8) /* RC; region program status
85*4882a593Smuzhiyun * 00 - Success,
86*4882a593Smuzhiyun * 01-re-program attempt in region with
87*4882a593Smuzhiyun * object mode data,
88*4882a593Smuzhiyun * 10-object mode program w attempt in
89*4882a593Smuzhiyun * region with control mode data
90*4882a593Smuzhiyun * 11-attempt to program invalid half
91*4882a593Smuzhiyun * with 0x41 command */
92*4882a593Smuzhiyun #define DSR_AOS (1<<12) /* RC; 1- AO related failure */
93*4882a593Smuzhiyun #define DSR_AVAILABLE (1<<15) /* R; Device availbility
94*4882a593Smuzhiyun * 1 - Device available
95*4882a593Smuzhiyun * 0 - not available */
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* The superset of all possible error bits in DSR */
98*4882a593Smuzhiyun #define DSR_ERR 0x133A
99*4882a593Smuzhiyun
send_pfow_command(struct map_info * map,unsigned long cmd_code,unsigned long adr,unsigned long len,map_word * datum)100*4882a593Smuzhiyun static inline void send_pfow_command(struct map_info *map,
101*4882a593Smuzhiyun unsigned long cmd_code, unsigned long adr,
102*4882a593Smuzhiyun unsigned long len, map_word *datum)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun int bits_per_chip = map_bankwidth(map) * 8;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun map_write(map, CMD(cmd_code), map->pfow_base + PFOW_COMMAND_CODE);
107*4882a593Smuzhiyun map_write(map, CMD(adr & ((1<<bits_per_chip) - 1)),
108*4882a593Smuzhiyun map->pfow_base + PFOW_COMMAND_ADDRESS_L);
109*4882a593Smuzhiyun map_write(map, CMD(adr>>bits_per_chip),
110*4882a593Smuzhiyun map->pfow_base + PFOW_COMMAND_ADDRESS_H);
111*4882a593Smuzhiyun if (len) {
112*4882a593Smuzhiyun map_write(map, CMD(len & ((1<<bits_per_chip) - 1)),
113*4882a593Smuzhiyun map->pfow_base + PFOW_DATA_COUNT_L);
114*4882a593Smuzhiyun map_write(map, CMD(len>>bits_per_chip),
115*4882a593Smuzhiyun map->pfow_base + PFOW_DATA_COUNT_H);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun if (datum)
118*4882a593Smuzhiyun map_write(map, *datum, map->pfow_base + PFOW_COMMAND_DATA);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Command execution start */
121*4882a593Smuzhiyun map_write(map, CMD(LPDDR_START_EXECUTION),
122*4882a593Smuzhiyun map->pfow_base + PFOW_COMMAND_EXECUTE);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun #endif /* __LINUX_MTD_PFOW_H */
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