1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Info: 6*4882a593Smuzhiyun * Contains defines, datastructures for ndfc nand controller 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __LINUX_MTD_NDFC_H 9*4882a593Smuzhiyun #define __LINUX_MTD_NDFC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* NDFC Register definitions */ 12*4882a593Smuzhiyun #define NDFC_CMD 0x00 13*4882a593Smuzhiyun #define NDFC_ALE 0x04 14*4882a593Smuzhiyun #define NDFC_DATA 0x08 15*4882a593Smuzhiyun #define NDFC_ECC 0x10 16*4882a593Smuzhiyun #define NDFC_BCFG0 0x30 17*4882a593Smuzhiyun #define NDFC_BCFG1 0x34 18*4882a593Smuzhiyun #define NDFC_BCFG2 0x38 19*4882a593Smuzhiyun #define NDFC_BCFG3 0x3c 20*4882a593Smuzhiyun #define NDFC_CCR 0x40 21*4882a593Smuzhiyun #define NDFC_STAT 0x44 22*4882a593Smuzhiyun #define NDFC_HWCTL 0x48 23*4882a593Smuzhiyun #define NDFC_REVID 0x50 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define NDFC_STAT_IS_READY 0x01000000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ 28*4882a593Smuzhiyun #define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ 29*4882a593Smuzhiyun #define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ 30*4882a593Smuzhiyun #define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ 31*4882a593Smuzhiyun #define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ 32*4882a593Smuzhiyun #define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ 33*4882a593Smuzhiyun #define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ 34*4882a593Smuzhiyun #define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ 35*4882a593Smuzhiyun #define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ 36*4882a593Smuzhiyun #define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ 37*4882a593Smuzhiyun #define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ 38*4882a593Smuzhiyun #define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ 39*4882a593Smuzhiyun #define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ 40*4882a593Smuzhiyun #define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ 41*4882a593Smuzhiyun #define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ 42*4882a593Smuzhiyun #define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ 45*4882a593Smuzhiyun #define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ 46*4882a593Smuzhiyun #define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ 47*4882a593Smuzhiyun #define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ 48*4882a593Smuzhiyun #define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define NDFC_MAX_BANKS 4 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct ndfc_controller_settings { 53*4882a593Smuzhiyun uint32_t ccr_settings; 54*4882a593Smuzhiyun uint64_t ndfc_erpn; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct ndfc_chip_settings { 58*4882a593Smuzhiyun uint32_t bank_settings; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62