xref: /OK3568_Linux_fs/kernel/include/linux/mpu6880.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Definitions for mma8452 compass chip.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun #ifndef __MPU6880_H
6*4882a593Smuzhiyun #define __MPU6880_H
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/ioctl.h>
9*4882a593Smuzhiyun /**add***/
10*4882a593Smuzhiyun #define MPU6880_PRECISION		16
11*4882a593Smuzhiyun #define MPU6880_RANGE			2000000
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define MPU6880_SMPLRT_DIV		0x19
14*4882a593Smuzhiyun #define MPU6880_CONFIG 			0x1A
15*4882a593Smuzhiyun #define MPU6880_GYRO_CONFIG		0x1B
16*4882a593Smuzhiyun #define MPU6880_ACCEL_CONFIG	0x1C
17*4882a593Smuzhiyun #define MPU6880_ACCEL_CONFIG2	0x1D
18*4882a593Smuzhiyun #define MPU6880_LP_ACCEL_ODR   0x1E
19*4882a593Smuzhiyun #define MPU6880_WOM_THRESH	0x1F
20*4882a593Smuzhiyun #define MPU6880_FIFO_EN			0x23
21*4882a593Smuzhiyun #define MPU6880_INT_PIN_CFG		0x37
22*4882a593Smuzhiyun #define MPU6880_INT_ENABLE		0x38
23*4882a593Smuzhiyun #define MPU6880_DMP_INT_STATUS	0x39
24*4882a593Smuzhiyun #define MPU6880_INT_STATUS		0x3A
25*4882a593Smuzhiyun #define MPU6880_ACCEL_XOUT_H	0x3B
26*4882a593Smuzhiyun #define MPU6880_TEMP_OUT_H	0x41
27*4882a593Smuzhiyun #define MPU6880_GYRO_XOUT_H	0x43
28*4882a593Smuzhiyun #define MPU6880_ACCEL_INTEL_CTRL 0x69
29*4882a593Smuzhiyun #define MPU6880_USER_CTRL		0x6A
30*4882a593Smuzhiyun #define MPU6880_PWR_MGMT_1		0x6B
31*4882a593Smuzhiyun #define MPU6880_PWR_MGMT_2		0x6C
32*4882a593Smuzhiyun #define MPU6880_PRGM_STRT_ADDRH     0x70
33*4882a593Smuzhiyun #define MPU6880_FIFO_COUNTH		0x72
34*4882a593Smuzhiyun #define MPU6880_FIFO_R_W		0x74
35*4882a593Smuzhiyun #define MPU6880_WHOAMI			0x75
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define MPU6880_DEVICE_ID		0x78
38*4882a593Smuzhiyun /*------------------------------
39*4882a593Smuzhiyun 	MPU6880_CONFIG
40*4882a593Smuzhiyun --------------------------------*/
41*4882a593Smuzhiyun #define DLPF_CFG_250HZ		0x00
42*4882a593Smuzhiyun #define DLPF_CFG_184HZ		0x01
43*4882a593Smuzhiyun #define DLPF_CFG_98HZ		0x02
44*4882a593Smuzhiyun #define DLPF_CFG_41HZ		0x03
45*4882a593Smuzhiyun #define DLPF_CFG_20HZ		0x04
46*4882a593Smuzhiyun #define DLPF_CFG_10HZ		0x05
47*4882a593Smuzhiyun #define DLPF_CFG_5HZ		0x06
48*4882a593Smuzhiyun #define DLPF_CFG_3600HZ		0x07
49*4882a593Smuzhiyun #define EXT_SYNC_SET_TEMP	0x08
50*4882a593Smuzhiyun #define EXT_SYNC_SET_GYRO_X	0x10
51*4882a593Smuzhiyun #define EXT_SYNC_SET_GYRO_Y	0x18
52*4882a593Smuzhiyun #define EXT_SYNC_SET_GYRO_Z	0x20
53*4882a593Smuzhiyun #define EXT_SYNC_SET_ACCEL_X	0x28
54*4882a593Smuzhiyun #define EXT_SYNC_SET_ACCEL_Y	0x30
55*4882a593Smuzhiyun #define EXT_SYNC_SET_ACCEL_Z	0x38
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun /*------------------------------
59*4882a593Smuzhiyun 	MPU6880_GYRO_CONFIG
60*4882a593Smuzhiyun --------------------------------*/
61*4882a593Smuzhiyun #define GFSR_250DPS			(0 <<3)
62*4882a593Smuzhiyun #define GFSR_500DPS			(1 <<3)
63*4882a593Smuzhiyun #define GFSR_1000DPS		(2 <<3)
64*4882a593Smuzhiyun #define GFSR_2000DPS		(3 <<3)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /*------------------------------
67*4882a593Smuzhiyun 	MPU6880_ACCEL_CONFIG
68*4882a593Smuzhiyun --------------------------------*/
69*4882a593Smuzhiyun #define AFSR_2G		(0 <<3)
70*4882a593Smuzhiyun #define AFSR_4G		(1 <<3)
71*4882a593Smuzhiyun #define AFSR_8G		(2 <<3)
72*4882a593Smuzhiyun #define AFSR_16G	(3 <<3)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /*------------------------------
76*4882a593Smuzhiyun 	MPU6880_ACCEL_CONFIG2
77*4882a593Smuzhiyun --------------------------------*/
78*4882a593Smuzhiyun #define A_DLPF_CFG_460HZ		0x00
79*4882a593Smuzhiyun #define A_DLPF_CFG_184HZ		0x01
80*4882a593Smuzhiyun #define A_DLPF_CFG_92HZ		0x02
81*4882a593Smuzhiyun #define A_DLPF_CFG_41HZ		0x03
82*4882a593Smuzhiyun #define A_DLPF_CFG_20HZ		0x04
83*4882a593Smuzhiyun #define A_DLPF_CFG_10HZ		0x05
84*4882a593Smuzhiyun #define A_DLPF_CFG_5HZ			0x06
85*4882a593Smuzhiyun //#define A_DLPF_CFG_460HZ      0x07
86*4882a593Smuzhiyun #define BIT_FIFO_SIZE_1K                 0x40
87*4882a593Smuzhiyun #define BIT_ACCEL_FCHOICE_B		0x08
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /*------------------------------
91*4882a593Smuzhiyun 	MPU6880_LP_ACCEL_ODR
92*4882a593Smuzhiyun --------------------------------*/
93*4882a593Smuzhiyun #define LPA_CLK_P24HZ	0x0
94*4882a593Smuzhiyun #define LPA_CLK_P49HZ	0x1
95*4882a593Smuzhiyun #define LPA_CLK_P98HZ	0x2
96*4882a593Smuzhiyun #define LPA_CLK_1P95HZ	0x3
97*4882a593Smuzhiyun #define LPA_CLK_3P91HZ	0x4
98*4882a593Smuzhiyun #define LPA_CLK_7P81HZ	0x5
99*4882a593Smuzhiyun #define LPA_CLK_15P63HZ	0x6
100*4882a593Smuzhiyun #define LPA_CLK_31P25HZ	0x7
101*4882a593Smuzhiyun #define LPA_CLK_62P50HZ	0x8
102*4882a593Smuzhiyun #define LPA_CLK_125HZ	0x9
103*4882a593Smuzhiyun #define LPA_CLK_250HZ	0xa
104*4882a593Smuzhiyun #define LPA_CLK_500HZ	0xb
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /*------------------------------
108*4882a593Smuzhiyun 	MPU6880_PWR_MGMT_1
109*4882a593Smuzhiyun --------------------------------*/
110*4882a593Smuzhiyun #define BIT_H_RESET			(1<<7)
111*4882a593Smuzhiyun #define BIT_SLEEP			(1<<6)
112*4882a593Smuzhiyun #define BIT_CYCLE			(1<<5)
113*4882a593Smuzhiyun #define BIT_GYRO_STANDBY	(1<<4)
114*4882a593Smuzhiyun #define BIT_PD_PTAT			(1<<3)
115*4882a593Smuzhiyun #define BIT_CLKSEL			(1<<0)
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define CLKSEL_INTERNAL		0
118*4882a593Smuzhiyun #define CLKSEL_PLL			1
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /*------------------------------
121*4882a593Smuzhiyun 	MPU6880_PWR_MGMT_2
122*4882a593Smuzhiyun --------------------------------*/
123*4882a593Smuzhiyun #define BIT_ACCEL_STBY              0x38
124*4882a593Smuzhiyun #define BIT_GYRO_STBY               0x07
125*4882a593Smuzhiyun #define BITS_LPA_WAKE_CTRL 0xC0
126*4882a593Smuzhiyun #define BITS_LPA_WAKE_1HZ 0x00
127*4882a593Smuzhiyun #define BITS_LPA_WAKE_2HZ 0x40
128*4882a593Smuzhiyun #define BITS_LPA_WAKE_20HZ 0x80
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun #define MPU6880_PWRM1_SLEEP				0x40
131*4882a593Smuzhiyun #define MPU6880_PWRM1_GYRO_STANDBY		0x10
132*4882a593Smuzhiyun #define MPU6880_PWRM2_ACCEL_DISABLE		0x38
133*4882a593Smuzhiyun #define MPU6880_PWRM2_GYRO_DISABLE		0x07
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /*------------------------------
136*4882a593Smuzhiyun 	MPU6880_ACCEL_INTEL_CTRL
137*4882a593Smuzhiyun --------------------------------*/
138*4882a593Smuzhiyun #define BIT_ACCEL_INTEL_EN	0x80
139*4882a593Smuzhiyun #define BIT_ACCEL_INTEL_MODE	0x40
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /*------------------------------
143*4882a593Smuzhiyun 	MPU6880_USER_CTRL
144*4882a593Smuzhiyun --------------------------------*/
145*4882a593Smuzhiyun #define BIT_FIFO_RST                    0x04
146*4882a593Smuzhiyun #define BIT_DMP_RST                     0x08
147*4882a593Smuzhiyun #define BIT_I2C_MST_EN                  0x20
148*4882a593Smuzhiyun #define BIT_FIFO_EN                     0x40
149*4882a593Smuzhiyun #define BIT_DMP_EN                      0x80
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /*------------------------------
153*4882a593Smuzhiyun 	MPU6880_FIFO_EN
154*4882a593Smuzhiyun --------------------------------*/
155*4882a593Smuzhiyun #define BIT_ACCEL_OUT           0x08
156*4882a593Smuzhiyun #define BITS_GYRO_OUT           0x70
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun /*------------------------------
160*4882a593Smuzhiyun 	MPU6880_INT_PIN_CFG
161*4882a593Smuzhiyun --------------------------------*/
162*4882a593Smuzhiyun #define BIT_BYPASS_EN           0x2
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /*------------------------------
165*4882a593Smuzhiyun 	MPU6880_INT_EN/INT_STATUS
166*4882a593Smuzhiyun --------------------------------*/
167*4882a593Smuzhiyun #define BIT_FIFO_OVERLOW 	0x80
168*4882a593Smuzhiyun #define BIT_MOT_INT				0x40
169*4882a593Smuzhiyun #define BIT_MPU_RDY                 0x04
170*4882a593Smuzhiyun #define BIT_DMP_INT                 0x02
171*4882a593Smuzhiyun #define BIT_RAW_RDY                 0x01
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun #define DMP_START_ADDR           0x400
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun #define AXIS_NUM 3
179*4882a593Smuzhiyun #define AXIS_ADC_BYTE 2
180*4882a593Smuzhiyun #define SENSOR_PACKET (AXIS_NUM * AXIS_ADC_BYTE)
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun /*
187*4882a593Smuzhiyun 	self-test parameter
188*4882a593Smuzhiyun */
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun #define DEF_ST_PRECISION            1000
191*4882a593Smuzhiyun #define DEF_ST_MPU6500_ACCEL_LPF        2
192*4882a593Smuzhiyun #define DEF_STABLE_TIME_ST 50
193*4882a593Smuzhiyun #define DEF_SELFTEST_GYRO_FS            (0 << 3)
194*4882a593Smuzhiyun #define DEF_SELFTEST_ACCEL_FS           (2 << 3)
195*4882a593Smuzhiyun #define DEF_SELFTEST_6500_ACCEL_FS      (0 << 3)
196*4882a593Smuzhiyun #define DEF_SW_SELFTEST_GYRO_FS	GFSR_2000DPS
197*4882a593Smuzhiyun #define DEF_SW_SELFTEST_SENSITIVITY	\
198*4882a593Smuzhiyun 	(2000*DEF_ST_PRECISION)/32768
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun #define DEF_SW_SELFTEST_SAMPLE_COUNT 75
201*4882a593Smuzhiyun #define DEF_SW_SELFTEST_SAMPLE_TIME 75
202*4882a593Smuzhiyun #define DEF_SW_ACCEL_CAL_SAMPLE_TIME 50
203*4882a593Smuzhiyun #define DEF_SW_SKIP_COUNT 10
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #define DEF_ST_6500_STABLE_TIME         20
206*4882a593Smuzhiyun #define BYTES_PER_SENSOR        (6)
207*4882a593Smuzhiyun #define DEF_SELFTEST_SAMPLE_RATE             0
208*4882a593Smuzhiyun #define DEF_GYRO_WAIT_TIME          50
209*4882a593Smuzhiyun #define THREE_AXIS              (3)
210*4882a593Smuzhiyun #define INIT_ST_SAMPLES          200
211*4882a593Smuzhiyun #define FIFO_COUNT_BYTE         (2)
212*4882a593Smuzhiyun #define DEF_ST_TRY_TIMES            2
213*4882a593Smuzhiyun #define REG_6500_XG_ST_DATA     0x0
214*4882a593Smuzhiyun #define REG_6500_XA_ST_DATA     0xD
215*4882a593Smuzhiyun #define BITS_SELF_TEST_EN		0xE0
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun #define DEF_ST_SCALE                    (1L << 15)
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun /*---- MPU6500 Self Test Pass/Fail Criteria ----*/
220*4882a593Smuzhiyun /* Gyro Offset Max Value (dps) */
221*4882a593Smuzhiyun #define DEF_GYRO_OFFSET_MAX             20
222*4882a593Smuzhiyun /* Gyro Self Test Absolute Limits ST_AL (dps) */
223*4882a593Smuzhiyun #define DEF_GYRO_ST_AL                  60
224*4882a593Smuzhiyun /* Accel Self Test Absolute Limits ST_AL (mg) */
225*4882a593Smuzhiyun #define DEF_ACCEL_ST_AL_MIN             225
226*4882a593Smuzhiyun #define DEF_ACCEL_ST_AL_MAX             675
227*4882a593Smuzhiyun #define DEF_6500_ACCEL_ST_SHIFT_DELTA   500
228*4882a593Smuzhiyun #define DEF_6500_GYRO_CT_SHIFT_DELTA    500
229*4882a593Smuzhiyun #define DEF_ST_MPU6500_ACCEL_LPF        2
230*4882a593Smuzhiyun #define DEF_ST_6500_ACCEL_FS_MG         2000UL
231*4882a593Smuzhiyun #define DEF_SELFTEST_6500_ACCEL_FS      (0 << 3)
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun #define DEF_SELFTEST_GYRO_SENS          (32768 / 250)
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun #define  GSENSOR_DEV_PATH    "/dev/mma8452_daemon"
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun #endif
239*4882a593Smuzhiyun 
240