xref: /OK3568_Linux_fs/kernel/include/linux/mmc/sdio.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  include/linux/mmc/sdio.h
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright 2006-2007 Pierre Ossman
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef LINUX_MMC_SDIO_H
9*4882a593Smuzhiyun #define LINUX_MMC_SDIO_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /* SDIO commands                         type  argument     response */
12*4882a593Smuzhiyun #define SD_IO_SEND_OP_COND          5 /* bcr  [23:0] OCR         R4  */
13*4882a593Smuzhiyun #define SD_IO_RW_DIRECT            52 /* ac   [31:0] See below   R5  */
14*4882a593Smuzhiyun #define SD_IO_RW_EXTENDED          53 /* adtc [31:0] See below   R5  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun  * SD_IO_RW_DIRECT argument format:
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  *      [31] R/W flag
20*4882a593Smuzhiyun  *      [30:28] Function number
21*4882a593Smuzhiyun  *      [27] RAW flag
22*4882a593Smuzhiyun  *      [25:9] Register address
23*4882a593Smuzhiyun  *      [7:0] Data
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun  * SD_IO_RW_EXTENDED argument format:
28*4882a593Smuzhiyun  *
29*4882a593Smuzhiyun  *      [31] R/W flag
30*4882a593Smuzhiyun  *      [30:28] Function number
31*4882a593Smuzhiyun  *      [27] Block mode
32*4882a593Smuzhiyun  *      [26] Increment address
33*4882a593Smuzhiyun  *      [25:9] Register address
34*4882a593Smuzhiyun  *      [8:0] Byte/block count
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define R4_18V_PRESENT (1<<24)
38*4882a593Smuzhiyun #define R4_MEMORY_PRESENT (1 << 27)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun   SDIO status in R5
42*4882a593Smuzhiyun   Type
43*4882a593Smuzhiyun 	e : error bit
44*4882a593Smuzhiyun 	s : status bit
45*4882a593Smuzhiyun 	r : detected and set for the actual command response
46*4882a593Smuzhiyun 	x : detected and set during command execution. the host must poll
47*4882a593Smuzhiyun             the card by sending status command in order to read these bits.
48*4882a593Smuzhiyun   Clear condition
49*4882a593Smuzhiyun 	a : according to the card state
50*4882a593Smuzhiyun 	b : always related to the previous command. Reception of
51*4882a593Smuzhiyun             a valid command will clear it (with a delay of one command)
52*4882a593Smuzhiyun 	c : clear by read
53*4882a593Smuzhiyun  */
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define R5_COM_CRC_ERROR	(1 << 15)	/* er, b */
56*4882a593Smuzhiyun #define R5_ILLEGAL_COMMAND	(1 << 14)	/* er, b */
57*4882a593Smuzhiyun #define R5_ERROR		(1 << 11)	/* erx, c */
58*4882a593Smuzhiyun #define R5_FUNCTION_NUMBER	(1 << 9)	/* er, c */
59*4882a593Smuzhiyun #define R5_OUT_OF_RANGE		(1 << 8)	/* er, c */
60*4882a593Smuzhiyun #define R5_STATUS(x)		(x & 0xCB00)
61*4882a593Smuzhiyun #define R5_IO_CURRENT_STATE(x)	((x & 0x3000) >> 12) /* s, b */
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun  * Card Common Control Registers (CCCR)
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define SDIO_CCCR_CCCR		0x00
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define  SDIO_CCCR_REV_1_00	0	/* CCCR/FBR Version 1.00 */
70*4882a593Smuzhiyun #define  SDIO_CCCR_REV_1_10	1	/* CCCR/FBR Version 1.10 */
71*4882a593Smuzhiyun #define  SDIO_CCCR_REV_1_20	2	/* CCCR/FBR Version 1.20 */
72*4882a593Smuzhiyun #define  SDIO_CCCR_REV_3_00	3	/* CCCR/FBR Version 3.00 */
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define  SDIO_SDIO_REV_1_00	0	/* SDIO Spec Version 1.00 */
75*4882a593Smuzhiyun #define  SDIO_SDIO_REV_1_10	1	/* SDIO Spec Version 1.10 */
76*4882a593Smuzhiyun #define  SDIO_SDIO_REV_1_20	2	/* SDIO Spec Version 1.20 */
77*4882a593Smuzhiyun #define  SDIO_SDIO_REV_2_00	3	/* SDIO Spec Version 2.00 */
78*4882a593Smuzhiyun #define  SDIO_SDIO_REV_3_00	4	/* SDIO Spec Version 3.00 */
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define SDIO_CCCR_SD		0x01
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define  SDIO_SD_REV_1_01	0	/* SD Physical Spec Version 1.01 */
83*4882a593Smuzhiyun #define  SDIO_SD_REV_1_10	1	/* SD Physical Spec Version 1.10 */
84*4882a593Smuzhiyun #define  SDIO_SD_REV_2_00	2	/* SD Physical Spec Version 2.00 */
85*4882a593Smuzhiyun #define  SDIO_SD_REV_3_00	3	/* SD Physical Spev Version 3.00 */
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define SDIO_CCCR_IOEx		0x02
88*4882a593Smuzhiyun #define SDIO_CCCR_IORx		0x03
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define SDIO_CCCR_IENx		0x04	/* Function/Master Interrupt Enable */
91*4882a593Smuzhiyun #define SDIO_CCCR_INTx		0x05	/* Function Interrupt Pending */
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #define SDIO_CCCR_ABORT		0x06	/* function abort/card reset */
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define SDIO_CCCR_IF		0x07	/* bus interface controls */
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define  SDIO_BUS_WIDTH_MASK	0x03	/* data bus width setting */
98*4882a593Smuzhiyun #define  SDIO_BUS_WIDTH_1BIT	0x00
99*4882a593Smuzhiyun #define  SDIO_BUS_WIDTH_RESERVED 0x01
100*4882a593Smuzhiyun #define  SDIO_BUS_WIDTH_4BIT	0x02
101*4882a593Smuzhiyun #define  SDIO_BUS_ECSI		0x20	/* Enable continuous SPI interrupt */
102*4882a593Smuzhiyun #define  SDIO_BUS_SCSI		0x40	/* Support continuous SPI interrupt */
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #define  SDIO_BUS_ASYNC_INT	0x20
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define  SDIO_BUS_CD_DISABLE     0x80	/* disable pull-up on DAT3 (pin 1) */
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun #define SDIO_CCCR_CAPS		0x08
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_SDC	0x01	/* can do CMD52 while data transfer */
111*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_SMB	0x02	/* can do multi-block xfers (CMD53) */
112*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_SRW	0x04	/* supports read-wait protocol */
113*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_SBS	0x08	/* supports suspend/resume */
114*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_S4MI	0x10	/* interrupt during 4-bit CMD53 */
115*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_E4MI	0x20	/* enable ints during 4-bit CMD53 */
116*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_LSC	0x40	/* low speed card */
117*4882a593Smuzhiyun #define  SDIO_CCCR_CAP_4BLS	0x80	/* 4 bit low speed card */
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun #define SDIO_CCCR_CIS		0x09	/* common CIS pointer (3 bytes) */
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /* Following 4 regs are valid only if SBS is set */
122*4882a593Smuzhiyun #define SDIO_CCCR_SUSPEND	0x0c
123*4882a593Smuzhiyun #define SDIO_CCCR_SELx		0x0d
124*4882a593Smuzhiyun #define SDIO_CCCR_EXECx		0x0e
125*4882a593Smuzhiyun #define SDIO_CCCR_READYx	0x0f
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define SDIO_CCCR_BLKSIZE	0x10
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define SDIO_CCCR_POWER		0x12
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun #define  SDIO_POWER_SMPC	0x01	/* Supports Master Power Control */
132*4882a593Smuzhiyun #define  SDIO_POWER_EMPC	0x02	/* Enable Master Power Control */
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun #define SDIO_CCCR_SPEED		0x13
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define  SDIO_SPEED_SHS		0x01	/* Supports High-Speed mode */
137*4882a593Smuzhiyun #define  SDIO_SPEED_BSS_SHIFT	1
138*4882a593Smuzhiyun #define  SDIO_SPEED_BSS_MASK	(7<<SDIO_SPEED_BSS_SHIFT)
139*4882a593Smuzhiyun #define  SDIO_SPEED_SDR12	(0<<SDIO_SPEED_BSS_SHIFT)
140*4882a593Smuzhiyun #define  SDIO_SPEED_SDR25	(1<<SDIO_SPEED_BSS_SHIFT)
141*4882a593Smuzhiyun #define  SDIO_SPEED_SDR50	(2<<SDIO_SPEED_BSS_SHIFT)
142*4882a593Smuzhiyun #define  SDIO_SPEED_SDR104	(3<<SDIO_SPEED_BSS_SHIFT)
143*4882a593Smuzhiyun #define  SDIO_SPEED_DDR50	(4<<SDIO_SPEED_BSS_SHIFT)
144*4882a593Smuzhiyun #define  SDIO_SPEED_EHS		SDIO_SPEED_SDR25	/* Enable High-Speed */
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #define SDIO_CCCR_UHS		0x14
147*4882a593Smuzhiyun #define  SDIO_UHS_SDR50		0x01
148*4882a593Smuzhiyun #define  SDIO_UHS_SDR104	0x02
149*4882a593Smuzhiyun #define  SDIO_UHS_DDR50		0x04
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun #define SDIO_CCCR_DRIVE_STRENGTH 0x15
152*4882a593Smuzhiyun #define  SDIO_SDTx_MASK		0x07
153*4882a593Smuzhiyun #define  SDIO_DRIVE_SDTA	(1<<0)
154*4882a593Smuzhiyun #define  SDIO_DRIVE_SDTC	(1<<1)
155*4882a593Smuzhiyun #define  SDIO_DRIVE_SDTD	(1<<2)
156*4882a593Smuzhiyun #define  SDIO_DRIVE_DTSx_MASK	0x03
157*4882a593Smuzhiyun #define  SDIO_DRIVE_DTSx_SHIFT	4
158*4882a593Smuzhiyun #define  SDIO_DTSx_SET_TYPE_B	(0 << SDIO_DRIVE_DTSx_SHIFT)
159*4882a593Smuzhiyun #define  SDIO_DTSx_SET_TYPE_A	(1 << SDIO_DRIVE_DTSx_SHIFT)
160*4882a593Smuzhiyun #define  SDIO_DTSx_SET_TYPE_C	(2 << SDIO_DRIVE_DTSx_SHIFT)
161*4882a593Smuzhiyun #define  SDIO_DTSx_SET_TYPE_D	(3 << SDIO_DRIVE_DTSx_SHIFT)
162*4882a593Smuzhiyun /*
163*4882a593Smuzhiyun  * Function Basic Registers (FBR)
164*4882a593Smuzhiyun  */
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #define SDIO_FBR_BASE(f)	((f) * 0x100) /* base of function f's FBRs */
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun #define SDIO_FBR_STD_IF		0x00
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun #define  SDIO_FBR_SUPPORTS_CSA	0x40	/* supports Code Storage Area */
171*4882a593Smuzhiyun #define  SDIO_FBR_ENABLE_CSA	0x80	/* enable Code Storage Area */
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun #define SDIO_FBR_STD_IF_EXT	0x01
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #define SDIO_FBR_POWER		0x02
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun #define  SDIO_FBR_POWER_SPS	0x01	/* Supports Power Selection */
178*4882a593Smuzhiyun #define  SDIO_FBR_POWER_EPS	0x02	/* Enable (low) Power Selection */
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun #define SDIO_FBR_CIS		0x09	/* CIS pointer (3 bytes) */
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #define SDIO_FBR_CSA		0x0C	/* CSA pointer (3 bytes) */
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun #define SDIO_FBR_CSA_DATA	0x0F
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun #define SDIO_FBR_BLKSIZE	0x10	/* block size (2 bytes) */
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun #endif /* LINUX_MMC_SDIO_H */
190