xref: /OK3568_Linux_fs/kernel/include/linux/mmc/card.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  linux/include/linux/mmc/card.h
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Card driver specific definitions.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun #ifndef LINUX_MMC_CARD_H
8*4882a593Smuzhiyun #define LINUX_MMC_CARD_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
12*4882a593Smuzhiyun #include <linux/android_kabi.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun struct mmc_cid {
15*4882a593Smuzhiyun 	unsigned int		manfid;
16*4882a593Smuzhiyun 	char			prod_name[8];
17*4882a593Smuzhiyun 	unsigned char		prv;
18*4882a593Smuzhiyun 	unsigned int		serial;
19*4882a593Smuzhiyun 	unsigned short		oemid;
20*4882a593Smuzhiyun 	unsigned short		year;
21*4882a593Smuzhiyun 	unsigned char		hwrev;
22*4882a593Smuzhiyun 	unsigned char		fwrev;
23*4882a593Smuzhiyun 	unsigned char		month;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun struct mmc_csd {
27*4882a593Smuzhiyun 	unsigned char		structure;
28*4882a593Smuzhiyun 	unsigned char		mmca_vsn;
29*4882a593Smuzhiyun 	unsigned short		cmdclass;
30*4882a593Smuzhiyun 	unsigned short		taac_clks;
31*4882a593Smuzhiyun 	unsigned int		taac_ns;
32*4882a593Smuzhiyun 	unsigned int		c_size;
33*4882a593Smuzhiyun 	unsigned int		r2w_factor;
34*4882a593Smuzhiyun 	unsigned int		max_dtr;
35*4882a593Smuzhiyun 	unsigned int		erase_size;		/* In sectors */
36*4882a593Smuzhiyun 	unsigned int		read_blkbits;
37*4882a593Smuzhiyun 	unsigned int		write_blkbits;
38*4882a593Smuzhiyun 	unsigned int		capacity;
39*4882a593Smuzhiyun 	unsigned int		read_partial:1,
40*4882a593Smuzhiyun 				read_misalign:1,
41*4882a593Smuzhiyun 				write_partial:1,
42*4882a593Smuzhiyun 				write_misalign:1,
43*4882a593Smuzhiyun 				dsr_imp:1;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun struct mmc_ext_csd {
47*4882a593Smuzhiyun 	u8			rev;
48*4882a593Smuzhiyun 	u8			erase_group_def;
49*4882a593Smuzhiyun 	u8			sec_feature_support;
50*4882a593Smuzhiyun 	u8			rel_sectors;
51*4882a593Smuzhiyun 	u8			rel_param;
52*4882a593Smuzhiyun 	bool			enhanced_rpmb_supported;
53*4882a593Smuzhiyun 	u8			part_config;
54*4882a593Smuzhiyun 	u8			cache_ctrl;
55*4882a593Smuzhiyun 	u8			rst_n_function;
56*4882a593Smuzhiyun 	u8			max_packed_writes;
57*4882a593Smuzhiyun 	u8			max_packed_reads;
58*4882a593Smuzhiyun 	u8			packed_event_en;
59*4882a593Smuzhiyun 	unsigned int		part_time;		/* Units: ms */
60*4882a593Smuzhiyun 	unsigned int		sa_timeout;		/* Units: 100ns */
61*4882a593Smuzhiyun 	unsigned int		generic_cmd6_time;	/* Units: 10ms */
62*4882a593Smuzhiyun 	unsigned int            power_off_longtime;     /* Units: ms */
63*4882a593Smuzhiyun 	u8			power_off_notification;	/* state */
64*4882a593Smuzhiyun 	unsigned int		hs_max_dtr;
65*4882a593Smuzhiyun 	unsigned int		hs200_max_dtr;
66*4882a593Smuzhiyun #define MMC_HIGH_26_MAX_DTR	26000000
67*4882a593Smuzhiyun #define MMC_HIGH_52_MAX_DTR	52000000
68*4882a593Smuzhiyun #define MMC_HIGH_DDR_MAX_DTR	52000000
69*4882a593Smuzhiyun #define MMC_HS200_MAX_DTR	200000000
70*4882a593Smuzhiyun 	unsigned int		sectors;
71*4882a593Smuzhiyun 	unsigned int		hc_erase_size;		/* In sectors */
72*4882a593Smuzhiyun 	unsigned int		hc_erase_timeout;	/* In milliseconds */
73*4882a593Smuzhiyun 	unsigned int		sec_trim_mult;	/* Secure trim multiplier  */
74*4882a593Smuzhiyun 	unsigned int		sec_erase_mult;	/* Secure erase multiplier */
75*4882a593Smuzhiyun 	unsigned int		trim_timeout;		/* In milliseconds */
76*4882a593Smuzhiyun 	bool			partition_setting_completed;	/* enable bit */
77*4882a593Smuzhiyun 	unsigned long long	enhanced_area_offset;	/* Units: Byte */
78*4882a593Smuzhiyun 	unsigned int		enhanced_area_size;	/* Units: KB */
79*4882a593Smuzhiyun 	unsigned int		cache_size;		/* Units: KB */
80*4882a593Smuzhiyun 	bool			hpi_en;			/* HPI enablebit */
81*4882a593Smuzhiyun 	bool			hpi;			/* HPI support bit */
82*4882a593Smuzhiyun 	unsigned int		hpi_cmd;		/* cmd used as HPI */
83*4882a593Smuzhiyun 	bool			bkops;		/* background support bit */
84*4882a593Smuzhiyun 	bool			man_bkops_en;	/* manual bkops enable bit */
85*4882a593Smuzhiyun 	bool			auto_bkops_en;	/* auto bkops enable bit */
86*4882a593Smuzhiyun 	unsigned int            data_sector_size;       /* 512 bytes or 4KB */
87*4882a593Smuzhiyun 	unsigned int            data_tag_unit_size;     /* DATA TAG UNIT size */
88*4882a593Smuzhiyun 	unsigned int		boot_ro_lock;		/* ro lock support */
89*4882a593Smuzhiyun 	bool			boot_ro_lockable;
90*4882a593Smuzhiyun 	bool			ffu_capable;	/* Firmware upgrade support */
91*4882a593Smuzhiyun 	bool			cmdq_en;	/* Command Queue enabled */
92*4882a593Smuzhiyun 	bool			cmdq_support;	/* Command Queue supported */
93*4882a593Smuzhiyun 	unsigned int		cmdq_depth;	/* Command Queue depth */
94*4882a593Smuzhiyun #define MMC_FIRMWARE_LEN 8
95*4882a593Smuzhiyun 	u8			fwrev[MMC_FIRMWARE_LEN];  /* FW version */
96*4882a593Smuzhiyun 	u8			raw_exception_status;	/* 54 */
97*4882a593Smuzhiyun 	u8			raw_partition_support;	/* 160 */
98*4882a593Smuzhiyun 	u8			raw_rpmb_size_mult;	/* 168 */
99*4882a593Smuzhiyun 	u8			raw_erased_mem_count;	/* 181 */
100*4882a593Smuzhiyun 	u8			strobe_support;		/* 184 */
101*4882a593Smuzhiyun 	u8			raw_ext_csd_structure;	/* 194 */
102*4882a593Smuzhiyun 	u8			raw_card_type;		/* 196 */
103*4882a593Smuzhiyun 	u8			raw_driver_strength;	/* 197 */
104*4882a593Smuzhiyun 	u8			out_of_int_time;	/* 198 */
105*4882a593Smuzhiyun 	u8			raw_pwr_cl_52_195;	/* 200 */
106*4882a593Smuzhiyun 	u8			raw_pwr_cl_26_195;	/* 201 */
107*4882a593Smuzhiyun 	u8			raw_pwr_cl_52_360;	/* 202 */
108*4882a593Smuzhiyun 	u8			raw_pwr_cl_26_360;	/* 203 */
109*4882a593Smuzhiyun 	u8			raw_s_a_timeout;	/* 217 */
110*4882a593Smuzhiyun 	u8			raw_hc_erase_gap_size;	/* 221 */
111*4882a593Smuzhiyun 	u8			raw_erase_timeout_mult;	/* 223 */
112*4882a593Smuzhiyun 	u8			raw_hc_erase_grp_size;	/* 224 */
113*4882a593Smuzhiyun 	u8			raw_sec_trim_mult;	/* 229 */
114*4882a593Smuzhiyun 	u8			raw_sec_erase_mult;	/* 230 */
115*4882a593Smuzhiyun 	u8			raw_sec_feature_support;/* 231 */
116*4882a593Smuzhiyun 	u8			raw_trim_mult;		/* 232 */
117*4882a593Smuzhiyun 	u8			raw_pwr_cl_200_195;	/* 236 */
118*4882a593Smuzhiyun 	u8			raw_pwr_cl_200_360;	/* 237 */
119*4882a593Smuzhiyun 	u8			raw_pwr_cl_ddr_52_195;	/* 238 */
120*4882a593Smuzhiyun 	u8			raw_pwr_cl_ddr_52_360;	/* 239 */
121*4882a593Smuzhiyun 	u8			raw_pwr_cl_ddr_200_360;	/* 253 */
122*4882a593Smuzhiyun 	u8			raw_bkops_status;	/* 246 */
123*4882a593Smuzhiyun 	u8			raw_sectors[4];		/* 212 - 4 bytes */
124*4882a593Smuzhiyun 	u8			pre_eol_info;		/* 267 */
125*4882a593Smuzhiyun 	u8			device_life_time_est_typ_a;	/* 268 */
126*4882a593Smuzhiyun 	u8			device_life_time_est_typ_b;	/* 269 */
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	unsigned int            feature_support;
129*4882a593Smuzhiyun #define MMC_DISCARD_FEATURE	BIT(0)                  /* CMD38 feature */
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun struct sd_scr {
133*4882a593Smuzhiyun 	unsigned char		sda_vsn;
134*4882a593Smuzhiyun 	unsigned char		sda_spec3;
135*4882a593Smuzhiyun 	unsigned char		sda_spec4;
136*4882a593Smuzhiyun 	unsigned char		sda_specx;
137*4882a593Smuzhiyun 	unsigned char		bus_widths;
138*4882a593Smuzhiyun #define SD_SCR_BUS_WIDTH_1	(1<<0)
139*4882a593Smuzhiyun #define SD_SCR_BUS_WIDTH_4	(1<<2)
140*4882a593Smuzhiyun 	unsigned char		cmds;
141*4882a593Smuzhiyun #define SD_SCR_CMD20_SUPPORT   (1<<0)
142*4882a593Smuzhiyun #define SD_SCR_CMD23_SUPPORT   (1<<1)
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun struct sd_ssr {
146*4882a593Smuzhiyun 	unsigned int		au;			/* In sectors */
147*4882a593Smuzhiyun 	unsigned int		erase_timeout;		/* In milliseconds */
148*4882a593Smuzhiyun 	unsigned int		erase_offset;		/* In milliseconds */
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun struct sd_switch_caps {
152*4882a593Smuzhiyun 	unsigned int		hs_max_dtr;
153*4882a593Smuzhiyun 	unsigned int		uhs_max_dtr;
154*4882a593Smuzhiyun #define HIGH_SPEED_MAX_DTR	50000000
155*4882a593Smuzhiyun #define UHS_SDR104_MAX_DTR	208000000
156*4882a593Smuzhiyun #define UHS_SDR50_MAX_DTR	100000000
157*4882a593Smuzhiyun #define UHS_DDR50_MAX_DTR	50000000
158*4882a593Smuzhiyun #define UHS_SDR25_MAX_DTR	UHS_DDR50_MAX_DTR
159*4882a593Smuzhiyun #define UHS_SDR12_MAX_DTR	25000000
160*4882a593Smuzhiyun #define DEFAULT_SPEED_MAX_DTR	UHS_SDR12_MAX_DTR
161*4882a593Smuzhiyun 	unsigned int		sd3_bus_mode;
162*4882a593Smuzhiyun #define UHS_SDR12_BUS_SPEED	0
163*4882a593Smuzhiyun #define HIGH_SPEED_BUS_SPEED	1
164*4882a593Smuzhiyun #define UHS_SDR25_BUS_SPEED	1
165*4882a593Smuzhiyun #define UHS_SDR50_BUS_SPEED	2
166*4882a593Smuzhiyun #define UHS_SDR104_BUS_SPEED	3
167*4882a593Smuzhiyun #define UHS_DDR50_BUS_SPEED	4
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun #define SD_MODE_HIGH_SPEED	(1 << HIGH_SPEED_BUS_SPEED)
170*4882a593Smuzhiyun #define SD_MODE_UHS_SDR12	(1 << UHS_SDR12_BUS_SPEED)
171*4882a593Smuzhiyun #define SD_MODE_UHS_SDR25	(1 << UHS_SDR25_BUS_SPEED)
172*4882a593Smuzhiyun #define SD_MODE_UHS_SDR50	(1 << UHS_SDR50_BUS_SPEED)
173*4882a593Smuzhiyun #define SD_MODE_UHS_SDR104	(1 << UHS_SDR104_BUS_SPEED)
174*4882a593Smuzhiyun #define SD_MODE_UHS_DDR50	(1 << UHS_DDR50_BUS_SPEED)
175*4882a593Smuzhiyun 	unsigned int		sd3_drv_type;
176*4882a593Smuzhiyun #define SD_DRIVER_TYPE_B	0x01
177*4882a593Smuzhiyun #define SD_DRIVER_TYPE_A	0x02
178*4882a593Smuzhiyun #define SD_DRIVER_TYPE_C	0x04
179*4882a593Smuzhiyun #define SD_DRIVER_TYPE_D	0x08
180*4882a593Smuzhiyun 	unsigned int		sd3_curr_limit;
181*4882a593Smuzhiyun #define SD_SET_CURRENT_LIMIT_200	0
182*4882a593Smuzhiyun #define SD_SET_CURRENT_LIMIT_400	1
183*4882a593Smuzhiyun #define SD_SET_CURRENT_LIMIT_600	2
184*4882a593Smuzhiyun #define SD_SET_CURRENT_LIMIT_800	3
185*4882a593Smuzhiyun #define SD_SET_CURRENT_NO_CHANGE	(-1)
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun #define SD_MAX_CURRENT_200	(1 << SD_SET_CURRENT_LIMIT_200)
188*4882a593Smuzhiyun #define SD_MAX_CURRENT_400	(1 << SD_SET_CURRENT_LIMIT_400)
189*4882a593Smuzhiyun #define SD_MAX_CURRENT_600	(1 << SD_SET_CURRENT_LIMIT_600)
190*4882a593Smuzhiyun #define SD_MAX_CURRENT_800	(1 << SD_SET_CURRENT_LIMIT_800)
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun struct sdio_cccr {
194*4882a593Smuzhiyun 	unsigned int		sdio_vsn;
195*4882a593Smuzhiyun 	unsigned int		sd_vsn;
196*4882a593Smuzhiyun 	unsigned int		multi_block:1,
197*4882a593Smuzhiyun 				low_speed:1,
198*4882a593Smuzhiyun 				wide_bus:1,
199*4882a593Smuzhiyun 				high_power:1,
200*4882a593Smuzhiyun 				high_speed:1,
201*4882a593Smuzhiyun 				disable_cd:1;
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun struct sdio_cis {
205*4882a593Smuzhiyun 	unsigned short		vendor;
206*4882a593Smuzhiyun 	unsigned short		device;
207*4882a593Smuzhiyun 	unsigned short		blksize;
208*4882a593Smuzhiyun 	unsigned int		max_dtr;
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun struct mmc_host;
212*4882a593Smuzhiyun struct sdio_func;
213*4882a593Smuzhiyun struct sdio_func_tuple;
214*4882a593Smuzhiyun struct mmc_queue_req;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun #define SDIO_MAX_FUNCS		7
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun /* The number of MMC physical partitions.  These consist of:
219*4882a593Smuzhiyun  * boot partitions (2), general purpose partitions (4) and
220*4882a593Smuzhiyun  * RPMB partition (1) in MMC v4.4.
221*4882a593Smuzhiyun  */
222*4882a593Smuzhiyun #define MMC_NUM_BOOT_PARTITION	2
223*4882a593Smuzhiyun #define MMC_NUM_GP_PARTITION	4
224*4882a593Smuzhiyun #define MMC_NUM_PHY_PARTITION	7
225*4882a593Smuzhiyun #define MAX_MMC_PART_NAME_LEN	20
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun  * MMC Physical partitions
229*4882a593Smuzhiyun  */
230*4882a593Smuzhiyun struct mmc_part {
231*4882a593Smuzhiyun 	u64		size;	/* partition size (in bytes) */
232*4882a593Smuzhiyun 	unsigned int	part_cfg;	/* partition type */
233*4882a593Smuzhiyun 	char	name[MAX_MMC_PART_NAME_LEN];
234*4882a593Smuzhiyun 	bool	force_ro;	/* to make boot parts RO by default */
235*4882a593Smuzhiyun 	unsigned int	area_type;
236*4882a593Smuzhiyun #define MMC_BLK_DATA_AREA_MAIN	(1<<0)
237*4882a593Smuzhiyun #define MMC_BLK_DATA_AREA_BOOT	(1<<1)
238*4882a593Smuzhiyun #define MMC_BLK_DATA_AREA_GP	(1<<2)
239*4882a593Smuzhiyun #define MMC_BLK_DATA_AREA_RPMB	(1<<3)
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun /*
245*4882a593Smuzhiyun  * MMC device
246*4882a593Smuzhiyun  */
247*4882a593Smuzhiyun struct mmc_card {
248*4882a593Smuzhiyun 	struct mmc_host		*host;		/* the host this device belongs to */
249*4882a593Smuzhiyun 	struct device		dev;		/* the device */
250*4882a593Smuzhiyun 	u32			ocr;		/* the current OCR setting */
251*4882a593Smuzhiyun 	unsigned int		rca;		/* relative card address of device */
252*4882a593Smuzhiyun 	unsigned int		type;		/* card type */
253*4882a593Smuzhiyun #define MMC_TYPE_MMC		0		/* MMC card */
254*4882a593Smuzhiyun #define MMC_TYPE_SD		1		/* SD card */
255*4882a593Smuzhiyun #define MMC_TYPE_SDIO		2		/* SDIO card */
256*4882a593Smuzhiyun #define MMC_TYPE_SD_COMBO	3		/* SD combo (IO+mem) card */
257*4882a593Smuzhiyun 	unsigned int		state;		/* (our) card state */
258*4882a593Smuzhiyun 	unsigned int		quirks; 	/* card quirks */
259*4882a593Smuzhiyun 	unsigned int		quirk_max_rate;	/* max rate set by quirks */
260*4882a593Smuzhiyun #define MMC_QUIRK_LENIENT_FN0	(1<<0)		/* allow SDIO FN0 writes outside of the VS CCCR range */
261*4882a593Smuzhiyun #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1)	/* use func->cur_blksize */
262*4882a593Smuzhiyun 						/* for byte mode */
263*4882a593Smuzhiyun #define MMC_QUIRK_NONSTD_SDIO	(1<<2)		/* non-standard SDIO card attached */
264*4882a593Smuzhiyun 						/* (missing CIA registers) */
265*4882a593Smuzhiyun #define MMC_QUIRK_NONSTD_FUNC_IF (1<<4)		/* SDIO card has nonstd function interfaces */
266*4882a593Smuzhiyun #define MMC_QUIRK_DISABLE_CD	(1<<5)		/* disconnect CD/DAT[3] resistor */
267*4882a593Smuzhiyun #define MMC_QUIRK_INAND_CMD38	(1<<6)		/* iNAND devices have broken CMD38 */
268*4882a593Smuzhiyun #define MMC_QUIRK_BLK_NO_CMD23	(1<<7)		/* Avoid CMD23 for regular multiblock */
269*4882a593Smuzhiyun #define MMC_QUIRK_BROKEN_BYTE_MODE_512 (1<<8)	/* Avoid sending 512 bytes in */
270*4882a593Smuzhiyun 						/* byte mode */
271*4882a593Smuzhiyun #define MMC_QUIRK_LONG_READ_TIME (1<<9)		/* Data read time > CSD says */
272*4882a593Smuzhiyun #define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10)	/* Skip secure for erase/trim */
273*4882a593Smuzhiyun #define MMC_QUIRK_BROKEN_IRQ_POLLING	(1<<11)	/* Polling SDIO_CCCR_INTx could create a fake interrupt */
274*4882a593Smuzhiyun #define MMC_QUIRK_TRIM_BROKEN	(1<<12)		/* Skip trim */
275*4882a593Smuzhiyun #define MMC_QUIRK_BROKEN_HPI	(1<<13)		/* Disable broken HPI support */
276*4882a593Smuzhiyun #define MMC_QUIRK_BROKEN_SD_DISCARD	(1<<14)	/* Disable broken SD discard support */
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	bool			reenable_cmdq;	/* Re-enable Command Queue */
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	unsigned int		erase_size;	/* erase size in sectors */
281*4882a593Smuzhiyun  	unsigned int		erase_shift;	/* if erase unit is power 2 */
282*4882a593Smuzhiyun  	unsigned int		pref_erase;	/* in sectors */
283*4882a593Smuzhiyun 	unsigned int		eg_boundary;	/* don't cross erase-group boundaries */
284*4882a593Smuzhiyun 	unsigned int		erase_arg;	/* erase / trim / discard */
285*4882a593Smuzhiyun  	u8			erased_byte;	/* value of erased bytes */
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	u32			raw_cid[4];	/* raw card CID */
288*4882a593Smuzhiyun 	u32			raw_csd[4];	/* raw card CSD */
289*4882a593Smuzhiyun 	u32			raw_scr[2];	/* raw card SCR */
290*4882a593Smuzhiyun 	u32			raw_ssr[16];	/* raw card SSR */
291*4882a593Smuzhiyun 	struct mmc_cid		cid;		/* card identification */
292*4882a593Smuzhiyun 	struct mmc_csd		csd;		/* card specific */
293*4882a593Smuzhiyun 	struct mmc_ext_csd	ext_csd;	/* mmc v4 extended card specific */
294*4882a593Smuzhiyun 	struct sd_scr		scr;		/* extra SD information */
295*4882a593Smuzhiyun 	struct sd_ssr		ssr;		/* yet more SD information */
296*4882a593Smuzhiyun 	struct sd_switch_caps	sw_caps;	/* switch (CMD6) caps */
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	unsigned int		sdio_funcs;	/* number of SDIO functions */
299*4882a593Smuzhiyun 	atomic_t		sdio_funcs_probed; /* number of probed SDIO funcs */
300*4882a593Smuzhiyun 	struct sdio_cccr	cccr;		/* common card info */
301*4882a593Smuzhiyun 	struct sdio_cis		cis;		/* common tuple info */
302*4882a593Smuzhiyun 	struct sdio_func	*sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */
303*4882a593Smuzhiyun 	struct sdio_func	*sdio_single_irq; /* SDIO function when only one IRQ active */
304*4882a593Smuzhiyun 	u8			major_rev;	/* major revision number */
305*4882a593Smuzhiyun 	u8			minor_rev;	/* minor revision number */
306*4882a593Smuzhiyun 	unsigned		num_info;	/* number of info strings */
307*4882a593Smuzhiyun 	const char		**info;		/* info strings */
308*4882a593Smuzhiyun 	struct sdio_func_tuple	*tuples;	/* unknown common tuples */
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	unsigned int		sd_bus_speed;	/* Bus Speed Mode set for the card */
311*4882a593Smuzhiyun 	unsigned int		mmc_avail_type;	/* supported device type by both host and card */
312*4882a593Smuzhiyun 	unsigned int		drive_strength;	/* for UHS-I, HS200 or HS400 */
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	struct dentry		*debugfs_root;
315*4882a593Smuzhiyun 	struct mmc_part	part[MMC_NUM_PHY_PARTITION]; /* physical partitions */
316*4882a593Smuzhiyun 	unsigned int    nr_parts;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	unsigned int		bouncesz;	/* Bounce buffer size */
319*4882a593Smuzhiyun 	struct workqueue_struct *complete_wq;	/* Private workqueue */
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
322*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(2);
323*4882a593Smuzhiyun 	ANDROID_VENDOR_DATA(1);
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun 
mmc_large_sector(struct mmc_card * card)326*4882a593Smuzhiyun static inline bool mmc_large_sector(struct mmc_card *card)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun 	return card->ext_csd.data_sector_size == 4096;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun bool mmc_card_is_blockaddr(struct mmc_card *card);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun #define mmc_card_mmc(c)		((c)->type == MMC_TYPE_MMC)
334*4882a593Smuzhiyun #define mmc_card_sd(c)		((c)->type == MMC_TYPE_SD)
335*4882a593Smuzhiyun #define mmc_card_sdio(c)	((c)->type == MMC_TYPE_SDIO)
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun #endif /* LINUX_MMC_CARD_H */
338