1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2*4882a593Smuzhiyun /* Copyright (c) 2018 Mellanox Technologies. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef MLX5_CORE_EQ_H
5*4882a593Smuzhiyun #define MLX5_CORE_EQ_H
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define MLX5_IRQ_VEC_COMP_BASE 1
8*4882a593Smuzhiyun #define MLX5_NUM_CMD_EQE (32)
9*4882a593Smuzhiyun #define MLX5_NUM_ASYNC_EQE (0x1000)
10*4882a593Smuzhiyun #define MLX5_NUM_SPARE_EQE (0x80)
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct mlx5_eq;
13*4882a593Smuzhiyun struct mlx5_core_dev;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct mlx5_eq_param {
16*4882a593Smuzhiyun u8 irq_index;
17*4882a593Smuzhiyun int nent;
18*4882a593Smuzhiyun u64 mask[4];
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct mlx5_eq *
22*4882a593Smuzhiyun mlx5_eq_create_generic(struct mlx5_core_dev *dev, struct mlx5_eq_param *param);
23*4882a593Smuzhiyun int
24*4882a593Smuzhiyun mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
25*4882a593Smuzhiyun int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
26*4882a593Smuzhiyun struct notifier_block *nb);
27*4882a593Smuzhiyun void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
28*4882a593Smuzhiyun struct notifier_block *nb);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc);
31*4882a593Smuzhiyun void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* The HCA will think the queue has overflowed if we
34*4882a593Smuzhiyun * don't tell it we've been processing events. We
35*4882a593Smuzhiyun * create EQs with MLX5_NUM_SPARE_EQE extra entries,
36*4882a593Smuzhiyun * so we must update our consumer index at
37*4882a593Smuzhiyun * least that often.
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * mlx5_eq_update_cc must be called on every EQE @EQ irq handler
40*4882a593Smuzhiyun */
mlx5_eq_update_cc(struct mlx5_eq * eq,u32 cc)41*4882a593Smuzhiyun static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun if (unlikely(cc >= MLX5_NUM_SPARE_EQE)) {
44*4882a593Smuzhiyun mlx5_eq_update_ci(eq, cc, 0);
45*4882a593Smuzhiyun cc = 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun return cc;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun struct mlx5_nb {
51*4882a593Smuzhiyun struct notifier_block nb;
52*4882a593Smuzhiyun u8 event_type;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define mlx5_nb_cof(ptr, type, member) \
56*4882a593Smuzhiyun (container_of(container_of(ptr, struct mlx5_nb, nb), type, member))
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define MLX5_NB_INIT(name, handler, event) do { \
59*4882a593Smuzhiyun (name)->nb.notifier_call = handler; \
60*4882a593Smuzhiyun (name)->event_type = MLX5_EVENT_TYPE_##event; \
61*4882a593Smuzhiyun } while (0)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #endif /* MLX5_CORE_EQ_H */
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