1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifndef __MLX5_ACCEL_H__
35*4882a593Smuzhiyun #define __MLX5_ACCEL_H__
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include <linux/mlx5/driver.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun enum mlx5_accel_esp_aes_gcm_keymat_iv_algo {
40*4882a593Smuzhiyun MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun enum mlx5_accel_esp_flags {
44*4882a593Smuzhiyun MLX5_ACCEL_ESP_FLAGS_TUNNEL = 0, /* Default */
45*4882a593Smuzhiyun MLX5_ACCEL_ESP_FLAGS_TRANSPORT = 1UL << 0,
46*4882a593Smuzhiyun MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED = 1UL << 1,
47*4882a593Smuzhiyun MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP = 1UL << 2,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun enum mlx5_accel_esp_action {
51*4882a593Smuzhiyun MLX5_ACCEL_ESP_ACTION_DECRYPT,
52*4882a593Smuzhiyun MLX5_ACCEL_ESP_ACTION_ENCRYPT,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun enum mlx5_accel_esp_keymats {
56*4882a593Smuzhiyun MLX5_ACCEL_ESP_KEYMAT_AES_NONE,
57*4882a593Smuzhiyun MLX5_ACCEL_ESP_KEYMAT_AES_GCM,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun enum mlx5_accel_esp_replay {
61*4882a593Smuzhiyun MLX5_ACCEL_ESP_REPLAY_NONE,
62*4882a593Smuzhiyun MLX5_ACCEL_ESP_REPLAY_BMP,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct aes_gcm_keymat {
66*4882a593Smuzhiyun u64 seq_iv;
67*4882a593Smuzhiyun enum mlx5_accel_esp_aes_gcm_keymat_iv_algo iv_algo;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun u32 salt;
70*4882a593Smuzhiyun u32 icv_len;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun u32 key_len;
73*4882a593Smuzhiyun u32 aes_key[256 / 32];
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct mlx5_accel_esp_xfrm_attrs {
77*4882a593Smuzhiyun enum mlx5_accel_esp_action action;
78*4882a593Smuzhiyun u32 esn;
79*4882a593Smuzhiyun __be32 spi;
80*4882a593Smuzhiyun u32 seq;
81*4882a593Smuzhiyun u32 tfc_pad;
82*4882a593Smuzhiyun u32 flags;
83*4882a593Smuzhiyun u32 sa_handle;
84*4882a593Smuzhiyun enum mlx5_accel_esp_replay replay_type;
85*4882a593Smuzhiyun union {
86*4882a593Smuzhiyun struct {
87*4882a593Smuzhiyun u32 size;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun } bmp;
90*4882a593Smuzhiyun } replay;
91*4882a593Smuzhiyun enum mlx5_accel_esp_keymats keymat_type;
92*4882a593Smuzhiyun union {
93*4882a593Smuzhiyun struct aes_gcm_keymat aes_gcm;
94*4882a593Smuzhiyun } keymat;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun union {
97*4882a593Smuzhiyun __be32 a4;
98*4882a593Smuzhiyun __be32 a6[4];
99*4882a593Smuzhiyun } saddr;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun union {
102*4882a593Smuzhiyun __be32 a4;
103*4882a593Smuzhiyun __be32 a6[4];
104*4882a593Smuzhiyun } daddr;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun u8 is_ipv6;
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun struct mlx5_accel_esp_xfrm {
110*4882a593Smuzhiyun struct mlx5_core_dev *mdev;
111*4882a593Smuzhiyun struct mlx5_accel_esp_xfrm_attrs attrs;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun enum {
115*4882a593Smuzhiyun MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA = 1UL << 0,
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun enum mlx5_accel_ipsec_cap {
119*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_DEVICE = 1 << 0,
120*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA = 1 << 1,
121*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 2,
122*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 3,
123*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 4,
124*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER = 1 << 5,
125*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_ESN = 1 << 6,
126*4882a593Smuzhiyun MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN = 1 << 7,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #ifdef CONFIG_MLX5_ACCEL
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun struct mlx5_accel_esp_xfrm *
134*4882a593Smuzhiyun mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
135*4882a593Smuzhiyun const struct mlx5_accel_esp_xfrm_attrs *attrs,
136*4882a593Smuzhiyun u32 flags);
137*4882a593Smuzhiyun void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm);
138*4882a593Smuzhiyun int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
139*4882a593Smuzhiyun const struct mlx5_accel_esp_xfrm_attrs *attrs);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #else
142*4882a593Smuzhiyun
mlx5_accel_ipsec_device_caps(struct mlx5_core_dev * mdev)143*4882a593Smuzhiyun static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static inline struct mlx5_accel_esp_xfrm *
mlx5_accel_esp_create_xfrm(struct mlx5_core_dev * mdev,const struct mlx5_accel_esp_xfrm_attrs * attrs,u32 flags)146*4882a593Smuzhiyun mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
147*4882a593Smuzhiyun const struct mlx5_accel_esp_xfrm_attrs *attrs,
148*4882a593Smuzhiyun u32 flags) { return ERR_PTR(-EOPNOTSUPP); }
149*4882a593Smuzhiyun static inline void
mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm * xfrm)150*4882a593Smuzhiyun mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) {}
151*4882a593Smuzhiyun static inline int
mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm * xfrm,const struct mlx5_accel_esp_xfrm_attrs * attrs)152*4882a593Smuzhiyun mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
153*4882a593Smuzhiyun const struct mlx5_accel_esp_xfrm_attrs *attrs) { return -EOPNOTSUPP; }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #endif /* CONFIG_MLX5_ACCEL */
156*4882a593Smuzhiyun #endif /* __MLX5_ACCEL_H__ */
157