1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #ifndef MLX4_CQ_H
34*4882a593Smuzhiyun #define MLX4_CQ_H
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include <linux/types.h>
37*4882a593Smuzhiyun #include <uapi/linux/if_ether.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #include <linux/mlx4/device.h>
40*4882a593Smuzhiyun #include <linux/mlx4/doorbell.h>
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct mlx4_cqe {
43*4882a593Smuzhiyun __be32 vlan_my_qpn;
44*4882a593Smuzhiyun __be32 immed_rss_invalid;
45*4882a593Smuzhiyun __be32 g_mlpath_rqpn;
46*4882a593Smuzhiyun __be16 sl_vid;
47*4882a593Smuzhiyun union {
48*4882a593Smuzhiyun struct {
49*4882a593Smuzhiyun __be16 rlid;
50*4882a593Smuzhiyun __be16 status;
51*4882a593Smuzhiyun u8 ipv6_ext_mask;
52*4882a593Smuzhiyun u8 badfcs_enc;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun u8 smac[ETH_ALEN];
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun __be32 byte_cnt;
57*4882a593Smuzhiyun __be16 wqe_index;
58*4882a593Smuzhiyun __be16 checksum;
59*4882a593Smuzhiyun u8 reserved[3];
60*4882a593Smuzhiyun u8 owner_sr_opcode;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct mlx4_err_cqe {
64*4882a593Smuzhiyun __be32 my_qpn;
65*4882a593Smuzhiyun u32 reserved1[5];
66*4882a593Smuzhiyun __be16 wqe_index;
67*4882a593Smuzhiyun u8 vendor_err_syndrome;
68*4882a593Smuzhiyun u8 syndrome;
69*4882a593Smuzhiyun u8 reserved2[3];
70*4882a593Smuzhiyun u8 owner_sr_opcode;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun struct mlx4_ts_cqe {
74*4882a593Smuzhiyun __be32 vlan_my_qpn;
75*4882a593Smuzhiyun __be32 immed_rss_invalid;
76*4882a593Smuzhiyun __be32 g_mlpath_rqpn;
77*4882a593Smuzhiyun __be32 timestamp_hi;
78*4882a593Smuzhiyun __be16 status;
79*4882a593Smuzhiyun u8 ipv6_ext_mask;
80*4882a593Smuzhiyun u8 badfcs_enc;
81*4882a593Smuzhiyun __be32 byte_cnt;
82*4882a593Smuzhiyun __be16 wqe_index;
83*4882a593Smuzhiyun __be16 checksum;
84*4882a593Smuzhiyun u8 reserved;
85*4882a593Smuzhiyun __be16 timestamp_lo;
86*4882a593Smuzhiyun u8 owner_sr_opcode;
87*4882a593Smuzhiyun } __packed;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun enum {
90*4882a593Smuzhiyun MLX4_CQE_L2_TUNNEL_IPOK = 1 << 31,
91*4882a593Smuzhiyun MLX4_CQE_CVLAN_PRESENT_MASK = 1 << 29,
92*4882a593Smuzhiyun MLX4_CQE_SVLAN_PRESENT_MASK = 1 << 30,
93*4882a593Smuzhiyun MLX4_CQE_L2_TUNNEL = 1 << 27,
94*4882a593Smuzhiyun MLX4_CQE_L2_TUNNEL_CSUM = 1 << 26,
95*4882a593Smuzhiyun MLX4_CQE_L2_TUNNEL_IPV4 = 1 << 25,
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun MLX4_CQE_QPN_MASK = 0xffffff,
98*4882a593Smuzhiyun MLX4_CQE_VID_MASK = 0xfff,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun enum {
102*4882a593Smuzhiyun MLX4_CQE_OWNER_MASK = 0x80,
103*4882a593Smuzhiyun MLX4_CQE_IS_SEND_MASK = 0x40,
104*4882a593Smuzhiyun MLX4_CQE_OPCODE_MASK = 0x1f
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun enum {
108*4882a593Smuzhiyun MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
109*4882a593Smuzhiyun MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
110*4882a593Smuzhiyun MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
111*4882a593Smuzhiyun MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
112*4882a593Smuzhiyun MLX4_CQE_SYNDROME_MW_BIND_ERR = 0x06,
113*4882a593Smuzhiyun MLX4_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
114*4882a593Smuzhiyun MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
115*4882a593Smuzhiyun MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
116*4882a593Smuzhiyun MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
117*4882a593Smuzhiyun MLX4_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
118*4882a593Smuzhiyun MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
119*4882a593Smuzhiyun MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
120*4882a593Smuzhiyun MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun enum {
124*4882a593Smuzhiyun MLX4_CQE_STATUS_IPV4 = 1 << 6,
125*4882a593Smuzhiyun MLX4_CQE_STATUS_IPV4F = 1 << 7,
126*4882a593Smuzhiyun MLX4_CQE_STATUS_IPV6 = 1 << 8,
127*4882a593Smuzhiyun MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
128*4882a593Smuzhiyun MLX4_CQE_STATUS_TCP = 1 << 10,
129*4882a593Smuzhiyun MLX4_CQE_STATUS_UDP = 1 << 11,
130*4882a593Smuzhiyun MLX4_CQE_STATUS_IPOK = 1 << 12,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* L4_CSUM is logically part of status, but has to checked against badfcs_enc */
134*4882a593Smuzhiyun enum {
135*4882a593Smuzhiyun MLX4_CQE_STATUS_L4_CSUM = 1 << 2,
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun enum {
139*4882a593Smuzhiyun MLX4_CQE_LLC = 1,
140*4882a593Smuzhiyun MLX4_CQE_SNAP = 1 << 1,
141*4882a593Smuzhiyun MLX4_CQE_BAD_FCS = 1 << 4,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #define MLX4_MAX_CQ_PERIOD (BIT(16) - 1)
145*4882a593Smuzhiyun #define MLX4_MAX_CQ_COUNT (BIT(16) - 1)
146*4882a593Smuzhiyun
mlx4_cq_arm(struct mlx4_cq * cq,u32 cmd,void __iomem * uar_page,spinlock_t * doorbell_lock)147*4882a593Smuzhiyun static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
148*4882a593Smuzhiyun void __iomem *uar_page,
149*4882a593Smuzhiyun spinlock_t *doorbell_lock)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun __be32 doorbell[2];
152*4882a593Smuzhiyun u32 sn;
153*4882a593Smuzhiyun u32 ci;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun sn = cq->arm_sn & 3;
156*4882a593Smuzhiyun ci = cq->cons_index & 0xffffff;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /*
161*4882a593Smuzhiyun * Make sure that the doorbell record in host memory is
162*4882a593Smuzhiyun * written before ringing the doorbell via PCI MMIO.
163*4882a593Smuzhiyun */
164*4882a593Smuzhiyun wmb();
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun doorbell[0] = cpu_to_be32(sn << 28 | cmd | cq->cqn);
167*4882a593Smuzhiyun doorbell[1] = cpu_to_be32(ci);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun mlx4_write64(doorbell, uar_page + MLX4_CQ_DOORBELL, doorbell_lock);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
mlx4_cq_set_ci(struct mlx4_cq * cq)172*4882a593Smuzhiyun static inline void mlx4_cq_set_ci(struct mlx4_cq *cq)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun enum {
178*4882a593Smuzhiyun MLX4_CQ_DB_REQ_NOT_SOL = 1 << 24,
179*4882a593Smuzhiyun MLX4_CQ_DB_REQ_NOT = 2 << 24
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
183*4882a593Smuzhiyun u16 count, u16 period);
184*4882a593Smuzhiyun int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
185*4882a593Smuzhiyun int entries, struct mlx4_mtt *mtt);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #endif /* MLX4_CQ_H */
188