1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MFD_WM8994_REGISTERS_H__ 11*4882a593Smuzhiyun #define __MFD_WM8994_REGISTERS_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Register values. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define WM8994_SOFTWARE_RESET 0x00 17*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_1 0x01 18*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_2 0x02 19*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_3 0x03 20*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_4 0x04 21*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_5 0x05 22*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_6 0x06 23*4882a593Smuzhiyun #define WM8994_INPUT_MIXER_1 0x15 24*4882a593Smuzhiyun #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18 25*4882a593Smuzhiyun #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19 26*4882a593Smuzhiyun #define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A 27*4882a593Smuzhiyun #define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B 28*4882a593Smuzhiyun #define WM8994_LEFT_OUTPUT_VOLUME 0x1C 29*4882a593Smuzhiyun #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D 30*4882a593Smuzhiyun #define WM8994_LINE_OUTPUTS_VOLUME 0x1E 31*4882a593Smuzhiyun #define WM8994_HPOUT2_VOLUME 0x1F 32*4882a593Smuzhiyun #define WM8994_LEFT_OPGA_VOLUME 0x20 33*4882a593Smuzhiyun #define WM8994_RIGHT_OPGA_VOLUME 0x21 34*4882a593Smuzhiyun #define WM8994_SPKMIXL_ATTENUATION 0x22 35*4882a593Smuzhiyun #define WM8994_SPKMIXR_ATTENUATION 0x23 36*4882a593Smuzhiyun #define WM8994_SPKOUT_MIXERS 0x24 37*4882a593Smuzhiyun #define WM8994_CLASSD 0x25 38*4882a593Smuzhiyun #define WM8994_SPEAKER_VOLUME_LEFT 0x26 39*4882a593Smuzhiyun #define WM8994_SPEAKER_VOLUME_RIGHT 0x27 40*4882a593Smuzhiyun #define WM8994_INPUT_MIXER_2 0x28 41*4882a593Smuzhiyun #define WM8994_INPUT_MIXER_3 0x29 42*4882a593Smuzhiyun #define WM8994_INPUT_MIXER_4 0x2A 43*4882a593Smuzhiyun #define WM8994_INPUT_MIXER_5 0x2B 44*4882a593Smuzhiyun #define WM8994_INPUT_MIXER_6 0x2C 45*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_1 0x2D 46*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_2 0x2E 47*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_3 0x2F 48*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_4 0x30 49*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_5 0x31 50*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_6 0x32 51*4882a593Smuzhiyun #define WM8994_HPOUT2_MIXER 0x33 52*4882a593Smuzhiyun #define WM8994_LINE_MIXER_1 0x34 53*4882a593Smuzhiyun #define WM8994_LINE_MIXER_2 0x35 54*4882a593Smuzhiyun #define WM8994_SPEAKER_MIXER 0x36 55*4882a593Smuzhiyun #define WM8994_ADDITIONAL_CONTROL 0x37 56*4882a593Smuzhiyun #define WM8994_ANTIPOP_1 0x38 57*4882a593Smuzhiyun #define WM8994_ANTIPOP_2 0x39 58*4882a593Smuzhiyun #define WM8994_MICBIAS 0x3A 59*4882a593Smuzhiyun #define WM8994_LDO_1 0x3B 60*4882a593Smuzhiyun #define WM8994_LDO_2 0x3C 61*4882a593Smuzhiyun #define WM8958_MICBIAS1 0x3D 62*4882a593Smuzhiyun #define WM8958_MICBIAS2 0x3E 63*4882a593Smuzhiyun #define WM8994_CHARGE_PUMP_1 0x4C 64*4882a593Smuzhiyun #define WM8958_CHARGE_PUMP_2 0x4D 65*4882a593Smuzhiyun #define WM8994_CLASS_W_1 0x51 66*4882a593Smuzhiyun #define WM8994_DC_SERVO_1 0x54 67*4882a593Smuzhiyun #define WM8994_DC_SERVO_2 0x55 68*4882a593Smuzhiyun #define WM8994_DC_SERVO_4 0x57 69*4882a593Smuzhiyun #define WM8994_DC_SERVO_READBACK 0x58 70*4882a593Smuzhiyun #define WM8994_DC_SERVO_4E 0x59 71*4882a593Smuzhiyun #define WM8994_ANALOGUE_HP_1 0x60 72*4882a593Smuzhiyun #define WM8958_MIC_DETECT_1 0xD0 73*4882a593Smuzhiyun #define WM8958_MIC_DETECT_2 0xD1 74*4882a593Smuzhiyun #define WM8958_MIC_DETECT_3 0xD2 75*4882a593Smuzhiyun #define WM8994_CHIP_REVISION 0x100 76*4882a593Smuzhiyun #define WM8994_CONTROL_INTERFACE 0x101 77*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_CTRL_1 0x110 78*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_CTRL_2 0x111 79*4882a593Smuzhiyun #define WM8994_AIF1_CLOCKING_1 0x200 80*4882a593Smuzhiyun #define WM8994_AIF1_CLOCKING_2 0x201 81*4882a593Smuzhiyun #define WM8994_AIF2_CLOCKING_1 0x204 82*4882a593Smuzhiyun #define WM8994_AIF2_CLOCKING_2 0x205 83*4882a593Smuzhiyun #define WM8994_CLOCKING_1 0x208 84*4882a593Smuzhiyun #define WM8994_CLOCKING_2 0x209 85*4882a593Smuzhiyun #define WM8994_AIF1_RATE 0x210 86*4882a593Smuzhiyun #define WM8994_AIF2_RATE 0x211 87*4882a593Smuzhiyun #define WM8994_RATE_STATUS 0x212 88*4882a593Smuzhiyun #define WM8994_FLL1_CONTROL_1 0x220 89*4882a593Smuzhiyun #define WM8994_FLL1_CONTROL_2 0x221 90*4882a593Smuzhiyun #define WM8994_FLL1_CONTROL_3 0x222 91*4882a593Smuzhiyun #define WM8994_FLL1_CONTROL_4 0x223 92*4882a593Smuzhiyun #define WM8994_FLL1_CONTROL_5 0x224 93*4882a593Smuzhiyun #define WM8958_FLL1_EFS_1 0x226 94*4882a593Smuzhiyun #define WM8958_FLL1_EFS_2 0x227 95*4882a593Smuzhiyun #define WM8994_FLL2_CONTROL_1 0x240 96*4882a593Smuzhiyun #define WM8994_FLL2_CONTROL_2 0x241 97*4882a593Smuzhiyun #define WM8994_FLL2_CONTROL_3 0x242 98*4882a593Smuzhiyun #define WM8994_FLL2_CONTROL_4 0x243 99*4882a593Smuzhiyun #define WM8994_FLL2_CONTROL_5 0x244 100*4882a593Smuzhiyun #define WM8958_FLL2_EFS_1 0x246 101*4882a593Smuzhiyun #define WM8958_FLL2_EFS_2 0x247 102*4882a593Smuzhiyun #define WM8994_AIF1_CONTROL_1 0x300 103*4882a593Smuzhiyun #define WM8994_AIF1_CONTROL_2 0x301 104*4882a593Smuzhiyun #define WM8994_AIF1_MASTER_SLAVE 0x302 105*4882a593Smuzhiyun #define WM8994_AIF1_BCLK 0x303 106*4882a593Smuzhiyun #define WM8994_AIF1ADC_LRCLK 0x304 107*4882a593Smuzhiyun #define WM8994_AIF1DAC_LRCLK 0x305 108*4882a593Smuzhiyun #define WM8994_AIF1DAC_DATA 0x306 109*4882a593Smuzhiyun #define WM8994_AIF1ADC_DATA 0x307 110*4882a593Smuzhiyun #define WM8994_AIF2_CONTROL_1 0x310 111*4882a593Smuzhiyun #define WM8994_AIF2_CONTROL_2 0x311 112*4882a593Smuzhiyun #define WM8994_AIF2_MASTER_SLAVE 0x312 113*4882a593Smuzhiyun #define WM8994_AIF2_BCLK 0x313 114*4882a593Smuzhiyun #define WM8994_AIF2ADC_LRCLK 0x314 115*4882a593Smuzhiyun #define WM8994_AIF2DAC_LRCLK 0x315 116*4882a593Smuzhiyun #define WM8994_AIF2DAC_DATA 0x316 117*4882a593Smuzhiyun #define WM8994_AIF2ADC_DATA 0x317 118*4882a593Smuzhiyun #define WM1811_AIF2TX_CONTROL 0x318 119*4882a593Smuzhiyun #define WM8958_AIF3_CONTROL_1 0x320 120*4882a593Smuzhiyun #define WM8958_AIF3_CONTROL_2 0x321 121*4882a593Smuzhiyun #define WM8958_AIF3DAC_DATA 0x322 122*4882a593Smuzhiyun #define WM8958_AIF3ADC_DATA 0x323 123*4882a593Smuzhiyun #define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400 124*4882a593Smuzhiyun #define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401 125*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402 126*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_RIGHT_VOLUME 0x403 127*4882a593Smuzhiyun #define WM8994_AIF1_ADC2_LEFT_VOLUME 0x404 128*4882a593Smuzhiyun #define WM8994_AIF1_ADC2_RIGHT_VOLUME 0x405 129*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_LEFT_VOLUME 0x406 130*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_RIGHT_VOLUME 0x407 131*4882a593Smuzhiyun #define WM8994_AIF1_ADC1_FILTERS 0x410 132*4882a593Smuzhiyun #define WM8994_AIF1_ADC2_FILTERS 0x411 133*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_FILTERS_1 0x420 134*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_FILTERS_2 0x421 135*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_FILTERS_1 0x422 136*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_FILTERS_2 0x423 137*4882a593Smuzhiyun #define WM8958_AIF1_DAC1_NOISE_GATE 0x430 138*4882a593Smuzhiyun #define WM8958_AIF1_DAC2_NOISE_GATE 0x431 139*4882a593Smuzhiyun #define WM8994_AIF1_DRC1_1 0x440 140*4882a593Smuzhiyun #define WM8994_AIF1_DRC1_2 0x441 141*4882a593Smuzhiyun #define WM8994_AIF1_DRC1_3 0x442 142*4882a593Smuzhiyun #define WM8994_AIF1_DRC1_4 0x443 143*4882a593Smuzhiyun #define WM8994_AIF1_DRC1_5 0x444 144*4882a593Smuzhiyun #define WM8994_AIF1_DRC2_1 0x450 145*4882a593Smuzhiyun #define WM8994_AIF1_DRC2_2 0x451 146*4882a593Smuzhiyun #define WM8994_AIF1_DRC2_3 0x452 147*4882a593Smuzhiyun #define WM8994_AIF1_DRC2_4 0x453 148*4882a593Smuzhiyun #define WM8994_AIF1_DRC2_5 0x454 149*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480 150*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481 151*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_1_A 0x482 152*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_1_B 0x483 153*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_1_PG 0x484 154*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_2_A 0x485 155*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_2_B 0x486 156*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_2_C 0x487 157*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_2_PG 0x488 158*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_3_A 0x489 159*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_3_B 0x48A 160*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_3_C 0x48B 161*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_3_PG 0x48C 162*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_4_A 0x48D 163*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_4_B 0x48E 164*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_4_C 0x48F 165*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_4_PG 0x490 166*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491 167*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492 168*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493 169*4882a593Smuzhiyun #define WM8994_AIF1_DAC1_EQ_BAND_1_C 0x494 170*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0 171*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1 172*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2 173*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_1_B 0x4A3 174*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 175*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_2_A 0x4A5 176*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_2_B 0x4A6 177*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_2_C 0x4A7 178*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 179*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_3_A 0x4A9 180*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_3_B 0x4AA 181*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_3_C 0x4AB 182*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_3_PG 0x4AC 183*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_4_A 0x4AD 184*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_4_B 0x4AE 185*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_4_C 0x4AF 186*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 187*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1 188*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2 189*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 190*4882a593Smuzhiyun #define WM8994_AIF1_DAC2_EQ_BAND_1_C 0x4B4 191*4882a593Smuzhiyun #define WM8994_AIF2_ADC_LEFT_VOLUME 0x500 192*4882a593Smuzhiyun #define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501 193*4882a593Smuzhiyun #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 194*4882a593Smuzhiyun #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 195*4882a593Smuzhiyun #define WM8994_AIF2_ADC_FILTERS 0x510 196*4882a593Smuzhiyun #define WM8994_AIF2_DAC_FILTERS_1 0x520 197*4882a593Smuzhiyun #define WM8994_AIF2_DAC_FILTERS_2 0x521 198*4882a593Smuzhiyun #define WM8958_AIF2_DAC_NOISE_GATE 0x530 199*4882a593Smuzhiyun #define WM8994_AIF2_DRC_1 0x540 200*4882a593Smuzhiyun #define WM8994_AIF2_DRC_2 0x541 201*4882a593Smuzhiyun #define WM8994_AIF2_DRC_3 0x542 202*4882a593Smuzhiyun #define WM8994_AIF2_DRC_4 0x543 203*4882a593Smuzhiyun #define WM8994_AIF2_DRC_5 0x544 204*4882a593Smuzhiyun #define WM8994_AIF2_EQ_GAINS_1 0x580 205*4882a593Smuzhiyun #define WM8994_AIF2_EQ_GAINS_2 0x581 206*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_1_A 0x582 207*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_1_B 0x583 208*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_1_PG 0x584 209*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_2_A 0x585 210*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_2_B 0x586 211*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_2_C 0x587 212*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_2_PG 0x588 213*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_3_A 0x589 214*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_3_B 0x58A 215*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_3_C 0x58B 216*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_3_PG 0x58C 217*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_4_A 0x58D 218*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_4_B 0x58E 219*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_4_C 0x58F 220*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_4_PG 0x590 221*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_5_A 0x591 222*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_5_B 0x592 223*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_5_PG 0x593 224*4882a593Smuzhiyun #define WM8994_AIF2_EQ_BAND_1_C 0x594 225*4882a593Smuzhiyun #define WM8994_DAC1_MIXER_VOLUMES 0x600 226*4882a593Smuzhiyun #define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 227*4882a593Smuzhiyun #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 228*4882a593Smuzhiyun #define WM8994_DAC2_MIXER_VOLUMES 0x603 229*4882a593Smuzhiyun #define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604 230*4882a593Smuzhiyun #define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605 231*4882a593Smuzhiyun #define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 232*4882a593Smuzhiyun #define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 233*4882a593Smuzhiyun #define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 234*4882a593Smuzhiyun #define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 235*4882a593Smuzhiyun #define WM8994_DAC1_LEFT_VOLUME 0x610 236*4882a593Smuzhiyun #define WM8994_DAC1_RIGHT_VOLUME 0x611 237*4882a593Smuzhiyun #define WM8994_DAC2_LEFT_VOLUME 0x612 238*4882a593Smuzhiyun #define WM8994_DAC2_RIGHT_VOLUME 0x613 239*4882a593Smuzhiyun #define WM8994_DAC_SOFTMUTE 0x614 240*4882a593Smuzhiyun #define WM8994_OVERSAMPLING 0x620 241*4882a593Smuzhiyun #define WM8994_SIDETONE 0x621 242*4882a593Smuzhiyun #define WM8994_GPIO_1 0x700 243*4882a593Smuzhiyun #define WM8994_GPIO_2 0x701 244*4882a593Smuzhiyun #define WM8994_GPIO_3 0x702 245*4882a593Smuzhiyun #define WM8994_GPIO_4 0x703 246*4882a593Smuzhiyun #define WM8994_GPIO_5 0x704 247*4882a593Smuzhiyun #define WM8994_GPIO_6 0x705 248*4882a593Smuzhiyun #define WM1811_JACKDET_CTRL 0x705 249*4882a593Smuzhiyun #define WM8994_GPIO_7 0x706 250*4882a593Smuzhiyun #define WM8994_GPIO_8 0x707 251*4882a593Smuzhiyun #define WM8994_GPIO_9 0x708 252*4882a593Smuzhiyun #define WM8994_GPIO_10 0x709 253*4882a593Smuzhiyun #define WM8994_GPIO_11 0x70A 254*4882a593Smuzhiyun #define WM8994_PULL_CONTROL_1 0x720 255*4882a593Smuzhiyun #define WM8994_PULL_CONTROL_2 0x721 256*4882a593Smuzhiyun #define WM8994_INTERRUPT_STATUS_1 0x730 257*4882a593Smuzhiyun #define WM8994_INTERRUPT_STATUS_2 0x731 258*4882a593Smuzhiyun #define WM8994_INTERRUPT_RAW_STATUS_2 0x732 259*4882a593Smuzhiyun #define WM8994_INTERRUPT_STATUS_1_MASK 0x738 260*4882a593Smuzhiyun #define WM8994_INTERRUPT_STATUS_2_MASK 0x739 261*4882a593Smuzhiyun #define WM8994_INTERRUPT_CONTROL 0x740 262*4882a593Smuzhiyun #define WM8994_IRQ_DEBOUNCE 0x748 263*4882a593Smuzhiyun #define WM8958_DSP2_PROGRAM 0x900 264*4882a593Smuzhiyun #define WM8958_DSP2_CONFIG 0x901 265*4882a593Smuzhiyun #define WM8958_DSP2_MAGICNUM 0xA00 266*4882a593Smuzhiyun #define WM8958_DSP2_RELEASEYEAR 0xA01 267*4882a593Smuzhiyun #define WM8958_DSP2_RELEASEMONTHDAY 0xA02 268*4882a593Smuzhiyun #define WM8958_DSP2_RELEASETIME 0xA03 269*4882a593Smuzhiyun #define WM8958_DSP2_VERMAJMIN 0xA04 270*4882a593Smuzhiyun #define WM8958_DSP2_VERBUILD 0xA05 271*4882a593Smuzhiyun #define WM8958_DSP2_TESTREG 0xA06 272*4882a593Smuzhiyun #define WM8958_DSP2_XORREG 0xA07 273*4882a593Smuzhiyun #define WM8958_DSP2_SHIFTMAXX 0xA08 274*4882a593Smuzhiyun #define WM8958_DSP2_SHIFTMAXY 0xA09 275*4882a593Smuzhiyun #define WM8958_DSP2_SHIFTMAXZ 0xA0A 276*4882a593Smuzhiyun #define WM8958_DSP2_SHIFTMAXEXTLO 0xA0B 277*4882a593Smuzhiyun #define WM8958_DSP2_AESSELECT 0xA0C 278*4882a593Smuzhiyun #define WM8958_DSP2_EXECCONTROL 0xA0D 279*4882a593Smuzhiyun #define WM8958_DSP2_SAMPLEBREAK 0xA0E 280*4882a593Smuzhiyun #define WM8958_DSP2_COUNTBREAK 0xA0F 281*4882a593Smuzhiyun #define WM8958_DSP2_INTSTATUS 0xA10 282*4882a593Smuzhiyun #define WM8958_DSP2_EVENTSTATUS 0xA11 283*4882a593Smuzhiyun #define WM8958_DSP2_INTMASK 0xA12 284*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGDWIDTH 0xA13 285*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGINSTR 0xA14 286*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGDMEM 0xA15 287*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGDELAYS 0xA16 288*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGNUMIO 0xA17 289*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGEXTDEPTH 0xA18 290*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGMULTIPLIER 0xA19 291*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGCTRLDWIDTH 0xA1A 292*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGPIPELINE 0xA1B 293*4882a593Smuzhiyun #define WM8958_DSP2_SHIFTMAXEXTHI 0xA1C 294*4882a593Smuzhiyun #define WM8958_DSP2_SWVERSIONREG 0xA1D 295*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGXMEM 0xA1E 296*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGYMEM 0xA1F 297*4882a593Smuzhiyun #define WM8958_DSP2_CONFIGZMEM 0xA20 298*4882a593Smuzhiyun #define WM8958_FW_BUILD_1 0x2000 299*4882a593Smuzhiyun #define WM8958_FW_BUILD_0 0x2001 300*4882a593Smuzhiyun #define WM8958_FW_ID_1 0x2002 301*4882a593Smuzhiyun #define WM8958_FW_ID_0 0x2003 302*4882a593Smuzhiyun #define WM8958_FW_MAJOR_1 0x2004 303*4882a593Smuzhiyun #define WM8958_FW_MAJOR_0 0x2005 304*4882a593Smuzhiyun #define WM8958_FW_MINOR_1 0x2006 305*4882a593Smuzhiyun #define WM8958_FW_MINOR_0 0x2007 306*4882a593Smuzhiyun #define WM8958_FW_PATCH_1 0x2008 307*4882a593Smuzhiyun #define WM8958_FW_PATCH_0 0x2009 308*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200 309*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201 310*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202 311*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2 0x2203 312*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1 0x2204 313*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2 0x2205 314*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1 0x2206 315*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2 0x2207 316*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1 0x2208 317*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2 0x2209 318*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1 0x220A 319*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2 0x220B 320*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1 0x220C 321*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2 0x220D 322*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1 0x220E 323*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2 0x220F 324*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1 0x2210 325*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2 0x2211 326*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_LOWER_CUTOFF_1 0x2212 327*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_LOWER_CUTOFF_2 0x2213 328*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_K_1 0x2400 329*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_K_2 0x2401 330*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N1_1 0x2402 331*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N1_2 0x2403 332*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N2_1 0x2404 333*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N2_2 0x2405 334*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N3_1 0x2406 335*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N3_2 0x2407 336*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N4_1 0x2408 337*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N4_2 0x2409 338*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N5_1 0x240A 339*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_N5_2 0x240B 340*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_X1_1 0x240C 341*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_X1_2 0x240D 342*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_X2_1 0x240E 343*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_X2_2 0x240F 344*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_X3_1 0x2410 345*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_X3_2 0x2411 346*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_ATTACK_1 0x2412 347*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_ATTACK_2 0x2413 348*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_DECAY_1 0x2414 349*4882a593Smuzhiyun #define WM8958_MBC_BAND_1_DECAY_2 0x2415 350*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_K_1 0x2416 351*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_K_2 0x2417 352*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N1_1 0x2418 353*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N1_2 0x2419 354*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N2_1 0x241A 355*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N2_2 0x241B 356*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N3_1 0x241C 357*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N3_2 0x241D 358*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N4_1 0x241E 359*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N4_2 0x241F 360*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N5_1 0x2420 361*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_N5_2 0x2421 362*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_X1_1 0x2422 363*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_X1_2 0x2423 364*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_X2_1 0x2424 365*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_X2_2 0x2425 366*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_X3_1 0x2426 367*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_X3_2 0x2427 368*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_ATTACK_1 0x2428 369*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_ATTACK_2 0x2429 370*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_DECAY_1 0x242A 371*4882a593Smuzhiyun #define WM8958_MBC_BAND_2_DECAY_2 0x242B 372*4882a593Smuzhiyun #define WM8958_MBC_B2_PG2_1 0x242C 373*4882a593Smuzhiyun #define WM8958_MBC_B2_PG2_2 0x242D 374*4882a593Smuzhiyun #define WM8958_MBC_B1_PG2_1 0x242E 375*4882a593Smuzhiyun #define WM8958_MBC_B1_PG2_2 0x242F 376*4882a593Smuzhiyun #define WM8958_MBC_CROSSOVER_1 0x2600 377*4882a593Smuzhiyun #define WM8958_MBC_CROSSOVER_2 0x2601 378*4882a593Smuzhiyun #define WM8958_MBC_HPF_1 0x2602 379*4882a593Smuzhiyun #define WM8958_MBC_HPF_2 0x2603 380*4882a593Smuzhiyun #define WM8958_MBC_LPF_1 0x2606 381*4882a593Smuzhiyun #define WM8958_MBC_LPF_2 0x2607 382*4882a593Smuzhiyun #define WM8958_MBC_RMS_LIMIT_1 0x260A 383*4882a593Smuzhiyun #define WM8958_MBC_RMS_LIMIT_2 0x260B 384*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_0 0x3000 385*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_1 0x3001 386*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_2 0x3002 387*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_3 0x3003 388*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_4 0x3004 389*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_5 0x3005 390*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_6 0x3006 391*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_7 0x3007 392*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_8 0x3008 393*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_9 0x3009 394*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_10 0x300A 395*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_11 0x300B 396*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_12 0x300C 397*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_13 0x300D 398*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_14 0x300E 399*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_15 0x300F 400*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_16 0x3010 401*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_17 0x3011 402*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_18 0x3012 403*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_19 0x3013 404*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_20 0x3014 405*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_21 0x3015 406*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_22 0x3016 407*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_23 0x3017 408*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_24 0x3018 409*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_25 0x3019 410*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_26 0x301A 411*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_27 0x301B 412*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_28 0x301C 413*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_29 0x301D 414*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_30 0x301E 415*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_31 0x301F 416*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_32 0x3020 417*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_33 0x3021 418*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_34 0x3022 419*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_35 0x3023 420*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_36 0x3024 421*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_37 0x3025 422*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_38 0x3026 423*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_39 0x3027 424*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_40 0x3028 425*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_41 0x3029 426*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_42 0x302A 427*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_43 0x302B 428*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_44 0x302C 429*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_45 0x302D 430*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_46 0x302E 431*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_47 0x302F 432*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_48 0x3030 433*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_49 0x3031 434*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_50 0x3032 435*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_51 0x3033 436*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_52 0x3034 437*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_53 0x3035 438*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_54 0x3036 439*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_55 0x3037 440*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_56 0x3038 441*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_57 0x3039 442*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_58 0x303A 443*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_59 0x303B 444*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_60 0x303C 445*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_61 0x303D 446*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_62 0x303E 447*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_63 0x303F 448*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_64 0x3040 449*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_65 0x3041 450*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_66 0x3042 451*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_67 0x3043 452*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_68 0x3044 453*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_69 0x3045 454*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_70 0x3046 455*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_71 0x3047 456*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_72 0x3048 457*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_73 0x3049 458*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_74 0x304A 459*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_75 0x304B 460*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_76 0x304C 461*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_77 0x304D 462*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_78 0x304E 463*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_79 0x304F 464*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_80 0x3050 465*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_81 0x3051 466*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_82 0x3052 467*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_83 0x3053 468*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_84 0x3054 469*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_85 0x3055 470*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_86 0x3056 471*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_87 0x3057 472*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_88 0x3058 473*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_89 0x3059 474*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_90 0x305A 475*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_91 0x305B 476*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_92 0x305C 477*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_93 0x305D 478*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_94 0x305E 479*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_95 0x305F 480*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_96 0x3060 481*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_97 0x3061 482*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_98 0x3062 483*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_99 0x3063 484*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_100 0x3064 485*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_101 0x3065 486*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_102 0x3066 487*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_103 0x3067 488*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_104 0x3068 489*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_105 0x3069 490*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_106 0x306A 491*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_107 0x306B 492*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_108 0x306C 493*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_109 0x306D 494*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_110 0x306E 495*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_111 0x306F 496*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_112 0x3070 497*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_113 0x3071 498*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_114 0x3072 499*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_115 0x3073 500*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_116 0x3074 501*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_117 0x3075 502*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_118 0x3076 503*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_119 0x3077 504*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_120 0x3078 505*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_121 0x3079 506*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_122 0x307A 507*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_123 0x307B 508*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_124 0x307C 509*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_125 0x307D 510*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_126 0x307E 511*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_127 0x307F 512*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_128 0x3080 513*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_129 0x3081 514*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_130 0x3082 515*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_131 0x3083 516*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_132 0x3084 517*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_133 0x3085 518*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_134 0x3086 519*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_135 0x3087 520*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_136 0x3088 521*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_137 0x3089 522*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_138 0x308A 523*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_139 0x308B 524*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_140 0x308C 525*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_141 0x308D 526*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_142 0x308E 527*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_143 0x308F 528*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_144 0x3090 529*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_145 0x3091 530*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_146 0x3092 531*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_147 0x3093 532*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_148 0x3094 533*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_149 0x3095 534*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_150 0x3096 535*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_151 0x3097 536*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_152 0x3098 537*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_153 0x3099 538*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_154 0x309A 539*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_155 0x309B 540*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_156 0x309C 541*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_157 0x309D 542*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_158 0x309E 543*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_159 0x309F 544*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_160 0x30A0 545*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_161 0x30A1 546*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_162 0x30A2 547*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_163 0x30A3 548*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_164 0x30A4 549*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_165 0x30A5 550*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_166 0x30A6 551*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_167 0x30A7 552*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_168 0x30A8 553*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_169 0x30A9 554*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_170 0x30AA 555*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_171 0x30AB 556*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_172 0x30AC 557*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_173 0x30AD 558*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_174 0x30AE 559*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_175 0x30AF 560*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_176 0x30B0 561*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_177 0x30B1 562*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_178 0x30B2 563*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_179 0x30B3 564*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_180 0x30B4 565*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_181 0x30B5 566*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_182 0x30B6 567*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_183 0x30B7 568*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_184 0x30B8 569*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_185 0x30B9 570*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_186 0x30BA 571*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_187 0x30BB 572*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_188 0x30BC 573*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_189 0x30BD 574*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_190 0x30BE 575*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_191 0x30BF 576*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_192 0x30C0 577*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_193 0x30C1 578*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_194 0x30C2 579*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_195 0x30C3 580*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_196 0x30C4 581*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_197 0x30C5 582*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_198 0x30C6 583*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_199 0x30C7 584*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_200 0x30C8 585*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_201 0x30C9 586*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_202 0x30CA 587*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_203 0x30CB 588*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_204 0x30CC 589*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_205 0x30CD 590*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_206 0x30CE 591*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_207 0x30CF 592*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_208 0x30D0 593*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_209 0x30D1 594*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_210 0x30D2 595*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_211 0x30D3 596*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_212 0x30D4 597*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_213 0x30D5 598*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_214 0x30D6 599*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_215 0x30D7 600*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_216 0x30D8 601*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_217 0x30D9 602*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_218 0x30DA 603*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_219 0x30DB 604*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_220 0x30DC 605*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_221 0x30DD 606*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_222 0x30DE 607*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_223 0x30DF 608*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_224 0x30E0 609*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_225 0x30E1 610*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_226 0x30E2 611*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_227 0x30E3 612*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_228 0x30E4 613*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_229 0x30E5 614*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_230 0x30E6 615*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_231 0x30E7 616*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_232 0x30E8 617*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_233 0x30E9 618*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_234 0x30EA 619*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_235 0x30EB 620*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_236 0x30EC 621*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_237 0x30ED 622*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_238 0x30EE 623*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_239 0x30EF 624*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_240 0x30F0 625*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_241 0x30F1 626*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_242 0x30F2 627*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_243 0x30F3 628*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_244 0x30F4 629*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_245 0x30F5 630*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_246 0x30F6 631*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_247 0x30F7 632*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_248 0x30F8 633*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_249 0x30F9 634*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_250 0x30FA 635*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_251 0x30FB 636*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_252 0x30FC 637*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_253 0x30FD 638*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_254 0x30FE 639*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_255 0x30FF 640*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_256 0x3100 641*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_257 0x3101 642*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_258 0x3102 643*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_259 0x3103 644*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_260 0x3104 645*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_261 0x3105 646*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_262 0x3106 647*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_263 0x3107 648*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_264 0x3108 649*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_265 0x3109 650*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_266 0x310A 651*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_267 0x310B 652*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_268 0x310C 653*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_269 0x310D 654*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_270 0x310E 655*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_271 0x310F 656*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_272 0x3110 657*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_273 0x3111 658*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_274 0x3112 659*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_275 0x3113 660*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_276 0x3114 661*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_277 0x3115 662*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_278 0x3116 663*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_279 0x3117 664*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_280 0x3118 665*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_281 0x3119 666*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_282 0x311A 667*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_283 0x311B 668*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_284 0x311C 669*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_285 0x311D 670*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_286 0x311E 671*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_287 0x311F 672*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_288 0x3120 673*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_289 0x3121 674*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_290 0x3122 675*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_291 0x3123 676*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_292 0x3124 677*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_293 0x3125 678*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_294 0x3126 679*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_295 0x3127 680*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_296 0x3128 681*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_297 0x3129 682*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_298 0x312A 683*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_299 0x312B 684*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_300 0x312C 685*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_301 0x312D 686*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_302 0x312E 687*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_303 0x312F 688*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_304 0x3130 689*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_305 0x3131 690*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_306 0x3132 691*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_307 0x3133 692*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_308 0x3134 693*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_309 0x3135 694*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_310 0x3136 695*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_311 0x3137 696*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_312 0x3138 697*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_313 0x3139 698*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_314 0x313A 699*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_315 0x313B 700*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_316 0x313C 701*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_317 0x313D 702*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_318 0x313E 703*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_319 0x313F 704*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_320 0x3140 705*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_321 0x3141 706*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_322 0x3142 707*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_323 0x3143 708*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_324 0x3144 709*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_325 0x3145 710*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_326 0x3146 711*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_327 0x3147 712*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_328 0x3148 713*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_329 0x3149 714*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_330 0x314A 715*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_331 0x314B 716*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_332 0x314C 717*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_333 0x314D 718*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_334 0x314E 719*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_335 0x314F 720*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_336 0x3150 721*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_337 0x3151 722*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_338 0x3152 723*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_339 0x3153 724*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_340 0x3154 725*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_341 0x3155 726*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_342 0x3156 727*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_343 0x3157 728*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_344 0x3158 729*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_345 0x3159 730*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_346 0x315A 731*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_347 0x315B 732*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_348 0x315C 733*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_349 0x315D 734*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_350 0x315E 735*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_351 0x315F 736*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_352 0x3160 737*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_353 0x3161 738*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_354 0x3162 739*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_355 0x3163 740*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_356 0x3164 741*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_357 0x3165 742*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_358 0x3166 743*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_359 0x3167 744*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_360 0x3168 745*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_361 0x3169 746*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_362 0x316A 747*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_363 0x316B 748*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_364 0x316C 749*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_365 0x316D 750*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_366 0x316E 751*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_367 0x316F 752*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_368 0x3170 753*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_369 0x3171 754*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_370 0x3172 755*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_371 0x3173 756*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_372 0x3174 757*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_373 0x3175 758*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_374 0x3176 759*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_375 0x3177 760*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_376 0x3178 761*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_377 0x3179 762*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_378 0x317A 763*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_379 0x317B 764*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_380 0x317C 765*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_381 0x317D 766*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_382 0x317E 767*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_383 0x317F 768*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_384 0x3180 769*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_385 0x3181 770*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_386 0x3182 771*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_387 0x3183 772*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_388 0x3184 773*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_389 0x3185 774*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_390 0x3186 775*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_391 0x3187 776*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_392 0x3188 777*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_393 0x3189 778*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_394 0x318A 779*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_395 0x318B 780*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_396 0x318C 781*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_397 0x318D 782*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_398 0x318E 783*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_399 0x318F 784*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_400 0x3190 785*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_401 0x3191 786*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_402 0x3192 787*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_403 0x3193 788*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_404 0x3194 789*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_405 0x3195 790*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_406 0x3196 791*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_407 0x3197 792*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_408 0x3198 793*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_409 0x3199 794*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_410 0x319A 795*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_411 0x319B 796*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_412 0x319C 797*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_413 0x319D 798*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_414 0x319E 799*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_415 0x319F 800*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_416 0x31A0 801*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_417 0x31A1 802*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_418 0x31A2 803*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_419 0x31A3 804*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_420 0x31A4 805*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_421 0x31A5 806*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_422 0x31A6 807*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_423 0x31A7 808*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_424 0x31A8 809*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_425 0x31A9 810*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_426 0x31AA 811*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_427 0x31AB 812*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_428 0x31AC 813*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_429 0x31AD 814*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_430 0x31AE 815*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_431 0x31AF 816*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_432 0x31B0 817*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_433 0x31B1 818*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_434 0x31B2 819*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_435 0x31B3 820*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_436 0x31B4 821*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_437 0x31B5 822*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_438 0x31B6 823*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_439 0x31B7 824*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_440 0x31B8 825*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_441 0x31B9 826*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_442 0x31BA 827*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_443 0x31BB 828*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_444 0x31BC 829*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_445 0x31BD 830*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_446 0x31BE 831*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_447 0x31BF 832*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_448 0x31C0 833*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_449 0x31C1 834*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_450 0x31C2 835*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_451 0x31C3 836*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_452 0x31C4 837*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_453 0x31C5 838*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_454 0x31C6 839*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_455 0x31C7 840*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_456 0x31C8 841*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_457 0x31C9 842*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_458 0x31CA 843*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_459 0x31CB 844*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_460 0x31CC 845*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_461 0x31CD 846*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_462 0x31CE 847*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_463 0x31CF 848*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_464 0x31D0 849*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_465 0x31D1 850*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_466 0x31D2 851*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_467 0x31D3 852*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_468 0x31D4 853*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_469 0x31D5 854*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_470 0x31D6 855*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_471 0x31D7 856*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_472 0x31D8 857*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_473 0x31D9 858*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_474 0x31DA 859*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_475 0x31DB 860*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_476 0x31DC 861*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_477 0x31DD 862*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_478 0x31DE 863*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_479 0x31DF 864*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_480 0x31E0 865*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_481 0x31E1 866*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_482 0x31E2 867*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_483 0x31E3 868*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_484 0x31E4 869*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_485 0x31E5 870*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_486 0x31E6 871*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_487 0x31E7 872*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_488 0x31E8 873*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_489 0x31E9 874*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_490 0x31EA 875*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_491 0x31EB 876*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_492 0x31EC 877*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_493 0x31ED 878*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_494 0x31EE 879*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_495 0x31EF 880*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_496 0x31F0 881*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_497 0x31F1 882*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_498 0x31F2 883*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_499 0x31F3 884*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_500 0x31F4 885*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_501 0x31F5 886*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_502 0x31F6 887*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_503 0x31F7 888*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_504 0x31F8 889*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_505 0x31F9 890*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_506 0x31FA 891*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_507 0x31FB 892*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_508 0x31FC 893*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_509 0x31FD 894*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_510 0x31FE 895*4882a593Smuzhiyun #define WM8994_WRITE_SEQUENCER_511 0x31FF 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun #define WM8994_REGISTER_COUNT 736 898*4882a593Smuzhiyun #define WM8994_MAX_REGISTER 0x31FF 899*4882a593Smuzhiyun #define WM8994_MAX_CACHED_REGISTER 0x749 900*4882a593Smuzhiyun 901*4882a593Smuzhiyun /* 902*4882a593Smuzhiyun * Field Definitions. 903*4882a593Smuzhiyun */ 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun /* 906*4882a593Smuzhiyun * R0 (0x00) - Software Reset 907*4882a593Smuzhiyun */ 908*4882a593Smuzhiyun #define WM8994_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 909*4882a593Smuzhiyun #define WM8994_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 910*4882a593Smuzhiyun #define WM8994_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun /* 913*4882a593Smuzhiyun * R1 (0x01) - Power Management (1) 914*4882a593Smuzhiyun */ 915*4882a593Smuzhiyun #define WM8994_SPKOUTR_ENA 0x2000 /* SPKOUTR_ENA */ 916*4882a593Smuzhiyun #define WM8994_SPKOUTR_ENA_MASK 0x2000 /* SPKOUTR_ENA */ 917*4882a593Smuzhiyun #define WM8994_SPKOUTR_ENA_SHIFT 13 /* SPKOUTR_ENA */ 918*4882a593Smuzhiyun #define WM8994_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */ 919*4882a593Smuzhiyun #define WM8994_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */ 920*4882a593Smuzhiyun #define WM8994_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */ 921*4882a593Smuzhiyun #define WM8994_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */ 922*4882a593Smuzhiyun #define WM8994_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */ 923*4882a593Smuzhiyun #define WM8994_HPOUT2_ENA 0x0800 /* HPOUT2_ENA */ 924*4882a593Smuzhiyun #define WM8994_HPOUT2_ENA_MASK 0x0800 /* HPOUT2_ENA */ 925*4882a593Smuzhiyun #define WM8994_HPOUT2_ENA_SHIFT 11 /* HPOUT2_ENA */ 926*4882a593Smuzhiyun #define WM8994_HPOUT2_ENA_WIDTH 1 /* HPOUT2_ENA */ 927*4882a593Smuzhiyun #define WM8994_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */ 928*4882a593Smuzhiyun #define WM8994_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */ 929*4882a593Smuzhiyun #define WM8994_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */ 930*4882a593Smuzhiyun #define WM8994_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 931*4882a593Smuzhiyun #define WM8994_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */ 932*4882a593Smuzhiyun #define WM8994_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */ 933*4882a593Smuzhiyun #define WM8994_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */ 934*4882a593Smuzhiyun #define WM8994_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 935*4882a593Smuzhiyun #define WM8994_MICB2_ENA 0x0020 /* MICB2_ENA */ 936*4882a593Smuzhiyun #define WM8994_MICB2_ENA_MASK 0x0020 /* MICB2_ENA */ 937*4882a593Smuzhiyun #define WM8994_MICB2_ENA_SHIFT 5 /* MICB2_ENA */ 938*4882a593Smuzhiyun #define WM8994_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 939*4882a593Smuzhiyun #define WM8994_MICB1_ENA 0x0010 /* MICB1_ENA */ 940*4882a593Smuzhiyun #define WM8994_MICB1_ENA_MASK 0x0010 /* MICB1_ENA */ 941*4882a593Smuzhiyun #define WM8994_MICB1_ENA_SHIFT 4 /* MICB1_ENA */ 942*4882a593Smuzhiyun #define WM8994_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 943*4882a593Smuzhiyun #define WM8994_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */ 944*4882a593Smuzhiyun #define WM8994_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */ 945*4882a593Smuzhiyun #define WM8994_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */ 946*4882a593Smuzhiyun #define WM8994_BIAS_ENA 0x0001 /* BIAS_ENA */ 947*4882a593Smuzhiyun #define WM8994_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 948*4882a593Smuzhiyun #define WM8994_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 949*4882a593Smuzhiyun #define WM8994_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun /* 952*4882a593Smuzhiyun * R2 (0x02) - Power Management (2) 953*4882a593Smuzhiyun */ 954*4882a593Smuzhiyun #define WM8994_TSHUT_ENA 0x4000 /* TSHUT_ENA */ 955*4882a593Smuzhiyun #define WM8994_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */ 956*4882a593Smuzhiyun #define WM8994_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */ 957*4882a593Smuzhiyun #define WM8994_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */ 958*4882a593Smuzhiyun #define WM8994_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ 959*4882a593Smuzhiyun #define WM8994_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */ 960*4882a593Smuzhiyun #define WM8994_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */ 961*4882a593Smuzhiyun #define WM8994_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */ 962*4882a593Smuzhiyun #define WM8994_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 963*4882a593Smuzhiyun #define WM8994_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 964*4882a593Smuzhiyun #define WM8994_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 965*4882a593Smuzhiyun #define WM8994_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 966*4882a593Smuzhiyun #define WM8994_MIXINL_ENA 0x0200 /* MIXINL_ENA */ 967*4882a593Smuzhiyun #define WM8994_MIXINL_ENA_MASK 0x0200 /* MIXINL_ENA */ 968*4882a593Smuzhiyun #define WM8994_MIXINL_ENA_SHIFT 9 /* MIXINL_ENA */ 969*4882a593Smuzhiyun #define WM8994_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */ 970*4882a593Smuzhiyun #define WM8994_MIXINR_ENA 0x0100 /* MIXINR_ENA */ 971*4882a593Smuzhiyun #define WM8994_MIXINR_ENA_MASK 0x0100 /* MIXINR_ENA */ 972*4882a593Smuzhiyun #define WM8994_MIXINR_ENA_SHIFT 8 /* MIXINR_ENA */ 973*4882a593Smuzhiyun #define WM8994_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */ 974*4882a593Smuzhiyun #define WM8994_IN2L_ENA 0x0080 /* IN2L_ENA */ 975*4882a593Smuzhiyun #define WM8994_IN2L_ENA_MASK 0x0080 /* IN2L_ENA */ 976*4882a593Smuzhiyun #define WM8994_IN2L_ENA_SHIFT 7 /* IN2L_ENA */ 977*4882a593Smuzhiyun #define WM8994_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 978*4882a593Smuzhiyun #define WM8994_IN1L_ENA 0x0040 /* IN1L_ENA */ 979*4882a593Smuzhiyun #define WM8994_IN1L_ENA_MASK 0x0040 /* IN1L_ENA */ 980*4882a593Smuzhiyun #define WM8994_IN1L_ENA_SHIFT 6 /* IN1L_ENA */ 981*4882a593Smuzhiyun #define WM8994_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 982*4882a593Smuzhiyun #define WM8994_IN2R_ENA 0x0020 /* IN2R_ENA */ 983*4882a593Smuzhiyun #define WM8994_IN2R_ENA_MASK 0x0020 /* IN2R_ENA */ 984*4882a593Smuzhiyun #define WM8994_IN2R_ENA_SHIFT 5 /* IN2R_ENA */ 985*4882a593Smuzhiyun #define WM8994_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 986*4882a593Smuzhiyun #define WM8994_IN1R_ENA 0x0010 /* IN1R_ENA */ 987*4882a593Smuzhiyun #define WM8994_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ 988*4882a593Smuzhiyun #define WM8994_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ 989*4882a593Smuzhiyun #define WM8994_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 990*4882a593Smuzhiyun 991*4882a593Smuzhiyun /* 992*4882a593Smuzhiyun * R3 (0x03) - Power Management (3) 993*4882a593Smuzhiyun */ 994*4882a593Smuzhiyun #define WM8994_LINEOUT1N_ENA 0x2000 /* LINEOUT1N_ENA */ 995*4882a593Smuzhiyun #define WM8994_LINEOUT1N_ENA_MASK 0x2000 /* LINEOUT1N_ENA */ 996*4882a593Smuzhiyun #define WM8994_LINEOUT1N_ENA_SHIFT 13 /* LINEOUT1N_ENA */ 997*4882a593Smuzhiyun #define WM8994_LINEOUT1N_ENA_WIDTH 1 /* LINEOUT1N_ENA */ 998*4882a593Smuzhiyun #define WM8994_LINEOUT1P_ENA 0x1000 /* LINEOUT1P_ENA */ 999*4882a593Smuzhiyun #define WM8994_LINEOUT1P_ENA_MASK 0x1000 /* LINEOUT1P_ENA */ 1000*4882a593Smuzhiyun #define WM8994_LINEOUT1P_ENA_SHIFT 12 /* LINEOUT1P_ENA */ 1001*4882a593Smuzhiyun #define WM8994_LINEOUT1P_ENA_WIDTH 1 /* LINEOUT1P_ENA */ 1002*4882a593Smuzhiyun #define WM8994_LINEOUT2N_ENA 0x0800 /* LINEOUT2N_ENA */ 1003*4882a593Smuzhiyun #define WM8994_LINEOUT2N_ENA_MASK 0x0800 /* LINEOUT2N_ENA */ 1004*4882a593Smuzhiyun #define WM8994_LINEOUT2N_ENA_SHIFT 11 /* LINEOUT2N_ENA */ 1005*4882a593Smuzhiyun #define WM8994_LINEOUT2N_ENA_WIDTH 1 /* LINEOUT2N_ENA */ 1006*4882a593Smuzhiyun #define WM8994_LINEOUT2P_ENA 0x0400 /* LINEOUT2P_ENA */ 1007*4882a593Smuzhiyun #define WM8994_LINEOUT2P_ENA_MASK 0x0400 /* LINEOUT2P_ENA */ 1008*4882a593Smuzhiyun #define WM8994_LINEOUT2P_ENA_SHIFT 10 /* LINEOUT2P_ENA */ 1009*4882a593Smuzhiyun #define WM8994_LINEOUT2P_ENA_WIDTH 1 /* LINEOUT2P_ENA */ 1010*4882a593Smuzhiyun #define WM8994_SPKRVOL_ENA 0x0200 /* SPKRVOL_ENA */ 1011*4882a593Smuzhiyun #define WM8994_SPKRVOL_ENA_MASK 0x0200 /* SPKRVOL_ENA */ 1012*4882a593Smuzhiyun #define WM8994_SPKRVOL_ENA_SHIFT 9 /* SPKRVOL_ENA */ 1013*4882a593Smuzhiyun #define WM8994_SPKRVOL_ENA_WIDTH 1 /* SPKRVOL_ENA */ 1014*4882a593Smuzhiyun #define WM8994_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */ 1015*4882a593Smuzhiyun #define WM8994_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */ 1016*4882a593Smuzhiyun #define WM8994_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */ 1017*4882a593Smuzhiyun #define WM8994_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */ 1018*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_ENA 0x0080 /* MIXOUTLVOL_ENA */ 1019*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_ENA_MASK 0x0080 /* MIXOUTLVOL_ENA */ 1020*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_ENA_SHIFT 7 /* MIXOUTLVOL_ENA */ 1021*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_ENA_WIDTH 1 /* MIXOUTLVOL_ENA */ 1022*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_ENA 0x0040 /* MIXOUTRVOL_ENA */ 1023*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_ENA_MASK 0x0040 /* MIXOUTRVOL_ENA */ 1024*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_ENA_SHIFT 6 /* MIXOUTRVOL_ENA */ 1025*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_ENA_WIDTH 1 /* MIXOUTRVOL_ENA */ 1026*4882a593Smuzhiyun #define WM8994_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */ 1027*4882a593Smuzhiyun #define WM8994_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */ 1028*4882a593Smuzhiyun #define WM8994_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */ 1029*4882a593Smuzhiyun #define WM8994_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */ 1030*4882a593Smuzhiyun #define WM8994_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */ 1031*4882a593Smuzhiyun #define WM8994_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */ 1032*4882a593Smuzhiyun #define WM8994_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */ 1033*4882a593Smuzhiyun #define WM8994_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */ 1034*4882a593Smuzhiyun 1035*4882a593Smuzhiyun /* 1036*4882a593Smuzhiyun * R4 (0x04) - Power Management (4) 1037*4882a593Smuzhiyun */ 1038*4882a593Smuzhiyun #define WM8994_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ 1039*4882a593Smuzhiyun #define WM8994_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ 1040*4882a593Smuzhiyun #define WM8994_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ 1041*4882a593Smuzhiyun #define WM8994_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ 1042*4882a593Smuzhiyun #define WM8994_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ 1043*4882a593Smuzhiyun #define WM8994_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ 1044*4882a593Smuzhiyun #define WM8994_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ 1045*4882a593Smuzhiyun #define WM8994_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ 1046*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ 1047*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ 1048*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ 1049*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ 1050*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ 1051*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ 1052*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ 1053*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ 1054*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ 1055*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ 1056*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ 1057*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ 1058*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ 1059*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ 1060*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ 1061*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ 1062*4882a593Smuzhiyun #define WM8994_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 1063*4882a593Smuzhiyun #define WM8994_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 1064*4882a593Smuzhiyun #define WM8994_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 1065*4882a593Smuzhiyun #define WM8994_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 1066*4882a593Smuzhiyun #define WM8994_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 1067*4882a593Smuzhiyun #define WM8994_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 1068*4882a593Smuzhiyun #define WM8994_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 1069*4882a593Smuzhiyun #define WM8994_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 1070*4882a593Smuzhiyun #define WM8994_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 1071*4882a593Smuzhiyun #define WM8994_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 1072*4882a593Smuzhiyun #define WM8994_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 1073*4882a593Smuzhiyun #define WM8994_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 1074*4882a593Smuzhiyun #define WM8994_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 1075*4882a593Smuzhiyun #define WM8994_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 1076*4882a593Smuzhiyun #define WM8994_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 1077*4882a593Smuzhiyun #define WM8994_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 1078*4882a593Smuzhiyun #define WM8994_ADCL_ENA 0x0002 /* ADCL_ENA */ 1079*4882a593Smuzhiyun #define WM8994_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 1080*4882a593Smuzhiyun #define WM8994_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 1081*4882a593Smuzhiyun #define WM8994_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 1082*4882a593Smuzhiyun #define WM8994_ADCR_ENA 0x0001 /* ADCR_ENA */ 1083*4882a593Smuzhiyun #define WM8994_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 1084*4882a593Smuzhiyun #define WM8994_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 1085*4882a593Smuzhiyun #define WM8994_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 1086*4882a593Smuzhiyun 1087*4882a593Smuzhiyun /* 1088*4882a593Smuzhiyun * R5 (0x05) - Power Management (5) 1089*4882a593Smuzhiyun */ 1090*4882a593Smuzhiyun #define WM8994_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ 1091*4882a593Smuzhiyun #define WM8994_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ 1092*4882a593Smuzhiyun #define WM8994_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ 1093*4882a593Smuzhiyun #define WM8994_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ 1094*4882a593Smuzhiyun #define WM8994_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ 1095*4882a593Smuzhiyun #define WM8994_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ 1096*4882a593Smuzhiyun #define WM8994_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ 1097*4882a593Smuzhiyun #define WM8994_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ 1098*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ 1099*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ 1100*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ 1101*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ 1102*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ 1103*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ 1104*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ 1105*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ 1106*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ 1107*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ 1108*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ 1109*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ 1110*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ 1111*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ 1112*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ 1113*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ 1114*4882a593Smuzhiyun #define WM8994_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 1115*4882a593Smuzhiyun #define WM8994_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 1116*4882a593Smuzhiyun #define WM8994_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 1117*4882a593Smuzhiyun #define WM8994_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 1118*4882a593Smuzhiyun #define WM8994_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 1119*4882a593Smuzhiyun #define WM8994_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 1120*4882a593Smuzhiyun #define WM8994_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 1121*4882a593Smuzhiyun #define WM8994_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 1122*4882a593Smuzhiyun #define WM8994_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 1123*4882a593Smuzhiyun #define WM8994_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 1124*4882a593Smuzhiyun #define WM8994_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 1125*4882a593Smuzhiyun #define WM8994_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 1126*4882a593Smuzhiyun #define WM8994_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 1127*4882a593Smuzhiyun #define WM8994_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 1128*4882a593Smuzhiyun #define WM8994_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 1129*4882a593Smuzhiyun #define WM8994_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 1130*4882a593Smuzhiyun 1131*4882a593Smuzhiyun /* 1132*4882a593Smuzhiyun * R6 (0x06) - Power Management (6) 1133*4882a593Smuzhiyun */ 1134*4882a593Smuzhiyun #define WM8958_AIF3ADC_SRC_MASK 0x0600 /* AIF3ADC_SRC - [10:9] */ 1135*4882a593Smuzhiyun #define WM8958_AIF3ADC_SRC_SHIFT 9 /* AIF3ADC_SRC - [10:9] */ 1136*4882a593Smuzhiyun #define WM8958_AIF3ADC_SRC_WIDTH 2 /* AIF3ADC_SRC - [10:9] */ 1137*4882a593Smuzhiyun #define WM8958_AIF2DAC_SRC_MASK 0x0180 /* AIF2DAC_SRC - [8:7] */ 1138*4882a593Smuzhiyun #define WM8958_AIF2DAC_SRC_SHIFT 7 /* AIF2DAC_SRC - [8:7] */ 1139*4882a593Smuzhiyun #define WM8958_AIF2DAC_SRC_WIDTH 2 /* AIF2DAC_SRC - [8:7] */ 1140*4882a593Smuzhiyun #define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */ 1141*4882a593Smuzhiyun #define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ 1142*4882a593Smuzhiyun #define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ 1143*4882a593Smuzhiyun #define WM8994_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 1144*4882a593Smuzhiyun #define WM8994_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ 1145*4882a593Smuzhiyun #define WM8994_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ 1146*4882a593Smuzhiyun #define WM8994_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ 1147*4882a593Smuzhiyun #define WM8994_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ 1148*4882a593Smuzhiyun #define WM8994_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ 1149*4882a593Smuzhiyun #define WM8994_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ 1150*4882a593Smuzhiyun #define WM8994_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ 1151*4882a593Smuzhiyun #define WM8994_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ 1152*4882a593Smuzhiyun #define WM8994_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ 1153*4882a593Smuzhiyun #define WM8994_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ 1154*4882a593Smuzhiyun #define WM8994_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ 1155*4882a593Smuzhiyun #define WM8994_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ 1156*4882a593Smuzhiyun #define WM8994_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ 1157*4882a593Smuzhiyun #define WM8994_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ 1158*4882a593Smuzhiyun #define WM8994_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ 1159*4882a593Smuzhiyun 1160*4882a593Smuzhiyun /* 1161*4882a593Smuzhiyun * R21 (0x15) - Input Mixer (1) 1162*4882a593Smuzhiyun */ 1163*4882a593Smuzhiyun #define WM8994_IN1RP_MIXINR_BOOST 0x0100 /* IN1RP_MIXINR_BOOST */ 1164*4882a593Smuzhiyun #define WM8994_IN1RP_MIXINR_BOOST_MASK 0x0100 /* IN1RP_MIXINR_BOOST */ 1165*4882a593Smuzhiyun #define WM8994_IN1RP_MIXINR_BOOST_SHIFT 8 /* IN1RP_MIXINR_BOOST */ 1166*4882a593Smuzhiyun #define WM8994_IN1RP_MIXINR_BOOST_WIDTH 1 /* IN1RP_MIXINR_BOOST */ 1167*4882a593Smuzhiyun #define WM8994_IN1LP_MIXINL_BOOST 0x0080 /* IN1LP_MIXINL_BOOST */ 1168*4882a593Smuzhiyun #define WM8994_IN1LP_MIXINL_BOOST_MASK 0x0080 /* IN1LP_MIXINL_BOOST */ 1169*4882a593Smuzhiyun #define WM8994_IN1LP_MIXINL_BOOST_SHIFT 7 /* IN1LP_MIXINL_BOOST */ 1170*4882a593Smuzhiyun #define WM8994_IN1LP_MIXINL_BOOST_WIDTH 1 /* IN1LP_MIXINL_BOOST */ 1171*4882a593Smuzhiyun #define WM8994_INPUTS_CLAMP 0x0040 /* INPUTS_CLAMP */ 1172*4882a593Smuzhiyun #define WM8994_INPUTS_CLAMP_MASK 0x0040 /* INPUTS_CLAMP */ 1173*4882a593Smuzhiyun #define WM8994_INPUTS_CLAMP_SHIFT 6 /* INPUTS_CLAMP */ 1174*4882a593Smuzhiyun #define WM8994_INPUTS_CLAMP_WIDTH 1 /* INPUTS_CLAMP */ 1175*4882a593Smuzhiyun 1176*4882a593Smuzhiyun /* 1177*4882a593Smuzhiyun * R24 (0x18) - Left Line Input 1&2 Volume 1178*4882a593Smuzhiyun */ 1179*4882a593Smuzhiyun #define WM8994_IN1_VU 0x0100 /* IN1_VU */ 1180*4882a593Smuzhiyun #define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */ 1181*4882a593Smuzhiyun #define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */ 1182*4882a593Smuzhiyun #define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */ 1183*4882a593Smuzhiyun #define WM8994_IN1L_MUTE 0x0080 /* IN1L_MUTE */ 1184*4882a593Smuzhiyun #define WM8994_IN1L_MUTE_MASK 0x0080 /* IN1L_MUTE */ 1185*4882a593Smuzhiyun #define WM8994_IN1L_MUTE_SHIFT 7 /* IN1L_MUTE */ 1186*4882a593Smuzhiyun #define WM8994_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 1187*4882a593Smuzhiyun #define WM8994_IN1L_ZC 0x0040 /* IN1L_ZC */ 1188*4882a593Smuzhiyun #define WM8994_IN1L_ZC_MASK 0x0040 /* IN1L_ZC */ 1189*4882a593Smuzhiyun #define WM8994_IN1L_ZC_SHIFT 6 /* IN1L_ZC */ 1190*4882a593Smuzhiyun #define WM8994_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 1191*4882a593Smuzhiyun #define WM8994_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 1192*4882a593Smuzhiyun #define WM8994_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 1193*4882a593Smuzhiyun #define WM8994_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 1194*4882a593Smuzhiyun 1195*4882a593Smuzhiyun /* 1196*4882a593Smuzhiyun * R25 (0x19) - Left Line Input 3&4 Volume 1197*4882a593Smuzhiyun */ 1198*4882a593Smuzhiyun #define WM8994_IN2_VU 0x0100 /* IN2_VU */ 1199*4882a593Smuzhiyun #define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */ 1200*4882a593Smuzhiyun #define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */ 1201*4882a593Smuzhiyun #define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */ 1202*4882a593Smuzhiyun #define WM8994_IN2L_MUTE 0x0080 /* IN2L_MUTE */ 1203*4882a593Smuzhiyun #define WM8994_IN2L_MUTE_MASK 0x0080 /* IN2L_MUTE */ 1204*4882a593Smuzhiyun #define WM8994_IN2L_MUTE_SHIFT 7 /* IN2L_MUTE */ 1205*4882a593Smuzhiyun #define WM8994_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 1206*4882a593Smuzhiyun #define WM8994_IN2L_ZC 0x0040 /* IN2L_ZC */ 1207*4882a593Smuzhiyun #define WM8994_IN2L_ZC_MASK 0x0040 /* IN2L_ZC */ 1208*4882a593Smuzhiyun #define WM8994_IN2L_ZC_SHIFT 6 /* IN2L_ZC */ 1209*4882a593Smuzhiyun #define WM8994_IN2L_ZC_WIDTH 1 /* IN2L_ZC */ 1210*4882a593Smuzhiyun #define WM8994_IN2L_VOL_MASK 0x001F /* IN2L_VOL - [4:0] */ 1211*4882a593Smuzhiyun #define WM8994_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [4:0] */ 1212*4882a593Smuzhiyun #define WM8994_IN2L_VOL_WIDTH 5 /* IN2L_VOL - [4:0] */ 1213*4882a593Smuzhiyun 1214*4882a593Smuzhiyun /* 1215*4882a593Smuzhiyun * R26 (0x1A) - Right Line Input 1&2 Volume 1216*4882a593Smuzhiyun */ 1217*4882a593Smuzhiyun #define WM8994_IN1_VU 0x0100 /* IN1_VU */ 1218*4882a593Smuzhiyun #define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */ 1219*4882a593Smuzhiyun #define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */ 1220*4882a593Smuzhiyun #define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */ 1221*4882a593Smuzhiyun #define WM8994_IN1R_MUTE 0x0080 /* IN1R_MUTE */ 1222*4882a593Smuzhiyun #define WM8994_IN1R_MUTE_MASK 0x0080 /* IN1R_MUTE */ 1223*4882a593Smuzhiyun #define WM8994_IN1R_MUTE_SHIFT 7 /* IN1R_MUTE */ 1224*4882a593Smuzhiyun #define WM8994_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 1225*4882a593Smuzhiyun #define WM8994_IN1R_ZC 0x0040 /* IN1R_ZC */ 1226*4882a593Smuzhiyun #define WM8994_IN1R_ZC_MASK 0x0040 /* IN1R_ZC */ 1227*4882a593Smuzhiyun #define WM8994_IN1R_ZC_SHIFT 6 /* IN1R_ZC */ 1228*4882a593Smuzhiyun #define WM8994_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 1229*4882a593Smuzhiyun #define WM8994_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 1230*4882a593Smuzhiyun #define WM8994_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 1231*4882a593Smuzhiyun #define WM8994_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 1232*4882a593Smuzhiyun 1233*4882a593Smuzhiyun /* 1234*4882a593Smuzhiyun * R27 (0x1B) - Right Line Input 3&4 Volume 1235*4882a593Smuzhiyun */ 1236*4882a593Smuzhiyun #define WM8994_IN2_VU 0x0100 /* IN2_VU */ 1237*4882a593Smuzhiyun #define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */ 1238*4882a593Smuzhiyun #define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */ 1239*4882a593Smuzhiyun #define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */ 1240*4882a593Smuzhiyun #define WM8994_IN2R_MUTE 0x0080 /* IN2R_MUTE */ 1241*4882a593Smuzhiyun #define WM8994_IN2R_MUTE_MASK 0x0080 /* IN2R_MUTE */ 1242*4882a593Smuzhiyun #define WM8994_IN2R_MUTE_SHIFT 7 /* IN2R_MUTE */ 1243*4882a593Smuzhiyun #define WM8994_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 1244*4882a593Smuzhiyun #define WM8994_IN2R_ZC 0x0040 /* IN2R_ZC */ 1245*4882a593Smuzhiyun #define WM8994_IN2R_ZC_MASK 0x0040 /* IN2R_ZC */ 1246*4882a593Smuzhiyun #define WM8994_IN2R_ZC_SHIFT 6 /* IN2R_ZC */ 1247*4882a593Smuzhiyun #define WM8994_IN2R_ZC_WIDTH 1 /* IN2R_ZC */ 1248*4882a593Smuzhiyun #define WM8994_IN2R_VOL_MASK 0x001F /* IN2R_VOL - [4:0] */ 1249*4882a593Smuzhiyun #define WM8994_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [4:0] */ 1250*4882a593Smuzhiyun #define WM8994_IN2R_VOL_WIDTH 5 /* IN2R_VOL - [4:0] */ 1251*4882a593Smuzhiyun 1252*4882a593Smuzhiyun /* 1253*4882a593Smuzhiyun * R28 (0x1C) - Left Output Volume 1254*4882a593Smuzhiyun */ 1255*4882a593Smuzhiyun #define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 1256*4882a593Smuzhiyun #define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 1257*4882a593Smuzhiyun #define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 1258*4882a593Smuzhiyun #define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 1259*4882a593Smuzhiyun #define WM8994_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ 1260*4882a593Smuzhiyun #define WM8994_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ 1261*4882a593Smuzhiyun #define WM8994_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ 1262*4882a593Smuzhiyun #define WM8994_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 1263*4882a593Smuzhiyun #define WM8994_HPOUT1L_MUTE_N 0x0040 /* HPOUT1L_MUTE_N */ 1264*4882a593Smuzhiyun #define WM8994_HPOUT1L_MUTE_N_MASK 0x0040 /* HPOUT1L_MUTE_N */ 1265*4882a593Smuzhiyun #define WM8994_HPOUT1L_MUTE_N_SHIFT 6 /* HPOUT1L_MUTE_N */ 1266*4882a593Smuzhiyun #define WM8994_HPOUT1L_MUTE_N_WIDTH 1 /* HPOUT1L_MUTE_N */ 1267*4882a593Smuzhiyun #define WM8994_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */ 1268*4882a593Smuzhiyun #define WM8994_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */ 1269*4882a593Smuzhiyun #define WM8994_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */ 1270*4882a593Smuzhiyun 1271*4882a593Smuzhiyun /* 1272*4882a593Smuzhiyun * R29 (0x1D) - Right Output Volume 1273*4882a593Smuzhiyun */ 1274*4882a593Smuzhiyun #define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 1275*4882a593Smuzhiyun #define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 1276*4882a593Smuzhiyun #define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 1277*4882a593Smuzhiyun #define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 1278*4882a593Smuzhiyun #define WM8994_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ 1279*4882a593Smuzhiyun #define WM8994_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ 1280*4882a593Smuzhiyun #define WM8994_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ 1281*4882a593Smuzhiyun #define WM8994_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 1282*4882a593Smuzhiyun #define WM8994_HPOUT1R_MUTE_N 0x0040 /* HPOUT1R_MUTE_N */ 1283*4882a593Smuzhiyun #define WM8994_HPOUT1R_MUTE_N_MASK 0x0040 /* HPOUT1R_MUTE_N */ 1284*4882a593Smuzhiyun #define WM8994_HPOUT1R_MUTE_N_SHIFT 6 /* HPOUT1R_MUTE_N */ 1285*4882a593Smuzhiyun #define WM8994_HPOUT1R_MUTE_N_WIDTH 1 /* HPOUT1R_MUTE_N */ 1286*4882a593Smuzhiyun #define WM8994_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */ 1287*4882a593Smuzhiyun #define WM8994_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */ 1288*4882a593Smuzhiyun #define WM8994_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */ 1289*4882a593Smuzhiyun 1290*4882a593Smuzhiyun /* 1291*4882a593Smuzhiyun * R30 (0x1E) - Line Outputs Volume 1292*4882a593Smuzhiyun */ 1293*4882a593Smuzhiyun #define WM8994_LINEOUT1N_MUTE 0x0040 /* LINEOUT1N_MUTE */ 1294*4882a593Smuzhiyun #define WM8994_LINEOUT1N_MUTE_MASK 0x0040 /* LINEOUT1N_MUTE */ 1295*4882a593Smuzhiyun #define WM8994_LINEOUT1N_MUTE_SHIFT 6 /* LINEOUT1N_MUTE */ 1296*4882a593Smuzhiyun #define WM8994_LINEOUT1N_MUTE_WIDTH 1 /* LINEOUT1N_MUTE */ 1297*4882a593Smuzhiyun #define WM8994_LINEOUT1P_MUTE 0x0020 /* LINEOUT1P_MUTE */ 1298*4882a593Smuzhiyun #define WM8994_LINEOUT1P_MUTE_MASK 0x0020 /* LINEOUT1P_MUTE */ 1299*4882a593Smuzhiyun #define WM8994_LINEOUT1P_MUTE_SHIFT 5 /* LINEOUT1P_MUTE */ 1300*4882a593Smuzhiyun #define WM8994_LINEOUT1P_MUTE_WIDTH 1 /* LINEOUT1P_MUTE */ 1301*4882a593Smuzhiyun #define WM8994_LINEOUT1_VOL 0x0010 /* LINEOUT1_VOL */ 1302*4882a593Smuzhiyun #define WM8994_LINEOUT1_VOL_MASK 0x0010 /* LINEOUT1_VOL */ 1303*4882a593Smuzhiyun #define WM8994_LINEOUT1_VOL_SHIFT 4 /* LINEOUT1_VOL */ 1304*4882a593Smuzhiyun #define WM8994_LINEOUT1_VOL_WIDTH 1 /* LINEOUT1_VOL */ 1305*4882a593Smuzhiyun #define WM8994_LINEOUT2N_MUTE 0x0004 /* LINEOUT2N_MUTE */ 1306*4882a593Smuzhiyun #define WM8994_LINEOUT2N_MUTE_MASK 0x0004 /* LINEOUT2N_MUTE */ 1307*4882a593Smuzhiyun #define WM8994_LINEOUT2N_MUTE_SHIFT 2 /* LINEOUT2N_MUTE */ 1308*4882a593Smuzhiyun #define WM8994_LINEOUT2N_MUTE_WIDTH 1 /* LINEOUT2N_MUTE */ 1309*4882a593Smuzhiyun #define WM8994_LINEOUT2P_MUTE 0x0002 /* LINEOUT2P_MUTE */ 1310*4882a593Smuzhiyun #define WM8994_LINEOUT2P_MUTE_MASK 0x0002 /* LINEOUT2P_MUTE */ 1311*4882a593Smuzhiyun #define WM8994_LINEOUT2P_MUTE_SHIFT 1 /* LINEOUT2P_MUTE */ 1312*4882a593Smuzhiyun #define WM8994_LINEOUT2P_MUTE_WIDTH 1 /* LINEOUT2P_MUTE */ 1313*4882a593Smuzhiyun #define WM8994_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */ 1314*4882a593Smuzhiyun #define WM8994_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */ 1315*4882a593Smuzhiyun #define WM8994_LINEOUT2_VOL_SHIFT 0 /* LINEOUT2_VOL */ 1316*4882a593Smuzhiyun #define WM8994_LINEOUT2_VOL_WIDTH 1 /* LINEOUT2_VOL */ 1317*4882a593Smuzhiyun 1318*4882a593Smuzhiyun /* 1319*4882a593Smuzhiyun * R31 (0x1F) - HPOUT2 Volume 1320*4882a593Smuzhiyun */ 1321*4882a593Smuzhiyun #define WM8994_HPOUT2_MUTE 0x0020 /* HPOUT2_MUTE */ 1322*4882a593Smuzhiyun #define WM8994_HPOUT2_MUTE_MASK 0x0020 /* HPOUT2_MUTE */ 1323*4882a593Smuzhiyun #define WM8994_HPOUT2_MUTE_SHIFT 5 /* HPOUT2_MUTE */ 1324*4882a593Smuzhiyun #define WM8994_HPOUT2_MUTE_WIDTH 1 /* HPOUT2_MUTE */ 1325*4882a593Smuzhiyun #define WM8994_HPOUT2_VOL 0x0010 /* HPOUT2_VOL */ 1326*4882a593Smuzhiyun #define WM8994_HPOUT2_VOL_MASK 0x0010 /* HPOUT2_VOL */ 1327*4882a593Smuzhiyun #define WM8994_HPOUT2_VOL_SHIFT 4 /* HPOUT2_VOL */ 1328*4882a593Smuzhiyun #define WM8994_HPOUT2_VOL_WIDTH 1 /* HPOUT2_VOL */ 1329*4882a593Smuzhiyun 1330*4882a593Smuzhiyun /* 1331*4882a593Smuzhiyun * R32 (0x20) - Left OPGA Volume 1332*4882a593Smuzhiyun */ 1333*4882a593Smuzhiyun #define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */ 1334*4882a593Smuzhiyun #define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */ 1335*4882a593Smuzhiyun #define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */ 1336*4882a593Smuzhiyun #define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */ 1337*4882a593Smuzhiyun #define WM8994_MIXOUTL_ZC 0x0080 /* MIXOUTL_ZC */ 1338*4882a593Smuzhiyun #define WM8994_MIXOUTL_ZC_MASK 0x0080 /* MIXOUTL_ZC */ 1339*4882a593Smuzhiyun #define WM8994_MIXOUTL_ZC_SHIFT 7 /* MIXOUTL_ZC */ 1340*4882a593Smuzhiyun #define WM8994_MIXOUTL_ZC_WIDTH 1 /* MIXOUTL_ZC */ 1341*4882a593Smuzhiyun #define WM8994_MIXOUTL_MUTE_N 0x0040 /* MIXOUTL_MUTE_N */ 1342*4882a593Smuzhiyun #define WM8994_MIXOUTL_MUTE_N_MASK 0x0040 /* MIXOUTL_MUTE_N */ 1343*4882a593Smuzhiyun #define WM8994_MIXOUTL_MUTE_N_SHIFT 6 /* MIXOUTL_MUTE_N */ 1344*4882a593Smuzhiyun #define WM8994_MIXOUTL_MUTE_N_WIDTH 1 /* MIXOUTL_MUTE_N */ 1345*4882a593Smuzhiyun #define WM8994_MIXOUTL_VOL_MASK 0x003F /* MIXOUTL_VOL - [5:0] */ 1346*4882a593Smuzhiyun #define WM8994_MIXOUTL_VOL_SHIFT 0 /* MIXOUTL_VOL - [5:0] */ 1347*4882a593Smuzhiyun #define WM8994_MIXOUTL_VOL_WIDTH 6 /* MIXOUTL_VOL - [5:0] */ 1348*4882a593Smuzhiyun 1349*4882a593Smuzhiyun /* 1350*4882a593Smuzhiyun * R33 (0x21) - Right OPGA Volume 1351*4882a593Smuzhiyun */ 1352*4882a593Smuzhiyun #define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */ 1353*4882a593Smuzhiyun #define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */ 1354*4882a593Smuzhiyun #define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */ 1355*4882a593Smuzhiyun #define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */ 1356*4882a593Smuzhiyun #define WM8994_MIXOUTR_ZC 0x0080 /* MIXOUTR_ZC */ 1357*4882a593Smuzhiyun #define WM8994_MIXOUTR_ZC_MASK 0x0080 /* MIXOUTR_ZC */ 1358*4882a593Smuzhiyun #define WM8994_MIXOUTR_ZC_SHIFT 7 /* MIXOUTR_ZC */ 1359*4882a593Smuzhiyun #define WM8994_MIXOUTR_ZC_WIDTH 1 /* MIXOUTR_ZC */ 1360*4882a593Smuzhiyun #define WM8994_MIXOUTR_MUTE_N 0x0040 /* MIXOUTR_MUTE_N */ 1361*4882a593Smuzhiyun #define WM8994_MIXOUTR_MUTE_N_MASK 0x0040 /* MIXOUTR_MUTE_N */ 1362*4882a593Smuzhiyun #define WM8994_MIXOUTR_MUTE_N_SHIFT 6 /* MIXOUTR_MUTE_N */ 1363*4882a593Smuzhiyun #define WM8994_MIXOUTR_MUTE_N_WIDTH 1 /* MIXOUTR_MUTE_N */ 1364*4882a593Smuzhiyun #define WM8994_MIXOUTR_VOL_MASK 0x003F /* MIXOUTR_VOL - [5:0] */ 1365*4882a593Smuzhiyun #define WM8994_MIXOUTR_VOL_SHIFT 0 /* MIXOUTR_VOL - [5:0] */ 1366*4882a593Smuzhiyun #define WM8994_MIXOUTR_VOL_WIDTH 6 /* MIXOUTR_VOL - [5:0] */ 1367*4882a593Smuzhiyun 1368*4882a593Smuzhiyun /* 1369*4882a593Smuzhiyun * R34 (0x22) - SPKMIXL Attenuation 1370*4882a593Smuzhiyun */ 1371*4882a593Smuzhiyun #define WM8994_DAC2L_SPKMIXL_VOL 0x0040 /* DAC2L_SPKMIXL_VOL */ 1372*4882a593Smuzhiyun #define WM8994_DAC2L_SPKMIXL_VOL_MASK 0x0040 /* DAC2L_SPKMIXL_VOL */ 1373*4882a593Smuzhiyun #define WM8994_DAC2L_SPKMIXL_VOL_SHIFT 6 /* DAC2L_SPKMIXL_VOL */ 1374*4882a593Smuzhiyun #define WM8994_DAC2L_SPKMIXL_VOL_WIDTH 1 /* DAC2L_SPKMIXL_VOL */ 1375*4882a593Smuzhiyun #define WM8994_MIXINL_SPKMIXL_VOL 0x0020 /* MIXINL_SPKMIXL_VOL */ 1376*4882a593Smuzhiyun #define WM8994_MIXINL_SPKMIXL_VOL_MASK 0x0020 /* MIXINL_SPKMIXL_VOL */ 1377*4882a593Smuzhiyun #define WM8994_MIXINL_SPKMIXL_VOL_SHIFT 5 /* MIXINL_SPKMIXL_VOL */ 1378*4882a593Smuzhiyun #define WM8994_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */ 1379*4882a593Smuzhiyun #define WM8994_IN1LP_SPKMIXL_VOL 0x0010 /* IN1LP_SPKMIXL_VOL */ 1380*4882a593Smuzhiyun #define WM8994_IN1LP_SPKMIXL_VOL_MASK 0x0010 /* IN1LP_SPKMIXL_VOL */ 1381*4882a593Smuzhiyun #define WM8994_IN1LP_SPKMIXL_VOL_SHIFT 4 /* IN1LP_SPKMIXL_VOL */ 1382*4882a593Smuzhiyun #define WM8994_IN1LP_SPKMIXL_VOL_WIDTH 1 /* IN1LP_SPKMIXL_VOL */ 1383*4882a593Smuzhiyun #define WM8994_MIXOUTL_SPKMIXL_VOL 0x0008 /* MIXOUTL_SPKMIXL_VOL */ 1384*4882a593Smuzhiyun #define WM8994_MIXOUTL_SPKMIXL_VOL_MASK 0x0008 /* MIXOUTL_SPKMIXL_VOL */ 1385*4882a593Smuzhiyun #define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT 3 /* MIXOUTL_SPKMIXL_VOL */ 1386*4882a593Smuzhiyun #define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH 1 /* MIXOUTL_SPKMIXL_VOL */ 1387*4882a593Smuzhiyun #define WM8994_DAC1L_SPKMIXL_VOL 0x0004 /* DAC1L_SPKMIXL_VOL */ 1388*4882a593Smuzhiyun #define WM8994_DAC1L_SPKMIXL_VOL_MASK 0x0004 /* DAC1L_SPKMIXL_VOL */ 1389*4882a593Smuzhiyun #define WM8994_DAC1L_SPKMIXL_VOL_SHIFT 2 /* DAC1L_SPKMIXL_VOL */ 1390*4882a593Smuzhiyun #define WM8994_DAC1L_SPKMIXL_VOL_WIDTH 1 /* DAC1L_SPKMIXL_VOL */ 1391*4882a593Smuzhiyun #define WM8994_SPKMIXL_VOL_MASK 0x0003 /* SPKMIXL_VOL - [1:0] */ 1392*4882a593Smuzhiyun #define WM8994_SPKMIXL_VOL_SHIFT 0 /* SPKMIXL_VOL - [1:0] */ 1393*4882a593Smuzhiyun #define WM8994_SPKMIXL_VOL_WIDTH 2 /* SPKMIXL_VOL - [1:0] */ 1394*4882a593Smuzhiyun 1395*4882a593Smuzhiyun /* 1396*4882a593Smuzhiyun * R35 (0x23) - SPKMIXR Attenuation 1397*4882a593Smuzhiyun */ 1398*4882a593Smuzhiyun #define WM8994_SPKOUT_CLASSAB 0x0100 /* SPKOUT_CLASSAB */ 1399*4882a593Smuzhiyun #define WM8994_SPKOUT_CLASSAB_MASK 0x0100 /* SPKOUT_CLASSAB */ 1400*4882a593Smuzhiyun #define WM8994_SPKOUT_CLASSAB_SHIFT 8 /* SPKOUT_CLASSAB */ 1401*4882a593Smuzhiyun #define WM8994_SPKOUT_CLASSAB_WIDTH 1 /* SPKOUT_CLASSAB */ 1402*4882a593Smuzhiyun #define WM8994_DAC2R_SPKMIXR_VOL 0x0040 /* DAC2R_SPKMIXR_VOL */ 1403*4882a593Smuzhiyun #define WM8994_DAC2R_SPKMIXR_VOL_MASK 0x0040 /* DAC2R_SPKMIXR_VOL */ 1404*4882a593Smuzhiyun #define WM8994_DAC2R_SPKMIXR_VOL_SHIFT 6 /* DAC2R_SPKMIXR_VOL */ 1405*4882a593Smuzhiyun #define WM8994_DAC2R_SPKMIXR_VOL_WIDTH 1 /* DAC2R_SPKMIXR_VOL */ 1406*4882a593Smuzhiyun #define WM8994_MIXINR_SPKMIXR_VOL 0x0020 /* MIXINR_SPKMIXR_VOL */ 1407*4882a593Smuzhiyun #define WM8994_MIXINR_SPKMIXR_VOL_MASK 0x0020 /* MIXINR_SPKMIXR_VOL */ 1408*4882a593Smuzhiyun #define WM8994_MIXINR_SPKMIXR_VOL_SHIFT 5 /* MIXINR_SPKMIXR_VOL */ 1409*4882a593Smuzhiyun #define WM8994_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */ 1410*4882a593Smuzhiyun #define WM8994_IN1RP_SPKMIXR_VOL 0x0010 /* IN1RP_SPKMIXR_VOL */ 1411*4882a593Smuzhiyun #define WM8994_IN1RP_SPKMIXR_VOL_MASK 0x0010 /* IN1RP_SPKMIXR_VOL */ 1412*4882a593Smuzhiyun #define WM8994_IN1RP_SPKMIXR_VOL_SHIFT 4 /* IN1RP_SPKMIXR_VOL */ 1413*4882a593Smuzhiyun #define WM8994_IN1RP_SPKMIXR_VOL_WIDTH 1 /* IN1RP_SPKMIXR_VOL */ 1414*4882a593Smuzhiyun #define WM8994_MIXOUTR_SPKMIXR_VOL 0x0008 /* MIXOUTR_SPKMIXR_VOL */ 1415*4882a593Smuzhiyun #define WM8994_MIXOUTR_SPKMIXR_VOL_MASK 0x0008 /* MIXOUTR_SPKMIXR_VOL */ 1416*4882a593Smuzhiyun #define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT 3 /* MIXOUTR_SPKMIXR_VOL */ 1417*4882a593Smuzhiyun #define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH 1 /* MIXOUTR_SPKMIXR_VOL */ 1418*4882a593Smuzhiyun #define WM8994_DAC1R_SPKMIXR_VOL 0x0004 /* DAC1R_SPKMIXR_VOL */ 1419*4882a593Smuzhiyun #define WM8994_DAC1R_SPKMIXR_VOL_MASK 0x0004 /* DAC1R_SPKMIXR_VOL */ 1420*4882a593Smuzhiyun #define WM8994_DAC1R_SPKMIXR_VOL_SHIFT 2 /* DAC1R_SPKMIXR_VOL */ 1421*4882a593Smuzhiyun #define WM8994_DAC1R_SPKMIXR_VOL_WIDTH 1 /* DAC1R_SPKMIXR_VOL */ 1422*4882a593Smuzhiyun #define WM8994_SPKMIXR_VOL_MASK 0x0003 /* SPKMIXR_VOL - [1:0] */ 1423*4882a593Smuzhiyun #define WM8994_SPKMIXR_VOL_SHIFT 0 /* SPKMIXR_VOL - [1:0] */ 1424*4882a593Smuzhiyun #define WM8994_SPKMIXR_VOL_WIDTH 2 /* SPKMIXR_VOL - [1:0] */ 1425*4882a593Smuzhiyun 1426*4882a593Smuzhiyun /* 1427*4882a593Smuzhiyun * R36 (0x24) - SPKOUT Mixers 1428*4882a593Smuzhiyun */ 1429*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTL 0x0020 /* IN2LRP_TO_SPKOUTL */ 1430*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTL_MASK 0x0020 /* IN2LRP_TO_SPKOUTL */ 1431*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTL_SHIFT 5 /* IN2LRP_TO_SPKOUTL */ 1432*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTL_WIDTH 1 /* IN2LRP_TO_SPKOUTL */ 1433*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */ 1434*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */ 1435*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */ 1436*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */ 1437*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTL 0x0008 /* SPKMIXR_TO_SPKOUTL */ 1438*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTL_MASK 0x0008 /* SPKMIXR_TO_SPKOUTL */ 1439*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT 3 /* SPKMIXR_TO_SPKOUTL */ 1440*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH 1 /* SPKMIXR_TO_SPKOUTL */ 1441*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTR 0x0004 /* IN2LRP_TO_SPKOUTR */ 1442*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTR_MASK 0x0004 /* IN2LRP_TO_SPKOUTR */ 1443*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTR_SHIFT 2 /* IN2LRP_TO_SPKOUTR */ 1444*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_SPKOUTR_WIDTH 1 /* IN2LRP_TO_SPKOUTR */ 1445*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTR 0x0002 /* SPKMIXL_TO_SPKOUTR */ 1446*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTR_MASK 0x0002 /* SPKMIXL_TO_SPKOUTR */ 1447*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT 1 /* SPKMIXL_TO_SPKOUTR */ 1448*4882a593Smuzhiyun #define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH 1 /* SPKMIXL_TO_SPKOUTR */ 1449*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */ 1450*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */ 1451*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT 0 /* SPKMIXR_TO_SPKOUTR */ 1452*4882a593Smuzhiyun #define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH 1 /* SPKMIXR_TO_SPKOUTR */ 1453*4882a593Smuzhiyun 1454*4882a593Smuzhiyun /* 1455*4882a593Smuzhiyun * R37 (0x25) - ClassD 1456*4882a593Smuzhiyun */ 1457*4882a593Smuzhiyun #define WM8994_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */ 1458*4882a593Smuzhiyun #define WM8994_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */ 1459*4882a593Smuzhiyun #define WM8994_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */ 1460*4882a593Smuzhiyun #define WM8994_SPKOUTR_BOOST_MASK 0x0007 /* SPKOUTR_BOOST - [2:0] */ 1461*4882a593Smuzhiyun #define WM8994_SPKOUTR_BOOST_SHIFT 0 /* SPKOUTR_BOOST - [2:0] */ 1462*4882a593Smuzhiyun #define WM8994_SPKOUTR_BOOST_WIDTH 3 /* SPKOUTR_BOOST - [2:0] */ 1463*4882a593Smuzhiyun 1464*4882a593Smuzhiyun /* 1465*4882a593Smuzhiyun * R38 (0x26) - Speaker Volume Left 1466*4882a593Smuzhiyun */ 1467*4882a593Smuzhiyun #define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 1468*4882a593Smuzhiyun #define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 1469*4882a593Smuzhiyun #define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 1470*4882a593Smuzhiyun #define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 1471*4882a593Smuzhiyun #define WM8994_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */ 1472*4882a593Smuzhiyun #define WM8994_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */ 1473*4882a593Smuzhiyun #define WM8994_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */ 1474*4882a593Smuzhiyun #define WM8994_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */ 1475*4882a593Smuzhiyun #define WM8994_SPKOUTL_MUTE_N 0x0040 /* SPKOUTL_MUTE_N */ 1476*4882a593Smuzhiyun #define WM8994_SPKOUTL_MUTE_N_MASK 0x0040 /* SPKOUTL_MUTE_N */ 1477*4882a593Smuzhiyun #define WM8994_SPKOUTL_MUTE_N_SHIFT 6 /* SPKOUTL_MUTE_N */ 1478*4882a593Smuzhiyun #define WM8994_SPKOUTL_MUTE_N_WIDTH 1 /* SPKOUTL_MUTE_N */ 1479*4882a593Smuzhiyun #define WM8994_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */ 1480*4882a593Smuzhiyun #define WM8994_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */ 1481*4882a593Smuzhiyun #define WM8994_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */ 1482*4882a593Smuzhiyun 1483*4882a593Smuzhiyun /* 1484*4882a593Smuzhiyun * R39 (0x27) - Speaker Volume Right 1485*4882a593Smuzhiyun */ 1486*4882a593Smuzhiyun #define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 1487*4882a593Smuzhiyun #define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 1488*4882a593Smuzhiyun #define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 1489*4882a593Smuzhiyun #define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 1490*4882a593Smuzhiyun #define WM8994_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */ 1491*4882a593Smuzhiyun #define WM8994_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */ 1492*4882a593Smuzhiyun #define WM8994_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */ 1493*4882a593Smuzhiyun #define WM8994_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */ 1494*4882a593Smuzhiyun #define WM8994_SPKOUTR_MUTE_N 0x0040 /* SPKOUTR_MUTE_N */ 1495*4882a593Smuzhiyun #define WM8994_SPKOUTR_MUTE_N_MASK 0x0040 /* SPKOUTR_MUTE_N */ 1496*4882a593Smuzhiyun #define WM8994_SPKOUTR_MUTE_N_SHIFT 6 /* SPKOUTR_MUTE_N */ 1497*4882a593Smuzhiyun #define WM8994_SPKOUTR_MUTE_N_WIDTH 1 /* SPKOUTR_MUTE_N */ 1498*4882a593Smuzhiyun #define WM8994_SPKOUTR_VOL_MASK 0x003F /* SPKOUTR_VOL - [5:0] */ 1499*4882a593Smuzhiyun #define WM8994_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [5:0] */ 1500*4882a593Smuzhiyun #define WM8994_SPKOUTR_VOL_WIDTH 6 /* SPKOUTR_VOL - [5:0] */ 1501*4882a593Smuzhiyun 1502*4882a593Smuzhiyun /* 1503*4882a593Smuzhiyun * R40 (0x28) - Input Mixer (2) 1504*4882a593Smuzhiyun */ 1505*4882a593Smuzhiyun #define WM8994_IN2LP_TO_IN2L 0x0080 /* IN2LP_TO_IN2L */ 1506*4882a593Smuzhiyun #define WM8994_IN2LP_TO_IN2L_MASK 0x0080 /* IN2LP_TO_IN2L */ 1507*4882a593Smuzhiyun #define WM8994_IN2LP_TO_IN2L_SHIFT 7 /* IN2LP_TO_IN2L */ 1508*4882a593Smuzhiyun #define WM8994_IN2LP_TO_IN2L_WIDTH 1 /* IN2LP_TO_IN2L */ 1509*4882a593Smuzhiyun #define WM8994_IN2LN_TO_IN2L 0x0040 /* IN2LN_TO_IN2L */ 1510*4882a593Smuzhiyun #define WM8994_IN2LN_TO_IN2L_MASK 0x0040 /* IN2LN_TO_IN2L */ 1511*4882a593Smuzhiyun #define WM8994_IN2LN_TO_IN2L_SHIFT 6 /* IN2LN_TO_IN2L */ 1512*4882a593Smuzhiyun #define WM8994_IN2LN_TO_IN2L_WIDTH 1 /* IN2LN_TO_IN2L */ 1513*4882a593Smuzhiyun #define WM8994_IN1LP_TO_IN1L 0x0020 /* IN1LP_TO_IN1L */ 1514*4882a593Smuzhiyun #define WM8994_IN1LP_TO_IN1L_MASK 0x0020 /* IN1LP_TO_IN1L */ 1515*4882a593Smuzhiyun #define WM8994_IN1LP_TO_IN1L_SHIFT 5 /* IN1LP_TO_IN1L */ 1516*4882a593Smuzhiyun #define WM8994_IN1LP_TO_IN1L_WIDTH 1 /* IN1LP_TO_IN1L */ 1517*4882a593Smuzhiyun #define WM8994_IN1LN_TO_IN1L 0x0010 /* IN1LN_TO_IN1L */ 1518*4882a593Smuzhiyun #define WM8994_IN1LN_TO_IN1L_MASK 0x0010 /* IN1LN_TO_IN1L */ 1519*4882a593Smuzhiyun #define WM8994_IN1LN_TO_IN1L_SHIFT 4 /* IN1LN_TO_IN1L */ 1520*4882a593Smuzhiyun #define WM8994_IN1LN_TO_IN1L_WIDTH 1 /* IN1LN_TO_IN1L */ 1521*4882a593Smuzhiyun #define WM8994_IN2RP_TO_IN2R 0x0008 /* IN2RP_TO_IN2R */ 1522*4882a593Smuzhiyun #define WM8994_IN2RP_TO_IN2R_MASK 0x0008 /* IN2RP_TO_IN2R */ 1523*4882a593Smuzhiyun #define WM8994_IN2RP_TO_IN2R_SHIFT 3 /* IN2RP_TO_IN2R */ 1524*4882a593Smuzhiyun #define WM8994_IN2RP_TO_IN2R_WIDTH 1 /* IN2RP_TO_IN2R */ 1525*4882a593Smuzhiyun #define WM8994_IN2RN_TO_IN2R 0x0004 /* IN2RN_TO_IN2R */ 1526*4882a593Smuzhiyun #define WM8994_IN2RN_TO_IN2R_MASK 0x0004 /* IN2RN_TO_IN2R */ 1527*4882a593Smuzhiyun #define WM8994_IN2RN_TO_IN2R_SHIFT 2 /* IN2RN_TO_IN2R */ 1528*4882a593Smuzhiyun #define WM8994_IN2RN_TO_IN2R_WIDTH 1 /* IN2RN_TO_IN2R */ 1529*4882a593Smuzhiyun #define WM8994_IN1RP_TO_IN1R 0x0002 /* IN1RP_TO_IN1R */ 1530*4882a593Smuzhiyun #define WM8994_IN1RP_TO_IN1R_MASK 0x0002 /* IN1RP_TO_IN1R */ 1531*4882a593Smuzhiyun #define WM8994_IN1RP_TO_IN1R_SHIFT 1 /* IN1RP_TO_IN1R */ 1532*4882a593Smuzhiyun #define WM8994_IN1RP_TO_IN1R_WIDTH 1 /* IN1RP_TO_IN1R */ 1533*4882a593Smuzhiyun #define WM8994_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */ 1534*4882a593Smuzhiyun #define WM8994_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */ 1535*4882a593Smuzhiyun #define WM8994_IN1RN_TO_IN1R_SHIFT 0 /* IN1RN_TO_IN1R */ 1536*4882a593Smuzhiyun #define WM8994_IN1RN_TO_IN1R_WIDTH 1 /* IN1RN_TO_IN1R */ 1537*4882a593Smuzhiyun 1538*4882a593Smuzhiyun /* 1539*4882a593Smuzhiyun * R41 (0x29) - Input Mixer (3) 1540*4882a593Smuzhiyun */ 1541*4882a593Smuzhiyun #define WM8994_IN2L_TO_MIXINL 0x0100 /* IN2L_TO_MIXINL */ 1542*4882a593Smuzhiyun #define WM8994_IN2L_TO_MIXINL_MASK 0x0100 /* IN2L_TO_MIXINL */ 1543*4882a593Smuzhiyun #define WM8994_IN2L_TO_MIXINL_SHIFT 8 /* IN2L_TO_MIXINL */ 1544*4882a593Smuzhiyun #define WM8994_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */ 1545*4882a593Smuzhiyun #define WM8994_IN2L_MIXINL_VOL 0x0080 /* IN2L_MIXINL_VOL */ 1546*4882a593Smuzhiyun #define WM8994_IN2L_MIXINL_VOL_MASK 0x0080 /* IN2L_MIXINL_VOL */ 1547*4882a593Smuzhiyun #define WM8994_IN2L_MIXINL_VOL_SHIFT 7 /* IN2L_MIXINL_VOL */ 1548*4882a593Smuzhiyun #define WM8994_IN2L_MIXINL_VOL_WIDTH 1 /* IN2L_MIXINL_VOL */ 1549*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXINL 0x0020 /* IN1L_TO_MIXINL */ 1550*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXINL_MASK 0x0020 /* IN1L_TO_MIXINL */ 1551*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXINL_SHIFT 5 /* IN1L_TO_MIXINL */ 1552*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXINL_WIDTH 1 /* IN1L_TO_MIXINL */ 1553*4882a593Smuzhiyun #define WM8994_IN1L_MIXINL_VOL 0x0010 /* IN1L_MIXINL_VOL */ 1554*4882a593Smuzhiyun #define WM8994_IN1L_MIXINL_VOL_MASK 0x0010 /* IN1L_MIXINL_VOL */ 1555*4882a593Smuzhiyun #define WM8994_IN1L_MIXINL_VOL_SHIFT 4 /* IN1L_MIXINL_VOL */ 1556*4882a593Smuzhiyun #define WM8994_IN1L_MIXINL_VOL_WIDTH 1 /* IN1L_MIXINL_VOL */ 1557*4882a593Smuzhiyun #define WM8994_MIXOUTL_MIXINL_VOL_MASK 0x0007 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1558*4882a593Smuzhiyun #define WM8994_MIXOUTL_MIXINL_VOL_SHIFT 0 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1559*4882a593Smuzhiyun #define WM8994_MIXOUTL_MIXINL_VOL_WIDTH 3 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1560*4882a593Smuzhiyun 1561*4882a593Smuzhiyun /* 1562*4882a593Smuzhiyun * R42 (0x2A) - Input Mixer (4) 1563*4882a593Smuzhiyun */ 1564*4882a593Smuzhiyun #define WM8994_IN2R_TO_MIXINR 0x0100 /* IN2R_TO_MIXINR */ 1565*4882a593Smuzhiyun #define WM8994_IN2R_TO_MIXINR_MASK 0x0100 /* IN2R_TO_MIXINR */ 1566*4882a593Smuzhiyun #define WM8994_IN2R_TO_MIXINR_SHIFT 8 /* IN2R_TO_MIXINR */ 1567*4882a593Smuzhiyun #define WM8994_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */ 1568*4882a593Smuzhiyun #define WM8994_IN2R_MIXINR_VOL 0x0080 /* IN2R_MIXINR_VOL */ 1569*4882a593Smuzhiyun #define WM8994_IN2R_MIXINR_VOL_MASK 0x0080 /* IN2R_MIXINR_VOL */ 1570*4882a593Smuzhiyun #define WM8994_IN2R_MIXINR_VOL_SHIFT 7 /* IN2R_MIXINR_VOL */ 1571*4882a593Smuzhiyun #define WM8994_IN2R_MIXINR_VOL_WIDTH 1 /* IN2R_MIXINR_VOL */ 1572*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXINR 0x0020 /* IN1R_TO_MIXINR */ 1573*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXINR_MASK 0x0020 /* IN1R_TO_MIXINR */ 1574*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXINR_SHIFT 5 /* IN1R_TO_MIXINR */ 1575*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXINR_WIDTH 1 /* IN1R_TO_MIXINR */ 1576*4882a593Smuzhiyun #define WM8994_IN1R_MIXINR_VOL 0x0010 /* IN1R_MIXINR_VOL */ 1577*4882a593Smuzhiyun #define WM8994_IN1R_MIXINR_VOL_MASK 0x0010 /* IN1R_MIXINR_VOL */ 1578*4882a593Smuzhiyun #define WM8994_IN1R_MIXINR_VOL_SHIFT 4 /* IN1R_MIXINR_VOL */ 1579*4882a593Smuzhiyun #define WM8994_IN1R_MIXINR_VOL_WIDTH 1 /* IN1R_MIXINR_VOL */ 1580*4882a593Smuzhiyun #define WM8994_MIXOUTR_MIXINR_VOL_MASK 0x0007 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1581*4882a593Smuzhiyun #define WM8994_MIXOUTR_MIXINR_VOL_SHIFT 0 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1582*4882a593Smuzhiyun #define WM8994_MIXOUTR_MIXINR_VOL_WIDTH 3 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1583*4882a593Smuzhiyun 1584*4882a593Smuzhiyun /* 1585*4882a593Smuzhiyun * R43 (0x2B) - Input Mixer (5) 1586*4882a593Smuzhiyun */ 1587*4882a593Smuzhiyun #define WM8994_IN1LP_MIXINL_VOL_MASK 0x01C0 /* IN1LP_MIXINL_VOL - [8:6] */ 1588*4882a593Smuzhiyun #define WM8994_IN1LP_MIXINL_VOL_SHIFT 6 /* IN1LP_MIXINL_VOL - [8:6] */ 1589*4882a593Smuzhiyun #define WM8994_IN1LP_MIXINL_VOL_WIDTH 3 /* IN1LP_MIXINL_VOL - [8:6] */ 1590*4882a593Smuzhiyun #define WM8994_IN2LRP_MIXINL_VOL_MASK 0x0007 /* IN2LRP_MIXINL_VOL - [2:0] */ 1591*4882a593Smuzhiyun #define WM8994_IN2LRP_MIXINL_VOL_SHIFT 0 /* IN2LRP_MIXINL_VOL - [2:0] */ 1592*4882a593Smuzhiyun #define WM8994_IN2LRP_MIXINL_VOL_WIDTH 3 /* IN2LRP_MIXINL_VOL - [2:0] */ 1593*4882a593Smuzhiyun 1594*4882a593Smuzhiyun /* 1595*4882a593Smuzhiyun * R44 (0x2C) - Input Mixer (6) 1596*4882a593Smuzhiyun */ 1597*4882a593Smuzhiyun #define WM8994_IN1RP_MIXINR_VOL_MASK 0x01C0 /* IN1RP_MIXINR_VOL - [8:6] */ 1598*4882a593Smuzhiyun #define WM8994_IN1RP_MIXINR_VOL_SHIFT 6 /* IN1RP_MIXINR_VOL - [8:6] */ 1599*4882a593Smuzhiyun #define WM8994_IN1RP_MIXINR_VOL_WIDTH 3 /* IN1RP_MIXINR_VOL - [8:6] */ 1600*4882a593Smuzhiyun #define WM8994_IN2LRP_MIXINR_VOL_MASK 0x0007 /* IN2LRP_MIXINR_VOL - [2:0] */ 1601*4882a593Smuzhiyun #define WM8994_IN2LRP_MIXINR_VOL_SHIFT 0 /* IN2LRP_MIXINR_VOL - [2:0] */ 1602*4882a593Smuzhiyun #define WM8994_IN2LRP_MIXINR_VOL_WIDTH 3 /* IN2LRP_MIXINR_VOL - [2:0] */ 1603*4882a593Smuzhiyun 1604*4882a593Smuzhiyun /* 1605*4882a593Smuzhiyun * R45 (0x2D) - Output Mixer (1) 1606*4882a593Smuzhiyun */ 1607*4882a593Smuzhiyun #define WM8994_DAC1L_TO_HPOUT1L 0x0100 /* DAC1L_TO_HPOUT1L */ 1608*4882a593Smuzhiyun #define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 /* DAC1L_TO_HPOUT1L */ 1609*4882a593Smuzhiyun #define WM8994_DAC1L_TO_HPOUT1L_SHIFT 8 /* DAC1L_TO_HPOUT1L */ 1610*4882a593Smuzhiyun #define WM8994_DAC1L_TO_HPOUT1L_WIDTH 1 /* DAC1L_TO_HPOUT1L */ 1611*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTL 0x0080 /* MIXINR_TO_MIXOUTL */ 1612*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTL_MASK 0x0080 /* MIXINR_TO_MIXOUTL */ 1613*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTL_SHIFT 7 /* MIXINR_TO_MIXOUTL */ 1614*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTL_WIDTH 1 /* MIXINR_TO_MIXOUTL */ 1615*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTL 0x0040 /* MIXINL_TO_MIXOUTL */ 1616*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTL_MASK 0x0040 /* MIXINL_TO_MIXOUTL */ 1617*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTL_SHIFT 6 /* MIXINL_TO_MIXOUTL */ 1618*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTL_WIDTH 1 /* MIXINL_TO_MIXOUTL */ 1619*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTL 0x0020 /* IN2RN_TO_MIXOUTL */ 1620*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTL_MASK 0x0020 /* IN2RN_TO_MIXOUTL */ 1621*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTL_SHIFT 5 /* IN2RN_TO_MIXOUTL */ 1622*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTL_WIDTH 1 /* IN2RN_TO_MIXOUTL */ 1623*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTL 0x0010 /* IN2LN_TO_MIXOUTL */ 1624*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTL_MASK 0x0010 /* IN2LN_TO_MIXOUTL */ 1625*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTL_SHIFT 4 /* IN2LN_TO_MIXOUTL */ 1626*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTL_WIDTH 1 /* IN2LN_TO_MIXOUTL */ 1627*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTL 0x0008 /* IN1R_TO_MIXOUTL */ 1628*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTL_MASK 0x0008 /* IN1R_TO_MIXOUTL */ 1629*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTL_SHIFT 3 /* IN1R_TO_MIXOUTL */ 1630*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTL_WIDTH 1 /* IN1R_TO_MIXOUTL */ 1631*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTL 0x0004 /* IN1L_TO_MIXOUTL */ 1632*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTL_MASK 0x0004 /* IN1L_TO_MIXOUTL */ 1633*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTL_SHIFT 2 /* IN1L_TO_MIXOUTL */ 1634*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTL_WIDTH 1 /* IN1L_TO_MIXOUTL */ 1635*4882a593Smuzhiyun #define WM8994_IN2LP_TO_MIXOUTL 0x0002 /* IN2LP_TO_MIXOUTL */ 1636*4882a593Smuzhiyun #define WM8994_IN2LP_TO_MIXOUTL_MASK 0x0002 /* IN2LP_TO_MIXOUTL */ 1637*4882a593Smuzhiyun #define WM8994_IN2LP_TO_MIXOUTL_SHIFT 1 /* IN2LP_TO_MIXOUTL */ 1638*4882a593Smuzhiyun #define WM8994_IN2LP_TO_MIXOUTL_WIDTH 1 /* IN2LP_TO_MIXOUTL */ 1639*4882a593Smuzhiyun #define WM8994_DAC1L_TO_MIXOUTL 0x0001 /* DAC1L_TO_MIXOUTL */ 1640*4882a593Smuzhiyun #define WM8994_DAC1L_TO_MIXOUTL_MASK 0x0001 /* DAC1L_TO_MIXOUTL */ 1641*4882a593Smuzhiyun #define WM8994_DAC1L_TO_MIXOUTL_SHIFT 0 /* DAC1L_TO_MIXOUTL */ 1642*4882a593Smuzhiyun #define WM8994_DAC1L_TO_MIXOUTL_WIDTH 1 /* DAC1L_TO_MIXOUTL */ 1643*4882a593Smuzhiyun 1644*4882a593Smuzhiyun /* 1645*4882a593Smuzhiyun * R46 (0x2E) - Output Mixer (2) 1646*4882a593Smuzhiyun */ 1647*4882a593Smuzhiyun #define WM8994_DAC1R_TO_HPOUT1R 0x0100 /* DAC1R_TO_HPOUT1R */ 1648*4882a593Smuzhiyun #define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 /* DAC1R_TO_HPOUT1R */ 1649*4882a593Smuzhiyun #define WM8994_DAC1R_TO_HPOUT1R_SHIFT 8 /* DAC1R_TO_HPOUT1R */ 1650*4882a593Smuzhiyun #define WM8994_DAC1R_TO_HPOUT1R_WIDTH 1 /* DAC1R_TO_HPOUT1R */ 1651*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTR 0x0080 /* MIXINL_TO_MIXOUTR */ 1652*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTR_MASK 0x0080 /* MIXINL_TO_MIXOUTR */ 1653*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTR_SHIFT 7 /* MIXINL_TO_MIXOUTR */ 1654*4882a593Smuzhiyun #define WM8994_MIXINL_TO_MIXOUTR_WIDTH 1 /* MIXINL_TO_MIXOUTR */ 1655*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTR 0x0040 /* MIXINR_TO_MIXOUTR */ 1656*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTR_MASK 0x0040 /* MIXINR_TO_MIXOUTR */ 1657*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTR_SHIFT 6 /* MIXINR_TO_MIXOUTR */ 1658*4882a593Smuzhiyun #define WM8994_MIXINR_TO_MIXOUTR_WIDTH 1 /* MIXINR_TO_MIXOUTR */ 1659*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTR 0x0020 /* IN2LN_TO_MIXOUTR */ 1660*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTR_MASK 0x0020 /* IN2LN_TO_MIXOUTR */ 1661*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTR_SHIFT 5 /* IN2LN_TO_MIXOUTR */ 1662*4882a593Smuzhiyun #define WM8994_IN2LN_TO_MIXOUTR_WIDTH 1 /* IN2LN_TO_MIXOUTR */ 1663*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTR 0x0010 /* IN2RN_TO_MIXOUTR */ 1664*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTR_MASK 0x0010 /* IN2RN_TO_MIXOUTR */ 1665*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTR_SHIFT 4 /* IN2RN_TO_MIXOUTR */ 1666*4882a593Smuzhiyun #define WM8994_IN2RN_TO_MIXOUTR_WIDTH 1 /* IN2RN_TO_MIXOUTR */ 1667*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTR 0x0008 /* IN1L_TO_MIXOUTR */ 1668*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTR_MASK 0x0008 /* IN1L_TO_MIXOUTR */ 1669*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTR_SHIFT 3 /* IN1L_TO_MIXOUTR */ 1670*4882a593Smuzhiyun #define WM8994_IN1L_TO_MIXOUTR_WIDTH 1 /* IN1L_TO_MIXOUTR */ 1671*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTR 0x0004 /* IN1R_TO_MIXOUTR */ 1672*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTR_MASK 0x0004 /* IN1R_TO_MIXOUTR */ 1673*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTR_SHIFT 2 /* IN1R_TO_MIXOUTR */ 1674*4882a593Smuzhiyun #define WM8994_IN1R_TO_MIXOUTR_WIDTH 1 /* IN1R_TO_MIXOUTR */ 1675*4882a593Smuzhiyun #define WM8994_IN2RP_TO_MIXOUTR 0x0002 /* IN2RP_TO_MIXOUTR */ 1676*4882a593Smuzhiyun #define WM8994_IN2RP_TO_MIXOUTR_MASK 0x0002 /* IN2RP_TO_MIXOUTR */ 1677*4882a593Smuzhiyun #define WM8994_IN2RP_TO_MIXOUTR_SHIFT 1 /* IN2RP_TO_MIXOUTR */ 1678*4882a593Smuzhiyun #define WM8994_IN2RP_TO_MIXOUTR_WIDTH 1 /* IN2RP_TO_MIXOUTR */ 1679*4882a593Smuzhiyun #define WM8994_DAC1R_TO_MIXOUTR 0x0001 /* DAC1R_TO_MIXOUTR */ 1680*4882a593Smuzhiyun #define WM8994_DAC1R_TO_MIXOUTR_MASK 0x0001 /* DAC1R_TO_MIXOUTR */ 1681*4882a593Smuzhiyun #define WM8994_DAC1R_TO_MIXOUTR_SHIFT 0 /* DAC1R_TO_MIXOUTR */ 1682*4882a593Smuzhiyun #define WM8994_DAC1R_TO_MIXOUTR_WIDTH 1 /* DAC1R_TO_MIXOUTR */ 1683*4882a593Smuzhiyun 1684*4882a593Smuzhiyun /* 1685*4882a593Smuzhiyun * R47 (0x2F) - Output Mixer (3) 1686*4882a593Smuzhiyun */ 1687*4882a593Smuzhiyun #define WM8994_IN2LP_MIXOUTL_VOL_MASK 0x0E00 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1688*4882a593Smuzhiyun #define WM8994_IN2LP_MIXOUTL_VOL_SHIFT 9 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1689*4882a593Smuzhiyun #define WM8994_IN2LP_MIXOUTL_VOL_WIDTH 3 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1690*4882a593Smuzhiyun #define WM8994_IN2LN_MIXOUTL_VOL_MASK 0x01C0 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1691*4882a593Smuzhiyun #define WM8994_IN2LN_MIXOUTL_VOL_SHIFT 6 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1692*4882a593Smuzhiyun #define WM8994_IN2LN_MIXOUTL_VOL_WIDTH 3 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1693*4882a593Smuzhiyun #define WM8994_IN1R_MIXOUTL_VOL_MASK 0x0038 /* IN1R_MIXOUTL_VOL - [5:3] */ 1694*4882a593Smuzhiyun #define WM8994_IN1R_MIXOUTL_VOL_SHIFT 3 /* IN1R_MIXOUTL_VOL - [5:3] */ 1695*4882a593Smuzhiyun #define WM8994_IN1R_MIXOUTL_VOL_WIDTH 3 /* IN1R_MIXOUTL_VOL - [5:3] */ 1696*4882a593Smuzhiyun #define WM8994_IN1L_MIXOUTL_VOL_MASK 0x0007 /* IN1L_MIXOUTL_VOL - [2:0] */ 1697*4882a593Smuzhiyun #define WM8994_IN1L_MIXOUTL_VOL_SHIFT 0 /* IN1L_MIXOUTL_VOL - [2:0] */ 1698*4882a593Smuzhiyun #define WM8994_IN1L_MIXOUTL_VOL_WIDTH 3 /* IN1L_MIXOUTL_VOL - [2:0] */ 1699*4882a593Smuzhiyun 1700*4882a593Smuzhiyun /* 1701*4882a593Smuzhiyun * R48 (0x30) - Output Mixer (4) 1702*4882a593Smuzhiyun */ 1703*4882a593Smuzhiyun #define WM8994_IN2RP_MIXOUTR_VOL_MASK 0x0E00 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1704*4882a593Smuzhiyun #define WM8994_IN2RP_MIXOUTR_VOL_SHIFT 9 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1705*4882a593Smuzhiyun #define WM8994_IN2RP_MIXOUTR_VOL_WIDTH 3 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1706*4882a593Smuzhiyun #define WM8994_IN2RN_MIXOUTR_VOL_MASK 0x01C0 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1707*4882a593Smuzhiyun #define WM8994_IN2RN_MIXOUTR_VOL_SHIFT 6 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1708*4882a593Smuzhiyun #define WM8994_IN2RN_MIXOUTR_VOL_WIDTH 3 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1709*4882a593Smuzhiyun #define WM8994_IN1L_MIXOUTR_VOL_MASK 0x0038 /* IN1L_MIXOUTR_VOL - [5:3] */ 1710*4882a593Smuzhiyun #define WM8994_IN1L_MIXOUTR_VOL_SHIFT 3 /* IN1L_MIXOUTR_VOL - [5:3] */ 1711*4882a593Smuzhiyun #define WM8994_IN1L_MIXOUTR_VOL_WIDTH 3 /* IN1L_MIXOUTR_VOL - [5:3] */ 1712*4882a593Smuzhiyun #define WM8994_IN1R_MIXOUTR_VOL_MASK 0x0007 /* IN1R_MIXOUTR_VOL - [2:0] */ 1713*4882a593Smuzhiyun #define WM8994_IN1R_MIXOUTR_VOL_SHIFT 0 /* IN1R_MIXOUTR_VOL - [2:0] */ 1714*4882a593Smuzhiyun #define WM8994_IN1R_MIXOUTR_VOL_WIDTH 3 /* IN1R_MIXOUTR_VOL - [2:0] */ 1715*4882a593Smuzhiyun 1716*4882a593Smuzhiyun /* 1717*4882a593Smuzhiyun * R49 (0x31) - Output Mixer (5) 1718*4882a593Smuzhiyun */ 1719*4882a593Smuzhiyun #define WM8994_DAC1L_MIXOUTL_VOL_MASK 0x0E00 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1720*4882a593Smuzhiyun #define WM8994_DAC1L_MIXOUTL_VOL_SHIFT 9 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1721*4882a593Smuzhiyun #define WM8994_DAC1L_MIXOUTL_VOL_WIDTH 3 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1722*4882a593Smuzhiyun #define WM8994_IN2RN_MIXOUTL_VOL_MASK 0x01C0 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1723*4882a593Smuzhiyun #define WM8994_IN2RN_MIXOUTL_VOL_SHIFT 6 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1724*4882a593Smuzhiyun #define WM8994_IN2RN_MIXOUTL_VOL_WIDTH 3 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1725*4882a593Smuzhiyun #define WM8994_MIXINR_MIXOUTL_VOL_MASK 0x0038 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1726*4882a593Smuzhiyun #define WM8994_MIXINR_MIXOUTL_VOL_SHIFT 3 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1727*4882a593Smuzhiyun #define WM8994_MIXINR_MIXOUTL_VOL_WIDTH 3 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1728*4882a593Smuzhiyun #define WM8994_MIXINL_MIXOUTL_VOL_MASK 0x0007 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1729*4882a593Smuzhiyun #define WM8994_MIXINL_MIXOUTL_VOL_SHIFT 0 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1730*4882a593Smuzhiyun #define WM8994_MIXINL_MIXOUTL_VOL_WIDTH 3 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1731*4882a593Smuzhiyun 1732*4882a593Smuzhiyun /* 1733*4882a593Smuzhiyun * R50 (0x32) - Output Mixer (6) 1734*4882a593Smuzhiyun */ 1735*4882a593Smuzhiyun #define WM8994_DAC1R_MIXOUTR_VOL_MASK 0x0E00 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1736*4882a593Smuzhiyun #define WM8994_DAC1R_MIXOUTR_VOL_SHIFT 9 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1737*4882a593Smuzhiyun #define WM8994_DAC1R_MIXOUTR_VOL_WIDTH 3 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1738*4882a593Smuzhiyun #define WM8994_IN2LN_MIXOUTR_VOL_MASK 0x01C0 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1739*4882a593Smuzhiyun #define WM8994_IN2LN_MIXOUTR_VOL_SHIFT 6 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1740*4882a593Smuzhiyun #define WM8994_IN2LN_MIXOUTR_VOL_WIDTH 3 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1741*4882a593Smuzhiyun #define WM8994_MIXINL_MIXOUTR_VOL_MASK 0x0038 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1742*4882a593Smuzhiyun #define WM8994_MIXINL_MIXOUTR_VOL_SHIFT 3 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1743*4882a593Smuzhiyun #define WM8994_MIXINL_MIXOUTR_VOL_WIDTH 3 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1744*4882a593Smuzhiyun #define WM8994_MIXINR_MIXOUTR_VOL_MASK 0x0007 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1745*4882a593Smuzhiyun #define WM8994_MIXINR_MIXOUTR_VOL_SHIFT 0 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1746*4882a593Smuzhiyun #define WM8994_MIXINR_MIXOUTR_VOL_WIDTH 3 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1747*4882a593Smuzhiyun 1748*4882a593Smuzhiyun /* 1749*4882a593Smuzhiyun * R51 (0x33) - HPOUT2 Mixer 1750*4882a593Smuzhiyun */ 1751*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_HPOUT2 0x0020 /* IN2LRP_TO_HPOUT2 */ 1752*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_HPOUT2_MASK 0x0020 /* IN2LRP_TO_HPOUT2 */ 1753*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_HPOUT2_SHIFT 5 /* IN2LRP_TO_HPOUT2 */ 1754*4882a593Smuzhiyun #define WM8994_IN2LRP_TO_HPOUT2_WIDTH 1 /* IN2LRP_TO_HPOUT2 */ 1755*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_TO_HPOUT2 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */ 1756*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */ 1757*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT 4 /* MIXOUTLVOL_TO_HPOUT2 */ 1758*4882a593Smuzhiyun #define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTLVOL_TO_HPOUT2 */ 1759*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_TO_HPOUT2 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */ 1760*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */ 1761*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT 3 /* MIXOUTRVOL_TO_HPOUT2 */ 1762*4882a593Smuzhiyun #define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTRVOL_TO_HPOUT2 */ 1763*4882a593Smuzhiyun 1764*4882a593Smuzhiyun /* 1765*4882a593Smuzhiyun * R52 (0x34) - Line Mixer (1) 1766*4882a593Smuzhiyun */ 1767*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1N 0x0040 /* MIXOUTL_TO_LINEOUT1N */ 1768*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1N_MASK 0x0040 /* MIXOUTL_TO_LINEOUT1N */ 1769*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT 6 /* MIXOUTL_TO_LINEOUT1N */ 1770*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH 1 /* MIXOUTL_TO_LINEOUT1N */ 1771*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT1N 0x0020 /* MIXOUTR_TO_LINEOUT1N */ 1772*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT1N_MASK 0x0020 /* MIXOUTR_TO_LINEOUT1N */ 1773*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT 5 /* MIXOUTR_TO_LINEOUT1N */ 1774*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH 1 /* MIXOUTR_TO_LINEOUT1N */ 1775*4882a593Smuzhiyun #define WM8994_LINEOUT1_MODE 0x0010 /* LINEOUT1_MODE */ 1776*4882a593Smuzhiyun #define WM8994_LINEOUT1_MODE_MASK 0x0010 /* LINEOUT1_MODE */ 1777*4882a593Smuzhiyun #define WM8994_LINEOUT1_MODE_SHIFT 4 /* LINEOUT1_MODE */ 1778*4882a593Smuzhiyun #define WM8994_LINEOUT1_MODE_WIDTH 1 /* LINEOUT1_MODE */ 1779*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT1P 0x0004 /* IN1R_TO_LINEOUT1P */ 1780*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT1P_MASK 0x0004 /* IN1R_TO_LINEOUT1P */ 1781*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT1P_SHIFT 2 /* IN1R_TO_LINEOUT1P */ 1782*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT1P_WIDTH 1 /* IN1R_TO_LINEOUT1P */ 1783*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT1P 0x0002 /* IN1L_TO_LINEOUT1P */ 1784*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT1P_MASK 0x0002 /* IN1L_TO_LINEOUT1P */ 1785*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT1P_SHIFT 1 /* IN1L_TO_LINEOUT1P */ 1786*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT1P_WIDTH 1 /* IN1L_TO_LINEOUT1P */ 1787*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */ 1788*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */ 1789*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT 0 /* MIXOUTL_TO_LINEOUT1P */ 1790*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH 1 /* MIXOUTL_TO_LINEOUT1P */ 1791*4882a593Smuzhiyun 1792*4882a593Smuzhiyun /* 1793*4882a593Smuzhiyun * R53 (0x35) - Line Mixer (2) 1794*4882a593Smuzhiyun */ 1795*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2N 0x0040 /* MIXOUTR_TO_LINEOUT2N */ 1796*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2N_MASK 0x0040 /* MIXOUTR_TO_LINEOUT2N */ 1797*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT 6 /* MIXOUTR_TO_LINEOUT2N */ 1798*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH 1 /* MIXOUTR_TO_LINEOUT2N */ 1799*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT2N 0x0020 /* MIXOUTL_TO_LINEOUT2N */ 1800*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT2N_MASK 0x0020 /* MIXOUTL_TO_LINEOUT2N */ 1801*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT 5 /* MIXOUTL_TO_LINEOUT2N */ 1802*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH 1 /* MIXOUTL_TO_LINEOUT2N */ 1803*4882a593Smuzhiyun #define WM8994_LINEOUT2_MODE 0x0010 /* LINEOUT2_MODE */ 1804*4882a593Smuzhiyun #define WM8994_LINEOUT2_MODE_MASK 0x0010 /* LINEOUT2_MODE */ 1805*4882a593Smuzhiyun #define WM8994_LINEOUT2_MODE_SHIFT 4 /* LINEOUT2_MODE */ 1806*4882a593Smuzhiyun #define WM8994_LINEOUT2_MODE_WIDTH 1 /* LINEOUT2_MODE */ 1807*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT2P 0x0004 /* IN1L_TO_LINEOUT2P */ 1808*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT2P_MASK 0x0004 /* IN1L_TO_LINEOUT2P */ 1809*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT2P_SHIFT 2 /* IN1L_TO_LINEOUT2P */ 1810*4882a593Smuzhiyun #define WM8994_IN1L_TO_LINEOUT2P_WIDTH 1 /* IN1L_TO_LINEOUT2P */ 1811*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT2P 0x0002 /* IN1R_TO_LINEOUT2P */ 1812*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT2P_MASK 0x0002 /* IN1R_TO_LINEOUT2P */ 1813*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT2P_SHIFT 1 /* IN1R_TO_LINEOUT2P */ 1814*4882a593Smuzhiyun #define WM8994_IN1R_TO_LINEOUT2P_WIDTH 1 /* IN1R_TO_LINEOUT2P */ 1815*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */ 1816*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */ 1817*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT 0 /* MIXOUTR_TO_LINEOUT2P */ 1818*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH 1 /* MIXOUTR_TO_LINEOUT2P */ 1819*4882a593Smuzhiyun 1820*4882a593Smuzhiyun /* 1821*4882a593Smuzhiyun * R54 (0x36) - Speaker Mixer 1822*4882a593Smuzhiyun */ 1823*4882a593Smuzhiyun #define WM8994_DAC2L_TO_SPKMIXL 0x0200 /* DAC2L_TO_SPKMIXL */ 1824*4882a593Smuzhiyun #define WM8994_DAC2L_TO_SPKMIXL_MASK 0x0200 /* DAC2L_TO_SPKMIXL */ 1825*4882a593Smuzhiyun #define WM8994_DAC2L_TO_SPKMIXL_SHIFT 9 /* DAC2L_TO_SPKMIXL */ 1826*4882a593Smuzhiyun #define WM8994_DAC2L_TO_SPKMIXL_WIDTH 1 /* DAC2L_TO_SPKMIXL */ 1827*4882a593Smuzhiyun #define WM8994_DAC2R_TO_SPKMIXR 0x0100 /* DAC2R_TO_SPKMIXR */ 1828*4882a593Smuzhiyun #define WM8994_DAC2R_TO_SPKMIXR_MASK 0x0100 /* DAC2R_TO_SPKMIXR */ 1829*4882a593Smuzhiyun #define WM8994_DAC2R_TO_SPKMIXR_SHIFT 8 /* DAC2R_TO_SPKMIXR */ 1830*4882a593Smuzhiyun #define WM8994_DAC2R_TO_SPKMIXR_WIDTH 1 /* DAC2R_TO_SPKMIXR */ 1831*4882a593Smuzhiyun #define WM8994_MIXINL_TO_SPKMIXL 0x0080 /* MIXINL_TO_SPKMIXL */ 1832*4882a593Smuzhiyun #define WM8994_MIXINL_TO_SPKMIXL_MASK 0x0080 /* MIXINL_TO_SPKMIXL */ 1833*4882a593Smuzhiyun #define WM8994_MIXINL_TO_SPKMIXL_SHIFT 7 /* MIXINL_TO_SPKMIXL */ 1834*4882a593Smuzhiyun #define WM8994_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */ 1835*4882a593Smuzhiyun #define WM8994_MIXINR_TO_SPKMIXR 0x0040 /* MIXINR_TO_SPKMIXR */ 1836*4882a593Smuzhiyun #define WM8994_MIXINR_TO_SPKMIXR_MASK 0x0040 /* MIXINR_TO_SPKMIXR */ 1837*4882a593Smuzhiyun #define WM8994_MIXINR_TO_SPKMIXR_SHIFT 6 /* MIXINR_TO_SPKMIXR */ 1838*4882a593Smuzhiyun #define WM8994_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */ 1839*4882a593Smuzhiyun #define WM8994_IN1LP_TO_SPKMIXL 0x0020 /* IN1LP_TO_SPKMIXL */ 1840*4882a593Smuzhiyun #define WM8994_IN1LP_TO_SPKMIXL_MASK 0x0020 /* IN1LP_TO_SPKMIXL */ 1841*4882a593Smuzhiyun #define WM8994_IN1LP_TO_SPKMIXL_SHIFT 5 /* IN1LP_TO_SPKMIXL */ 1842*4882a593Smuzhiyun #define WM8994_IN1LP_TO_SPKMIXL_WIDTH 1 /* IN1LP_TO_SPKMIXL */ 1843*4882a593Smuzhiyun #define WM8994_IN1RP_TO_SPKMIXR 0x0010 /* IN1RP_TO_SPKMIXR */ 1844*4882a593Smuzhiyun #define WM8994_IN1RP_TO_SPKMIXR_MASK 0x0010 /* IN1RP_TO_SPKMIXR */ 1845*4882a593Smuzhiyun #define WM8994_IN1RP_TO_SPKMIXR_SHIFT 4 /* IN1RP_TO_SPKMIXR */ 1846*4882a593Smuzhiyun #define WM8994_IN1RP_TO_SPKMIXR_WIDTH 1 /* IN1RP_TO_SPKMIXR */ 1847*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_SPKMIXL 0x0008 /* MIXOUTL_TO_SPKMIXL */ 1848*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_SPKMIXL_MASK 0x0008 /* MIXOUTL_TO_SPKMIXL */ 1849*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT 3 /* MIXOUTL_TO_SPKMIXL */ 1850*4882a593Smuzhiyun #define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH 1 /* MIXOUTL_TO_SPKMIXL */ 1851*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_SPKMIXR 0x0004 /* MIXOUTR_TO_SPKMIXR */ 1852*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_SPKMIXR_MASK 0x0004 /* MIXOUTR_TO_SPKMIXR */ 1853*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT 2 /* MIXOUTR_TO_SPKMIXR */ 1854*4882a593Smuzhiyun #define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH 1 /* MIXOUTR_TO_SPKMIXR */ 1855*4882a593Smuzhiyun #define WM8994_DAC1L_TO_SPKMIXL 0x0002 /* DAC1L_TO_SPKMIXL */ 1856*4882a593Smuzhiyun #define WM8994_DAC1L_TO_SPKMIXL_MASK 0x0002 /* DAC1L_TO_SPKMIXL */ 1857*4882a593Smuzhiyun #define WM8994_DAC1L_TO_SPKMIXL_SHIFT 1 /* DAC1L_TO_SPKMIXL */ 1858*4882a593Smuzhiyun #define WM8994_DAC1L_TO_SPKMIXL_WIDTH 1 /* DAC1L_TO_SPKMIXL */ 1859*4882a593Smuzhiyun #define WM8994_DAC1R_TO_SPKMIXR 0x0001 /* DAC1R_TO_SPKMIXR */ 1860*4882a593Smuzhiyun #define WM8994_DAC1R_TO_SPKMIXR_MASK 0x0001 /* DAC1R_TO_SPKMIXR */ 1861*4882a593Smuzhiyun #define WM8994_DAC1R_TO_SPKMIXR_SHIFT 0 /* DAC1R_TO_SPKMIXR */ 1862*4882a593Smuzhiyun #define WM8994_DAC1R_TO_SPKMIXR_WIDTH 1 /* DAC1R_TO_SPKMIXR */ 1863*4882a593Smuzhiyun 1864*4882a593Smuzhiyun /* 1865*4882a593Smuzhiyun * R55 (0x37) - Additional Control 1866*4882a593Smuzhiyun */ 1867*4882a593Smuzhiyun #define WM8994_LINEOUT1_FB 0x0080 /* LINEOUT1_FB */ 1868*4882a593Smuzhiyun #define WM8994_LINEOUT1_FB_MASK 0x0080 /* LINEOUT1_FB */ 1869*4882a593Smuzhiyun #define WM8994_LINEOUT1_FB_SHIFT 7 /* LINEOUT1_FB */ 1870*4882a593Smuzhiyun #define WM8994_LINEOUT1_FB_WIDTH 1 /* LINEOUT1_FB */ 1871*4882a593Smuzhiyun #define WM8994_LINEOUT2_FB 0x0040 /* LINEOUT2_FB */ 1872*4882a593Smuzhiyun #define WM8994_LINEOUT2_FB_MASK 0x0040 /* LINEOUT2_FB */ 1873*4882a593Smuzhiyun #define WM8994_LINEOUT2_FB_SHIFT 6 /* LINEOUT2_FB */ 1874*4882a593Smuzhiyun #define WM8994_LINEOUT2_FB_WIDTH 1 /* LINEOUT2_FB */ 1875*4882a593Smuzhiyun #define WM8994_VROI 0x0001 /* VROI */ 1876*4882a593Smuzhiyun #define WM8994_VROI_MASK 0x0001 /* VROI */ 1877*4882a593Smuzhiyun #define WM8994_VROI_SHIFT 0 /* VROI */ 1878*4882a593Smuzhiyun #define WM8994_VROI_WIDTH 1 /* VROI */ 1879*4882a593Smuzhiyun 1880*4882a593Smuzhiyun /* 1881*4882a593Smuzhiyun * R56 (0x38) - AntiPOP (1) 1882*4882a593Smuzhiyun */ 1883*4882a593Smuzhiyun #define WM8994_LINEOUT_VMID_BUF_ENA 0x0080 /* LINEOUT_VMID_BUF_ENA */ 1884*4882a593Smuzhiyun #define WM8994_LINEOUT_VMID_BUF_ENA_MASK 0x0080 /* LINEOUT_VMID_BUF_ENA */ 1885*4882a593Smuzhiyun #define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT 7 /* LINEOUT_VMID_BUF_ENA */ 1886*4882a593Smuzhiyun #define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH 1 /* LINEOUT_VMID_BUF_ENA */ 1887*4882a593Smuzhiyun #define WM8994_HPOUT2_IN_ENA 0x0040 /* HPOUT2_IN_ENA */ 1888*4882a593Smuzhiyun #define WM8994_HPOUT2_IN_ENA_MASK 0x0040 /* HPOUT2_IN_ENA */ 1889*4882a593Smuzhiyun #define WM8994_HPOUT2_IN_ENA_SHIFT 6 /* HPOUT2_IN_ENA */ 1890*4882a593Smuzhiyun #define WM8994_HPOUT2_IN_ENA_WIDTH 1 /* HPOUT2_IN_ENA */ 1891*4882a593Smuzhiyun #define WM8994_LINEOUT1_DISCH 0x0020 /* LINEOUT1_DISCH */ 1892*4882a593Smuzhiyun #define WM8994_LINEOUT1_DISCH_MASK 0x0020 /* LINEOUT1_DISCH */ 1893*4882a593Smuzhiyun #define WM8994_LINEOUT1_DISCH_SHIFT 5 /* LINEOUT1_DISCH */ 1894*4882a593Smuzhiyun #define WM8994_LINEOUT1_DISCH_WIDTH 1 /* LINEOUT1_DISCH */ 1895*4882a593Smuzhiyun #define WM8994_LINEOUT2_DISCH 0x0010 /* LINEOUT2_DISCH */ 1896*4882a593Smuzhiyun #define WM8994_LINEOUT2_DISCH_MASK 0x0010 /* LINEOUT2_DISCH */ 1897*4882a593Smuzhiyun #define WM8994_LINEOUT2_DISCH_SHIFT 4 /* LINEOUT2_DISCH */ 1898*4882a593Smuzhiyun #define WM8994_LINEOUT2_DISCH_WIDTH 1 /* LINEOUT2_DISCH */ 1899*4882a593Smuzhiyun 1900*4882a593Smuzhiyun /* 1901*4882a593Smuzhiyun * R57 (0x39) - AntiPOP (2) 1902*4882a593Smuzhiyun */ 1903*4882a593Smuzhiyun #define WM1811_JACKDET_MODE_MASK 0x0180 /* JACKDET_MODE - [8:7] */ 1904*4882a593Smuzhiyun #define WM1811_JACKDET_MODE_SHIFT 7 /* JACKDET_MODE - [8:7] */ 1905*4882a593Smuzhiyun #define WM1811_JACKDET_MODE_WIDTH 2 /* JACKDET_MODE - [8:7] */ 1906*4882a593Smuzhiyun #define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */ 1907*4882a593Smuzhiyun #define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */ 1908*4882a593Smuzhiyun #define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */ 1909*4882a593Smuzhiyun #define WM8994_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1910*4882a593Smuzhiyun #define WM8994_MICB1_DISCH 0x0080 /* MICB1_DISCH */ 1911*4882a593Smuzhiyun #define WM8994_MICB1_DISCH_MASK 0x0080 /* MICB1_DISCH */ 1912*4882a593Smuzhiyun #define WM8994_MICB1_DISCH_SHIFT 7 /* MICB1_DISCH */ 1913*4882a593Smuzhiyun #define WM8994_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1914*4882a593Smuzhiyun #define WM8994_VMID_RAMP_MASK 0x0060 /* VMID_RAMP - [6:5] */ 1915*4882a593Smuzhiyun #define WM8994_VMID_RAMP_SHIFT 5 /* VMID_RAMP - [6:5] */ 1916*4882a593Smuzhiyun #define WM8994_VMID_RAMP_WIDTH 2 /* VMID_RAMP - [6:5] */ 1917*4882a593Smuzhiyun #define WM8994_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */ 1918*4882a593Smuzhiyun #define WM8994_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */ 1919*4882a593Smuzhiyun #define WM8994_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */ 1920*4882a593Smuzhiyun #define WM8994_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 1921*4882a593Smuzhiyun #define WM8994_STARTUP_BIAS_ENA 0x0004 /* STARTUP_BIAS_ENA */ 1922*4882a593Smuzhiyun #define WM8994_STARTUP_BIAS_ENA_MASK 0x0004 /* STARTUP_BIAS_ENA */ 1923*4882a593Smuzhiyun #define WM8994_STARTUP_BIAS_ENA_SHIFT 2 /* STARTUP_BIAS_ENA */ 1924*4882a593Smuzhiyun #define WM8994_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 1925*4882a593Smuzhiyun #define WM8994_BIAS_SRC 0x0002 /* BIAS_SRC */ 1926*4882a593Smuzhiyun #define WM8994_BIAS_SRC_MASK 0x0002 /* BIAS_SRC */ 1927*4882a593Smuzhiyun #define WM8994_BIAS_SRC_SHIFT 1 /* BIAS_SRC */ 1928*4882a593Smuzhiyun #define WM8994_BIAS_SRC_WIDTH 1 /* BIAS_SRC */ 1929*4882a593Smuzhiyun #define WM8994_VMID_DISCH 0x0001 /* VMID_DISCH */ 1930*4882a593Smuzhiyun #define WM8994_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */ 1931*4882a593Smuzhiyun #define WM8994_VMID_DISCH_SHIFT 0 /* VMID_DISCH */ 1932*4882a593Smuzhiyun #define WM8994_VMID_DISCH_WIDTH 1 /* VMID_DISCH */ 1933*4882a593Smuzhiyun 1934*4882a593Smuzhiyun /* 1935*4882a593Smuzhiyun * R58 (0x3A) - MICBIAS 1936*4882a593Smuzhiyun */ 1937*4882a593Smuzhiyun #define WM8994_MICD_SCTHR_MASK 0x00C0 /* MICD_SCTHR - [7:6] */ 1938*4882a593Smuzhiyun #define WM8994_MICD_SCTHR_SHIFT 6 /* MICD_SCTHR - [7:6] */ 1939*4882a593Smuzhiyun #define WM8994_MICD_SCTHR_WIDTH 2 /* MICD_SCTHR - [7:6] */ 1940*4882a593Smuzhiyun #define WM8994_MICD_THR_MASK 0x0038 /* MICD_THR - [5:3] */ 1941*4882a593Smuzhiyun #define WM8994_MICD_THR_SHIFT 3 /* MICD_THR - [5:3] */ 1942*4882a593Smuzhiyun #define WM8994_MICD_THR_WIDTH 3 /* MICD_THR - [5:3] */ 1943*4882a593Smuzhiyun #define WM8994_MICD_ENA 0x0004 /* MICD_ENA */ 1944*4882a593Smuzhiyun #define WM8994_MICD_ENA_MASK 0x0004 /* MICD_ENA */ 1945*4882a593Smuzhiyun #define WM8994_MICD_ENA_SHIFT 2 /* MICD_ENA */ 1946*4882a593Smuzhiyun #define WM8994_MICD_ENA_WIDTH 1 /* MICD_ENA */ 1947*4882a593Smuzhiyun #define WM8994_MICB2_LVL 0x0002 /* MICB2_LVL */ 1948*4882a593Smuzhiyun #define WM8994_MICB2_LVL_MASK 0x0002 /* MICB2_LVL */ 1949*4882a593Smuzhiyun #define WM8994_MICB2_LVL_SHIFT 1 /* MICB2_LVL */ 1950*4882a593Smuzhiyun #define WM8994_MICB2_LVL_WIDTH 1 /* MICB2_LVL */ 1951*4882a593Smuzhiyun #define WM8994_MICB1_LVL 0x0001 /* MICB1_LVL */ 1952*4882a593Smuzhiyun #define WM8994_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */ 1953*4882a593Smuzhiyun #define WM8994_MICB1_LVL_SHIFT 0 /* MICB1_LVL */ 1954*4882a593Smuzhiyun #define WM8994_MICB1_LVL_WIDTH 1 /* MICB1_LVL */ 1955*4882a593Smuzhiyun 1956*4882a593Smuzhiyun /* 1957*4882a593Smuzhiyun * R59 (0x3B) - LDO 1 1958*4882a593Smuzhiyun */ 1959*4882a593Smuzhiyun #define WM8994_LDO1_VSEL_MASK 0x000E /* LDO1_VSEL - [3:1] */ 1960*4882a593Smuzhiyun #define WM8994_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [3:1] */ 1961*4882a593Smuzhiyun #define WM8994_LDO1_VSEL_WIDTH 3 /* LDO1_VSEL - [3:1] */ 1962*4882a593Smuzhiyun #define WM8994_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 1963*4882a593Smuzhiyun #define WM8994_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 1964*4882a593Smuzhiyun #define WM8994_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 1965*4882a593Smuzhiyun #define WM8994_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 1966*4882a593Smuzhiyun 1967*4882a593Smuzhiyun /* 1968*4882a593Smuzhiyun * R60 (0x3C) - LDO 2 1969*4882a593Smuzhiyun */ 1970*4882a593Smuzhiyun #define WM8994_LDO2_VSEL_MASK 0x0006 /* LDO2_VSEL - [2:1] */ 1971*4882a593Smuzhiyun #define WM8994_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [2:1] */ 1972*4882a593Smuzhiyun #define WM8994_LDO2_VSEL_WIDTH 2 /* LDO2_VSEL - [2:1] */ 1973*4882a593Smuzhiyun #define WM8994_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 1974*4882a593Smuzhiyun #define WM8994_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 1975*4882a593Smuzhiyun #define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 1976*4882a593Smuzhiyun #define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 1977*4882a593Smuzhiyun 1978*4882a593Smuzhiyun /* 1979*4882a593Smuzhiyun * R61 (0x3D) - MICBIAS1 1980*4882a593Smuzhiyun */ 1981*4882a593Smuzhiyun #define WM8958_MICB1_RATE 0x0020 /* MICB1_RATE */ 1982*4882a593Smuzhiyun #define WM8958_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 1983*4882a593Smuzhiyun #define WM8958_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 1984*4882a593Smuzhiyun #define WM8958_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 1985*4882a593Smuzhiyun #define WM8958_MICB1_MODE 0x0010 /* MICB1_MODE */ 1986*4882a593Smuzhiyun #define WM8958_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */ 1987*4882a593Smuzhiyun #define WM8958_MICB1_MODE_SHIFT 4 /* MICB1_MODE */ 1988*4882a593Smuzhiyun #define WM8958_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 1989*4882a593Smuzhiyun #define WM8958_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */ 1990*4882a593Smuzhiyun #define WM8958_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */ 1991*4882a593Smuzhiyun #define WM8958_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */ 1992*4882a593Smuzhiyun #define WM8958_MICB1_DISCH 0x0001 /* MICB1_DISCH */ 1993*4882a593Smuzhiyun #define WM8958_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ 1994*4882a593Smuzhiyun #define WM8958_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ 1995*4882a593Smuzhiyun #define WM8958_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1996*4882a593Smuzhiyun 1997*4882a593Smuzhiyun /* 1998*4882a593Smuzhiyun * R62 (0x3E) - MICBIAS2 1999*4882a593Smuzhiyun */ 2000*4882a593Smuzhiyun #define WM8958_MICB2_RATE 0x0020 /* MICB2_RATE */ 2001*4882a593Smuzhiyun #define WM8958_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 2002*4882a593Smuzhiyun #define WM8958_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 2003*4882a593Smuzhiyun #define WM8958_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 2004*4882a593Smuzhiyun #define WM8958_MICB2_MODE 0x0010 /* MICB2_MODE */ 2005*4882a593Smuzhiyun #define WM8958_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */ 2006*4882a593Smuzhiyun #define WM8958_MICB2_MODE_SHIFT 4 /* MICB2_MODE */ 2007*4882a593Smuzhiyun #define WM8958_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 2008*4882a593Smuzhiyun #define WM8958_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */ 2009*4882a593Smuzhiyun #define WM8958_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */ 2010*4882a593Smuzhiyun #define WM8958_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */ 2011*4882a593Smuzhiyun #define WM8958_MICB2_DISCH 0x0001 /* MICB2_DISCH */ 2012*4882a593Smuzhiyun #define WM8958_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ 2013*4882a593Smuzhiyun #define WM8958_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ 2014*4882a593Smuzhiyun #define WM8958_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 2015*4882a593Smuzhiyun 2016*4882a593Smuzhiyun /* 2017*4882a593Smuzhiyun * R210 (0xD2) - Mic Detect 3 2018*4882a593Smuzhiyun */ 2019*4882a593Smuzhiyun #define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ 2020*4882a593Smuzhiyun #define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ 2021*4882a593Smuzhiyun #define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ 2022*4882a593Smuzhiyun #define WM8958_MICD_VALID 0x0002 /* MICD_VALID */ 2023*4882a593Smuzhiyun #define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 2024*4882a593Smuzhiyun #define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */ 2025*4882a593Smuzhiyun #define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */ 2026*4882a593Smuzhiyun #define WM8958_MICD_STS 0x0001 /* MICD_STS */ 2027*4882a593Smuzhiyun #define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */ 2028*4882a593Smuzhiyun #define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */ 2029*4882a593Smuzhiyun #define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */ 2030*4882a593Smuzhiyun 2031*4882a593Smuzhiyun /* 2032*4882a593Smuzhiyun * R76 (0x4C) - Charge Pump (1) 2033*4882a593Smuzhiyun */ 2034*4882a593Smuzhiyun #define WM8994_CP_ENA 0x8000 /* CP_ENA */ 2035*4882a593Smuzhiyun #define WM8994_CP_ENA_MASK 0x8000 /* CP_ENA */ 2036*4882a593Smuzhiyun #define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */ 2037*4882a593Smuzhiyun #define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */ 2038*4882a593Smuzhiyun 2039*4882a593Smuzhiyun /* 2040*4882a593Smuzhiyun * R77 (0x4D) - Charge Pump (2) 2041*4882a593Smuzhiyun */ 2042*4882a593Smuzhiyun #define WM8958_CP_DISCH 0x8000 /* CP_DISCH */ 2043*4882a593Smuzhiyun #define WM8958_CP_DISCH_MASK 0x8000 /* CP_DISCH */ 2044*4882a593Smuzhiyun #define WM8958_CP_DISCH_SHIFT 15 /* CP_DISCH */ 2045*4882a593Smuzhiyun #define WM8958_CP_DISCH_WIDTH 1 /* CP_DISCH */ 2046*4882a593Smuzhiyun 2047*4882a593Smuzhiyun /* 2048*4882a593Smuzhiyun * R81 (0x51) - Class W (1) 2049*4882a593Smuzhiyun */ 2050*4882a593Smuzhiyun #define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ 2051*4882a593Smuzhiyun #define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ 2052*4882a593Smuzhiyun #define WM8994_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ 2053*4882a593Smuzhiyun #define WM8994_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 2054*4882a593Smuzhiyun #define WM8994_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 2055*4882a593Smuzhiyun #define WM8994_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 2056*4882a593Smuzhiyun #define WM8994_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 2057*4882a593Smuzhiyun 2058*4882a593Smuzhiyun /* 2059*4882a593Smuzhiyun * R84 (0x54) - DC Servo (1) 2060*4882a593Smuzhiyun */ 2061*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 2062*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 2063*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 2064*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 2065*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 2066*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 2067*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 2068*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 2069*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 2070*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 2071*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 2072*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 2073*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 2074*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 2075*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 2076*4882a593Smuzhiyun #define WM8994_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 2077*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 2078*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 2079*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 2080*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 2081*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 2082*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 2083*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 2084*4882a593Smuzhiyun #define WM8994_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 2085*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */ 2086*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */ 2087*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */ 2088*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 2089*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */ 2090*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */ 2091*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */ 2092*4882a593Smuzhiyun #define WM8994_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 2093*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 2094*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 2095*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 2096*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 2097*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 2098*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 2099*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 2100*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 2101*4882a593Smuzhiyun 2102*4882a593Smuzhiyun /* 2103*4882a593Smuzhiyun * R85 (0x55) - DC Servo (2) 2104*4882a593Smuzhiyun */ 2105*4882a593Smuzhiyun #define WM8994_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */ 2106*4882a593Smuzhiyun #define WM8994_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */ 2107*4882a593Smuzhiyun #define WM8994_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */ 2108*4882a593Smuzhiyun #define WM8994_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 2109*4882a593Smuzhiyun #define WM8994_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 2110*4882a593Smuzhiyun #define WM8994_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 2111*4882a593Smuzhiyun 2112*4882a593Smuzhiyun /* 2113*4882a593Smuzhiyun * R87 (0x57) - DC Servo (4) 2114*4882a593Smuzhiyun */ 2115*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 2116*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 2117*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 2118*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 2119*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 2120*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 2121*4882a593Smuzhiyun 2122*4882a593Smuzhiyun /* 2123*4882a593Smuzhiyun * R88 (0x58) - DC Servo Readback 2124*4882a593Smuzhiyun */ 2125*4882a593Smuzhiyun #define WM8994_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */ 2126*4882a593Smuzhiyun #define WM8994_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */ 2127*4882a593Smuzhiyun #define WM8994_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */ 2128*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */ 2129*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */ 2130*4882a593Smuzhiyun #define WM8994_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */ 2131*4882a593Smuzhiyun #define WM8994_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */ 2132*4882a593Smuzhiyun #define WM8994_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */ 2133*4882a593Smuzhiyun #define WM8994_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */ 2134*4882a593Smuzhiyun 2135*4882a593Smuzhiyun /* 2136*4882a593Smuzhiyun * R96 (0x60) - Analogue HP (1) 2137*4882a593Smuzhiyun */ 2138*4882a593Smuzhiyun #define WM1811_HPOUT1_ATTN 0x0100 /* HPOUT1_ATTN */ 2139*4882a593Smuzhiyun #define WM1811_HPOUT1_ATTN_MASK 0x0100 /* HPOUT1_ATTN */ 2140*4882a593Smuzhiyun #define WM1811_HPOUT1_ATTN_SHIFT 8 /* HPOUT1_ATTN */ 2141*4882a593Smuzhiyun #define WM1811_HPOUT1_ATTN_WIDTH 1 /* HPOUT1_ATTN */ 2142*4882a593Smuzhiyun #define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 2143*4882a593Smuzhiyun #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 2144*4882a593Smuzhiyun #define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 2145*4882a593Smuzhiyun #define WM8994_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 2146*4882a593Smuzhiyun #define WM8994_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 2147*4882a593Smuzhiyun #define WM8994_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 2148*4882a593Smuzhiyun #define WM8994_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 2149*4882a593Smuzhiyun #define WM8994_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 2150*4882a593Smuzhiyun #define WM8994_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 2151*4882a593Smuzhiyun #define WM8994_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 2152*4882a593Smuzhiyun #define WM8994_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 2153*4882a593Smuzhiyun #define WM8994_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 2154*4882a593Smuzhiyun #define WM8994_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 2155*4882a593Smuzhiyun #define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 2156*4882a593Smuzhiyun #define WM8994_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 2157*4882a593Smuzhiyun #define WM8994_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 2158*4882a593Smuzhiyun #define WM8994_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 2159*4882a593Smuzhiyun #define WM8994_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 2160*4882a593Smuzhiyun #define WM8994_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 2161*4882a593Smuzhiyun #define WM8994_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 2162*4882a593Smuzhiyun #define WM8994_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 2163*4882a593Smuzhiyun #define WM8994_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 2164*4882a593Smuzhiyun #define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 2165*4882a593Smuzhiyun #define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 2166*4882a593Smuzhiyun 2167*4882a593Smuzhiyun /* 2168*4882a593Smuzhiyun * R208 (0xD0) - Mic Detect 1 2169*4882a593Smuzhiyun */ 2170*4882a593Smuzhiyun #define WM8958_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ 2171*4882a593Smuzhiyun #define WM8958_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ 2172*4882a593Smuzhiyun #define WM8958_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ 2173*4882a593Smuzhiyun #define WM8958_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ 2174*4882a593Smuzhiyun #define WM8958_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ 2175*4882a593Smuzhiyun #define WM8958_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ 2176*4882a593Smuzhiyun #define WM8958_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 2177*4882a593Smuzhiyun #define WM8958_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 2178*4882a593Smuzhiyun #define WM8958_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 2179*4882a593Smuzhiyun #define WM8958_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 2180*4882a593Smuzhiyun #define WM8958_MICD_ENA 0x0001 /* MICD_ENA */ 2181*4882a593Smuzhiyun #define WM8958_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 2182*4882a593Smuzhiyun #define WM8958_MICD_ENA_SHIFT 0 /* MICD_ENA */ 2183*4882a593Smuzhiyun #define WM8958_MICD_ENA_WIDTH 1 /* MICD_ENA */ 2184*4882a593Smuzhiyun 2185*4882a593Smuzhiyun /* 2186*4882a593Smuzhiyun * R209 (0xD1) - Mic Detect 2 2187*4882a593Smuzhiyun */ 2188*4882a593Smuzhiyun #define WM8958_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ 2189*4882a593Smuzhiyun #define WM8958_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ 2190*4882a593Smuzhiyun #define WM8958_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ 2191*4882a593Smuzhiyun 2192*4882a593Smuzhiyun /* 2193*4882a593Smuzhiyun * R210 (0xD2) - Mic Detect 3 2194*4882a593Smuzhiyun */ 2195*4882a593Smuzhiyun #define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ 2196*4882a593Smuzhiyun #define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ 2197*4882a593Smuzhiyun #define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ 2198*4882a593Smuzhiyun #define WM8958_MICD_VALID 0x0002 /* MICD_VALID */ 2199*4882a593Smuzhiyun #define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 2200*4882a593Smuzhiyun #define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */ 2201*4882a593Smuzhiyun #define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */ 2202*4882a593Smuzhiyun #define WM8958_MICD_STS 0x0001 /* MICD_STS */ 2203*4882a593Smuzhiyun #define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */ 2204*4882a593Smuzhiyun #define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */ 2205*4882a593Smuzhiyun #define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */ 2206*4882a593Smuzhiyun 2207*4882a593Smuzhiyun /* 2208*4882a593Smuzhiyun * R256 (0x100) - Chip Revision 2209*4882a593Smuzhiyun */ 2210*4882a593Smuzhiyun #define WM8994_CUST_ID_MASK 0xFF00 /* CUST_ID - [15:8] */ 2211*4882a593Smuzhiyun #define WM8994_CUST_ID_SHIFT 8 /* CUST_ID - [15:8] */ 2212*4882a593Smuzhiyun #define WM8994_CUST_ID_WIDTH 8 /* CUST_ID - [15:8] */ 2213*4882a593Smuzhiyun #define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 2214*4882a593Smuzhiyun #define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 2215*4882a593Smuzhiyun #define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 2216*4882a593Smuzhiyun 2217*4882a593Smuzhiyun /* 2218*4882a593Smuzhiyun * R257 (0x101) - Control Interface 2219*4882a593Smuzhiyun */ 2220*4882a593Smuzhiyun #define WM8994_SPI_CONTRD 0x0040 /* SPI_CONTRD */ 2221*4882a593Smuzhiyun #define WM8994_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ 2222*4882a593Smuzhiyun #define WM8994_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ 2223*4882a593Smuzhiyun #define WM8994_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ 2224*4882a593Smuzhiyun #define WM8994_SPI_4WIRE 0x0020 /* SPI_4WIRE */ 2225*4882a593Smuzhiyun #define WM8994_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ 2226*4882a593Smuzhiyun #define WM8994_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ 2227*4882a593Smuzhiyun #define WM8994_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 2228*4882a593Smuzhiyun #define WM8994_SPI_CFG 0x0010 /* SPI_CFG */ 2229*4882a593Smuzhiyun #define WM8994_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 2230*4882a593Smuzhiyun #define WM8994_SPI_CFG_SHIFT 4 /* SPI_CFG */ 2231*4882a593Smuzhiyun #define WM8994_SPI_CFG_WIDTH 1 /* SPI_CFG */ 2232*4882a593Smuzhiyun #define WM8994_AUTO_INC 0x0004 /* AUTO_INC */ 2233*4882a593Smuzhiyun #define WM8994_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 2234*4882a593Smuzhiyun #define WM8994_AUTO_INC_SHIFT 2 /* AUTO_INC */ 2235*4882a593Smuzhiyun #define WM8994_AUTO_INC_WIDTH 1 /* AUTO_INC */ 2236*4882a593Smuzhiyun 2237*4882a593Smuzhiyun /* 2238*4882a593Smuzhiyun * R272 (0x110) - Write Sequencer Ctrl (1) 2239*4882a593Smuzhiyun */ 2240*4882a593Smuzhiyun #define WM8994_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 2241*4882a593Smuzhiyun #define WM8994_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 2242*4882a593Smuzhiyun #define WM8994_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 2243*4882a593Smuzhiyun #define WM8994_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 2244*4882a593Smuzhiyun #define WM8994_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 2245*4882a593Smuzhiyun #define WM8994_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 2246*4882a593Smuzhiyun #define WM8994_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 2247*4882a593Smuzhiyun #define WM8994_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 2248*4882a593Smuzhiyun #define WM8994_WSEQ_START 0x0100 /* WSEQ_START */ 2249*4882a593Smuzhiyun #define WM8994_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 2250*4882a593Smuzhiyun #define WM8994_WSEQ_START_SHIFT 8 /* WSEQ_START */ 2251*4882a593Smuzhiyun #define WM8994_WSEQ_START_WIDTH 1 /* WSEQ_START */ 2252*4882a593Smuzhiyun #define WM8994_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 2253*4882a593Smuzhiyun #define WM8994_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 2254*4882a593Smuzhiyun #define WM8994_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 2255*4882a593Smuzhiyun 2256*4882a593Smuzhiyun /* 2257*4882a593Smuzhiyun * R273 (0x111) - Write Sequencer Ctrl (2) 2258*4882a593Smuzhiyun */ 2259*4882a593Smuzhiyun #define WM8994_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 2260*4882a593Smuzhiyun #define WM8994_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 2261*4882a593Smuzhiyun #define WM8994_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 2262*4882a593Smuzhiyun #define WM8994_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 2263*4882a593Smuzhiyun #define WM8994_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 2264*4882a593Smuzhiyun #define WM8994_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 2265*4882a593Smuzhiyun #define WM8994_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 2266*4882a593Smuzhiyun 2267*4882a593Smuzhiyun /* 2268*4882a593Smuzhiyun * R512 (0x200) - AIF1 Clocking (1) 2269*4882a593Smuzhiyun */ 2270*4882a593Smuzhiyun #define WM8994_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ 2271*4882a593Smuzhiyun #define WM8994_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ 2272*4882a593Smuzhiyun #define WM8994_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ 2273*4882a593Smuzhiyun #define WM8994_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ 2274*4882a593Smuzhiyun #define WM8994_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ 2275*4882a593Smuzhiyun #define WM8994_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ 2276*4882a593Smuzhiyun #define WM8994_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ 2277*4882a593Smuzhiyun #define WM8994_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ 2278*4882a593Smuzhiyun #define WM8994_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ 2279*4882a593Smuzhiyun #define WM8994_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ 2280*4882a593Smuzhiyun #define WM8994_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ 2281*4882a593Smuzhiyun #define WM8994_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ 2282*4882a593Smuzhiyun #define WM8994_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ 2283*4882a593Smuzhiyun #define WM8994_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ 2284*4882a593Smuzhiyun #define WM8994_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ 2285*4882a593Smuzhiyun 2286*4882a593Smuzhiyun /* 2287*4882a593Smuzhiyun * R513 (0x201) - AIF1 Clocking (2) 2288*4882a593Smuzhiyun */ 2289*4882a593Smuzhiyun #define WM8994_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ 2290*4882a593Smuzhiyun #define WM8994_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ 2291*4882a593Smuzhiyun #define WM8994_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ 2292*4882a593Smuzhiyun #define WM8994_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ 2293*4882a593Smuzhiyun #define WM8994_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ 2294*4882a593Smuzhiyun #define WM8994_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ 2295*4882a593Smuzhiyun 2296*4882a593Smuzhiyun /* 2297*4882a593Smuzhiyun * R516 (0x204) - AIF2 Clocking (1) 2298*4882a593Smuzhiyun */ 2299*4882a593Smuzhiyun #define WM8994_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ 2300*4882a593Smuzhiyun #define WM8994_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ 2301*4882a593Smuzhiyun #define WM8994_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ 2302*4882a593Smuzhiyun #define WM8994_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ 2303*4882a593Smuzhiyun #define WM8994_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ 2304*4882a593Smuzhiyun #define WM8994_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ 2305*4882a593Smuzhiyun #define WM8994_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ 2306*4882a593Smuzhiyun #define WM8994_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ 2307*4882a593Smuzhiyun #define WM8994_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ 2308*4882a593Smuzhiyun #define WM8994_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ 2309*4882a593Smuzhiyun #define WM8994_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ 2310*4882a593Smuzhiyun #define WM8994_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ 2311*4882a593Smuzhiyun #define WM8994_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ 2312*4882a593Smuzhiyun #define WM8994_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ 2313*4882a593Smuzhiyun #define WM8994_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ 2314*4882a593Smuzhiyun 2315*4882a593Smuzhiyun /* 2316*4882a593Smuzhiyun * R517 (0x205) - AIF2 Clocking (2) 2317*4882a593Smuzhiyun */ 2318*4882a593Smuzhiyun #define WM8994_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ 2319*4882a593Smuzhiyun #define WM8994_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ 2320*4882a593Smuzhiyun #define WM8994_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ 2321*4882a593Smuzhiyun #define WM8994_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ 2322*4882a593Smuzhiyun #define WM8994_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ 2323*4882a593Smuzhiyun #define WM8994_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ 2324*4882a593Smuzhiyun 2325*4882a593Smuzhiyun /* 2326*4882a593Smuzhiyun * R520 (0x208) - Clocking (1) 2327*4882a593Smuzhiyun */ 2328*4882a593Smuzhiyun #define WM8958_DSP2CLK_ENA 0x4000 /* DSP2CLK_ENA */ 2329*4882a593Smuzhiyun #define WM8958_DSP2CLK_ENA_MASK 0x4000 /* DSP2CLK_ENA */ 2330*4882a593Smuzhiyun #define WM8958_DSP2CLK_ENA_SHIFT 14 /* DSP2CLK_ENA */ 2331*4882a593Smuzhiyun #define WM8958_DSP2CLK_ENA_WIDTH 1 /* DSP2CLK_ENA */ 2332*4882a593Smuzhiyun #define WM8958_DSP2CLK_SRC 0x1000 /* DSP2CLK_SRC */ 2333*4882a593Smuzhiyun #define WM8958_DSP2CLK_SRC_MASK 0x1000 /* DSP2CLK_SRC */ 2334*4882a593Smuzhiyun #define WM8958_DSP2CLK_SRC_SHIFT 12 /* DSP2CLK_SRC */ 2335*4882a593Smuzhiyun #define WM8958_DSP2CLK_SRC_WIDTH 1 /* DSP2CLK_SRC */ 2336*4882a593Smuzhiyun #define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 2337*4882a593Smuzhiyun #define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 2338*4882a593Smuzhiyun #define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 2339*4882a593Smuzhiyun #define WM8994_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 2340*4882a593Smuzhiyun #define WM8994_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ 2341*4882a593Smuzhiyun #define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ 2342*4882a593Smuzhiyun #define WM8994_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ 2343*4882a593Smuzhiyun #define WM8994_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ 2344*4882a593Smuzhiyun #define WM8994_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ 2345*4882a593Smuzhiyun #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ 2346*4882a593Smuzhiyun #define WM8994_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ 2347*4882a593Smuzhiyun #define WM8994_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ 2348*4882a593Smuzhiyun #define WM8994_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 2349*4882a593Smuzhiyun #define WM8994_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 2350*4882a593Smuzhiyun #define WM8994_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 2351*4882a593Smuzhiyun #define WM8994_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 2352*4882a593Smuzhiyun #define WM8994_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ 2353*4882a593Smuzhiyun #define WM8994_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ 2354*4882a593Smuzhiyun #define WM8994_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ 2355*4882a593Smuzhiyun #define WM8994_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 2356*4882a593Smuzhiyun 2357*4882a593Smuzhiyun /* 2358*4882a593Smuzhiyun * R521 (0x209) - Clocking (2) 2359*4882a593Smuzhiyun */ 2360*4882a593Smuzhiyun #define WM8994_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 2361*4882a593Smuzhiyun #define WM8994_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 2362*4882a593Smuzhiyun #define WM8994_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 2363*4882a593Smuzhiyun #define WM8994_DBCLK_DIV_MASK 0x0070 /* DBCLK_DIV - [6:4] */ 2364*4882a593Smuzhiyun #define WM8994_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [6:4] */ 2365*4882a593Smuzhiyun #define WM8994_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [6:4] */ 2366*4882a593Smuzhiyun #define WM8994_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 2367*4882a593Smuzhiyun #define WM8994_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 2368*4882a593Smuzhiyun #define WM8994_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 2369*4882a593Smuzhiyun 2370*4882a593Smuzhiyun /* 2371*4882a593Smuzhiyun * R528 (0x210) - AIF1 Rate 2372*4882a593Smuzhiyun */ 2373*4882a593Smuzhiyun #define WM8994_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ 2374*4882a593Smuzhiyun #define WM8994_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ 2375*4882a593Smuzhiyun #define WM8994_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ 2376*4882a593Smuzhiyun #define WM8994_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ 2377*4882a593Smuzhiyun #define WM8994_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ 2378*4882a593Smuzhiyun #define WM8994_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ 2379*4882a593Smuzhiyun 2380*4882a593Smuzhiyun /* 2381*4882a593Smuzhiyun * R529 (0x211) - AIF2 Rate 2382*4882a593Smuzhiyun */ 2383*4882a593Smuzhiyun #define WM8994_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ 2384*4882a593Smuzhiyun #define WM8994_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ 2385*4882a593Smuzhiyun #define WM8994_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ 2386*4882a593Smuzhiyun #define WM8994_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ 2387*4882a593Smuzhiyun #define WM8994_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ 2388*4882a593Smuzhiyun #define WM8994_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ 2389*4882a593Smuzhiyun 2390*4882a593Smuzhiyun /* 2391*4882a593Smuzhiyun * R530 (0x212) - Rate Status 2392*4882a593Smuzhiyun */ 2393*4882a593Smuzhiyun #define WM8994_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ 2394*4882a593Smuzhiyun #define WM8994_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ 2395*4882a593Smuzhiyun #define WM8994_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ 2396*4882a593Smuzhiyun 2397*4882a593Smuzhiyun /* 2398*4882a593Smuzhiyun * R544 (0x220) - FLL1 Control (1) 2399*4882a593Smuzhiyun */ 2400*4882a593Smuzhiyun #define WM8994_FLL1_FRAC 0x0004 /* FLL1_FRAC */ 2401*4882a593Smuzhiyun #define WM8994_FLL1_FRAC_MASK 0x0004 /* FLL1_FRAC */ 2402*4882a593Smuzhiyun #define WM8994_FLL1_FRAC_SHIFT 2 /* FLL1_FRAC */ 2403*4882a593Smuzhiyun #define WM8994_FLL1_FRAC_WIDTH 1 /* FLL1_FRAC */ 2404*4882a593Smuzhiyun #define WM8994_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ 2405*4882a593Smuzhiyun #define WM8994_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ 2406*4882a593Smuzhiyun #define WM8994_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ 2407*4882a593Smuzhiyun #define WM8994_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ 2408*4882a593Smuzhiyun #define WM8994_FLL1_ENA 0x0001 /* FLL1_ENA */ 2409*4882a593Smuzhiyun #define WM8994_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 2410*4882a593Smuzhiyun #define WM8994_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 2411*4882a593Smuzhiyun #define WM8994_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 2412*4882a593Smuzhiyun 2413*4882a593Smuzhiyun /* 2414*4882a593Smuzhiyun * R545 (0x221) - FLL1 Control (2) 2415*4882a593Smuzhiyun */ 2416*4882a593Smuzhiyun #define WM8994_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 2417*4882a593Smuzhiyun #define WM8994_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 2418*4882a593Smuzhiyun #define WM8994_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 2419*4882a593Smuzhiyun #define WM8994_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ 2420*4882a593Smuzhiyun #define WM8994_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ 2421*4882a593Smuzhiyun #define WM8994_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ 2422*4882a593Smuzhiyun #define WM8994_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 2423*4882a593Smuzhiyun #define WM8994_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 2424*4882a593Smuzhiyun #define WM8994_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 2425*4882a593Smuzhiyun 2426*4882a593Smuzhiyun /* 2427*4882a593Smuzhiyun * R546 (0x222) - FLL1 Control (3) 2428*4882a593Smuzhiyun */ 2429*4882a593Smuzhiyun #define WM8994_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ 2430*4882a593Smuzhiyun #define WM8994_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ 2431*4882a593Smuzhiyun #define WM8994_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ 2432*4882a593Smuzhiyun 2433*4882a593Smuzhiyun /* 2434*4882a593Smuzhiyun * R547 (0x223) - FLL1 Control (4) 2435*4882a593Smuzhiyun */ 2436*4882a593Smuzhiyun #define WM8994_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ 2437*4882a593Smuzhiyun #define WM8994_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ 2438*4882a593Smuzhiyun #define WM8994_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ 2439*4882a593Smuzhiyun #define WM8994_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ 2440*4882a593Smuzhiyun #define WM8994_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ 2441*4882a593Smuzhiyun #define WM8994_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ 2442*4882a593Smuzhiyun 2443*4882a593Smuzhiyun /* 2444*4882a593Smuzhiyun * R548 (0x224) - FLL1 Control (5) 2445*4882a593Smuzhiyun */ 2446*4882a593Smuzhiyun #define WM8958_FLL1_BYP 0x8000 /* FLL1_BYP */ 2447*4882a593Smuzhiyun #define WM8958_FLL1_BYP_MASK 0x8000 /* FLL1_BYP */ 2448*4882a593Smuzhiyun #define WM8958_FLL1_BYP_SHIFT 15 /* FLL1_BYP */ 2449*4882a593Smuzhiyun #define WM8958_FLL1_BYP_WIDTH 1 /* FLL1_BYP */ 2450*4882a593Smuzhiyun #define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 2451*4882a593Smuzhiyun #define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 2452*4882a593Smuzhiyun #define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 2453*4882a593Smuzhiyun #define WM8994_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ 2454*4882a593Smuzhiyun #define WM8994_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ 2455*4882a593Smuzhiyun #define WM8994_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ 2456*4882a593Smuzhiyun #define WM8994_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ 2457*4882a593Smuzhiyun #define WM8994_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ 2458*4882a593Smuzhiyun #define WM8994_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ 2459*4882a593Smuzhiyun #define WM8994_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ 2460*4882a593Smuzhiyun #define WM8994_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ 2461*4882a593Smuzhiyun #define WM8994_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ 2462*4882a593Smuzhiyun #define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 2463*4882a593Smuzhiyun 2464*4882a593Smuzhiyun /* 2465*4882a593Smuzhiyun * R550 (0x226) - FLL1 EFS 1 2466*4882a593Smuzhiyun */ 2467*4882a593Smuzhiyun #define WM8958_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */ 2468*4882a593Smuzhiyun #define WM8958_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */ 2469*4882a593Smuzhiyun #define WM8958_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */ 2470*4882a593Smuzhiyun 2471*4882a593Smuzhiyun /* 2472*4882a593Smuzhiyun * R551 (0x227) - FLL1 EFS 2 2473*4882a593Smuzhiyun */ 2474*4882a593Smuzhiyun #define WM8958_FLL1_LFSR_SEL_MASK 0x0006 /* FLL1_LFSR_SEL - [2:1] */ 2475*4882a593Smuzhiyun #define WM8958_FLL1_LFSR_SEL_SHIFT 1 /* FLL1_LFSR_SEL - [2:1] */ 2476*4882a593Smuzhiyun #define WM8958_FLL1_LFSR_SEL_WIDTH 2 /* FLL1_LFSR_SEL - [2:1] */ 2477*4882a593Smuzhiyun #define WM8958_FLL1_EFS_ENA 0x0001 /* FLL1_EFS_ENA */ 2478*4882a593Smuzhiyun #define WM8958_FLL1_EFS_ENA_MASK 0x0001 /* FLL1_EFS_ENA */ 2479*4882a593Smuzhiyun #define WM8958_FLL1_EFS_ENA_SHIFT 0 /* FLL1_EFS_ENA */ 2480*4882a593Smuzhiyun #define WM8958_FLL1_EFS_ENA_WIDTH 1 /* FLL1_EFS_ENA */ 2481*4882a593Smuzhiyun 2482*4882a593Smuzhiyun /* 2483*4882a593Smuzhiyun * R576 (0x240) - FLL2 Control (1) 2484*4882a593Smuzhiyun */ 2485*4882a593Smuzhiyun #define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */ 2486*4882a593Smuzhiyun #define WM8994_FLL2_FRAC_MASK 0x0004 /* FLL2_FRAC */ 2487*4882a593Smuzhiyun #define WM8994_FLL2_FRAC_SHIFT 2 /* FLL2_FRAC */ 2488*4882a593Smuzhiyun #define WM8994_FLL2_FRAC_WIDTH 1 /* FLL2_FRAC */ 2489*4882a593Smuzhiyun #define WM8994_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ 2490*4882a593Smuzhiyun #define WM8994_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ 2491*4882a593Smuzhiyun #define WM8994_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ 2492*4882a593Smuzhiyun #define WM8994_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ 2493*4882a593Smuzhiyun #define WM8994_FLL2_ENA 0x0001 /* FLL2_ENA */ 2494*4882a593Smuzhiyun #define WM8994_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 2495*4882a593Smuzhiyun #define WM8994_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 2496*4882a593Smuzhiyun #define WM8994_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 2497*4882a593Smuzhiyun 2498*4882a593Smuzhiyun /* 2499*4882a593Smuzhiyun * R577 (0x241) - FLL2 Control (2) 2500*4882a593Smuzhiyun */ 2501*4882a593Smuzhiyun #define WM8994_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 2502*4882a593Smuzhiyun #define WM8994_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 2503*4882a593Smuzhiyun #define WM8994_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 2504*4882a593Smuzhiyun #define WM8994_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ 2505*4882a593Smuzhiyun #define WM8994_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ 2506*4882a593Smuzhiyun #define WM8994_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ 2507*4882a593Smuzhiyun #define WM8994_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 2508*4882a593Smuzhiyun #define WM8994_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 2509*4882a593Smuzhiyun #define WM8994_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 2510*4882a593Smuzhiyun 2511*4882a593Smuzhiyun /* 2512*4882a593Smuzhiyun * R578 (0x242) - FLL2 Control (3) 2513*4882a593Smuzhiyun */ 2514*4882a593Smuzhiyun #define WM8994_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ 2515*4882a593Smuzhiyun #define WM8994_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ 2516*4882a593Smuzhiyun #define WM8994_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ 2517*4882a593Smuzhiyun 2518*4882a593Smuzhiyun /* 2519*4882a593Smuzhiyun * R579 (0x243) - FLL2 Control (4) 2520*4882a593Smuzhiyun */ 2521*4882a593Smuzhiyun #define WM8994_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ 2522*4882a593Smuzhiyun #define WM8994_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ 2523*4882a593Smuzhiyun #define WM8994_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ 2524*4882a593Smuzhiyun #define WM8994_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ 2525*4882a593Smuzhiyun #define WM8994_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ 2526*4882a593Smuzhiyun #define WM8994_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ 2527*4882a593Smuzhiyun 2528*4882a593Smuzhiyun /* 2529*4882a593Smuzhiyun * R580 (0x244) - FLL2 Control (5) 2530*4882a593Smuzhiyun */ 2531*4882a593Smuzhiyun #define WM8958_FLL2_BYP 0x8000 /* FLL2_BYP */ 2532*4882a593Smuzhiyun #define WM8958_FLL2_BYP_MASK 0x8000 /* FLL2_BYP */ 2533*4882a593Smuzhiyun #define WM8958_FLL2_BYP_SHIFT 15 /* FLL2_BYP */ 2534*4882a593Smuzhiyun #define WM8958_FLL2_BYP_WIDTH 1 /* FLL2_BYP */ 2535*4882a593Smuzhiyun #define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 2536*4882a593Smuzhiyun #define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 2537*4882a593Smuzhiyun #define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 2538*4882a593Smuzhiyun #define WM8994_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ 2539*4882a593Smuzhiyun #define WM8994_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ 2540*4882a593Smuzhiyun #define WM8994_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ 2541*4882a593Smuzhiyun #define WM8994_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ 2542*4882a593Smuzhiyun #define WM8994_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ 2543*4882a593Smuzhiyun #define WM8994_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ 2544*4882a593Smuzhiyun #define WM8994_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ 2545*4882a593Smuzhiyun #define WM8994_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ 2546*4882a593Smuzhiyun #define WM8994_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ 2547*4882a593Smuzhiyun #define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 2548*4882a593Smuzhiyun 2549*4882a593Smuzhiyun /* 2550*4882a593Smuzhiyun * R582 (0x246) - FLL2 EFS 1 2551*4882a593Smuzhiyun */ 2552*4882a593Smuzhiyun #define WM8958_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */ 2553*4882a593Smuzhiyun #define WM8958_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */ 2554*4882a593Smuzhiyun #define WM8958_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */ 2555*4882a593Smuzhiyun 2556*4882a593Smuzhiyun /* 2557*4882a593Smuzhiyun * R583 (0x247) - FLL2 EFS 2 2558*4882a593Smuzhiyun */ 2559*4882a593Smuzhiyun #define WM8958_FLL2_LFSR_SEL_MASK 0x0006 /* FLL2_LFSR_SEL - [2:1] */ 2560*4882a593Smuzhiyun #define WM8958_FLL2_LFSR_SEL_SHIFT 1 /* FLL2_LFSR_SEL - [2:1] */ 2561*4882a593Smuzhiyun #define WM8958_FLL2_LFSR_SEL_WIDTH 2 /* FLL2_LFSR_SEL - [2:1] */ 2562*4882a593Smuzhiyun #define WM8958_FLL2_EFS_ENA 0x0001 /* FLL2_EFS_ENA */ 2563*4882a593Smuzhiyun #define WM8958_FLL2_EFS_ENA_MASK 0x0001 /* FLL2_EFS_ENA */ 2564*4882a593Smuzhiyun #define WM8958_FLL2_EFS_ENA_SHIFT 0 /* FLL2_EFS_ENA */ 2565*4882a593Smuzhiyun #define WM8958_FLL2_EFS_ENA_WIDTH 1 /* FLL2_EFS_ENA */ 2566*4882a593Smuzhiyun 2567*4882a593Smuzhiyun /* 2568*4882a593Smuzhiyun * R768 (0x300) - AIF1 Control (1) 2569*4882a593Smuzhiyun */ 2570*4882a593Smuzhiyun #define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 2571*4882a593Smuzhiyun #define WM8994_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ 2572*4882a593Smuzhiyun #define WM8994_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ 2573*4882a593Smuzhiyun #define WM8994_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ 2574*4882a593Smuzhiyun #define WM8994_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ 2575*4882a593Smuzhiyun #define WM8994_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ 2576*4882a593Smuzhiyun #define WM8994_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ 2577*4882a593Smuzhiyun #define WM8994_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ 2578*4882a593Smuzhiyun #define WM8994_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ 2579*4882a593Smuzhiyun #define WM8994_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ 2580*4882a593Smuzhiyun #define WM8994_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ 2581*4882a593Smuzhiyun #define WM8994_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ 2582*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ 2583*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ 2584*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ 2585*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 2586*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ 2587*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ 2588*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ 2589*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 2590*4882a593Smuzhiyun #define WM8994_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ 2591*4882a593Smuzhiyun #define WM8994_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ 2592*4882a593Smuzhiyun #define WM8994_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ 2593*4882a593Smuzhiyun #define WM8994_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ 2594*4882a593Smuzhiyun #define WM8994_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ 2595*4882a593Smuzhiyun #define WM8994_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ 2596*4882a593Smuzhiyun 2597*4882a593Smuzhiyun /* 2598*4882a593Smuzhiyun * R769 (0x301) - AIF1 Control (2) 2599*4882a593Smuzhiyun */ 2600*4882a593Smuzhiyun #define WM8994_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ 2601*4882a593Smuzhiyun #define WM8994_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ 2602*4882a593Smuzhiyun #define WM8994_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ 2603*4882a593Smuzhiyun #define WM8994_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ 2604*4882a593Smuzhiyun #define WM8994_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ 2605*4882a593Smuzhiyun #define WM8994_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ 2606*4882a593Smuzhiyun #define WM8994_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ 2607*4882a593Smuzhiyun #define WM8994_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ 2608*4882a593Smuzhiyun #define WM8994_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ 2609*4882a593Smuzhiyun #define WM8994_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ 2610*4882a593Smuzhiyun #define WM8994_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ 2611*4882a593Smuzhiyun #define WM8994_AIF1_MONO 0x0100 /* AIF1_MONO */ 2612*4882a593Smuzhiyun #define WM8994_AIF1_MONO_MASK 0x0100 /* AIF1_MONO */ 2613*4882a593Smuzhiyun #define WM8994_AIF1_MONO_SHIFT 8 /* AIF1_MONO */ 2614*4882a593Smuzhiyun #define WM8994_AIF1_MONO_WIDTH 1 /* AIF1_MONO */ 2615*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ 2616*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ 2617*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ 2618*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ 2619*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ 2620*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ 2621*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ 2622*4882a593Smuzhiyun #define WM8994_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ 2623*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ 2624*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ 2625*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ 2626*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ 2627*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ 2628*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ 2629*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ 2630*4882a593Smuzhiyun #define WM8994_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ 2631*4882a593Smuzhiyun #define WM8994_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ 2632*4882a593Smuzhiyun #define WM8994_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ 2633*4882a593Smuzhiyun #define WM8994_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ 2634*4882a593Smuzhiyun #define WM8994_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ 2635*4882a593Smuzhiyun 2636*4882a593Smuzhiyun /* 2637*4882a593Smuzhiyun * R770 (0x302) - AIF1 Master/Slave 2638*4882a593Smuzhiyun */ 2639*4882a593Smuzhiyun #define WM8994_AIF1_TRI 0x8000 /* AIF1_TRI */ 2640*4882a593Smuzhiyun #define WM8994_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ 2641*4882a593Smuzhiyun #define WM8994_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ 2642*4882a593Smuzhiyun #define WM8994_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 2643*4882a593Smuzhiyun #define WM8994_AIF1_MSTR 0x4000 /* AIF1_MSTR */ 2644*4882a593Smuzhiyun #define WM8994_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ 2645*4882a593Smuzhiyun #define WM8994_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ 2646*4882a593Smuzhiyun #define WM8994_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ 2647*4882a593Smuzhiyun #define WM8994_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ 2648*4882a593Smuzhiyun #define WM8994_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ 2649*4882a593Smuzhiyun #define WM8994_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ 2650*4882a593Smuzhiyun #define WM8994_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ 2651*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ 2652*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ 2653*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ 2654*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ 2655*4882a593Smuzhiyun 2656*4882a593Smuzhiyun /* 2657*4882a593Smuzhiyun * R771 (0x303) - AIF1 BCLK 2658*4882a593Smuzhiyun */ 2659*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 /* AIF1_BCLK_DIV - [8:4] */ 2660*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [8:4] */ 2661*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_DIV_WIDTH 5 /* AIF1_BCLK_DIV - [8:4] */ 2662*4882a593Smuzhiyun 2663*4882a593Smuzhiyun /* 2664*4882a593Smuzhiyun * R772 (0x304) - AIF1ADC LRCLK 2665*4882a593Smuzhiyun */ 2666*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV 0x1000 /* AIF1_LRCLK_INV */ 2667*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV_MASK 0x1000 /* AIF1_LRCLK_INV */ 2668*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV_SHIFT 12 /* AIF1_LRCLK_INV */ 2669*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 2670*4882a593Smuzhiyun #define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ 2671*4882a593Smuzhiyun #define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ 2672*4882a593Smuzhiyun #define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ 2673*4882a593Smuzhiyun #define WM8994_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ 2674*4882a593Smuzhiyun #define WM8994_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ 2675*4882a593Smuzhiyun #define WM8994_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ 2676*4882a593Smuzhiyun #define WM8994_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ 2677*4882a593Smuzhiyun 2678*4882a593Smuzhiyun /* 2679*4882a593Smuzhiyun * R773 (0x305) - AIF1DAC LRCLK 2680*4882a593Smuzhiyun */ 2681*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV 0x1000 /* AIF1_LRCLK_INV */ 2682*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV_MASK 0x1000 /* AIF1_LRCLK_INV */ 2683*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV_SHIFT 12 /* AIF1_LRCLK_INV */ 2684*4882a593Smuzhiyun #define WM8958_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 2685*4882a593Smuzhiyun #define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ 2686*4882a593Smuzhiyun #define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ 2687*4882a593Smuzhiyun #define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ 2688*4882a593Smuzhiyun #define WM8994_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ 2689*4882a593Smuzhiyun #define WM8994_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ 2690*4882a593Smuzhiyun #define WM8994_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ 2691*4882a593Smuzhiyun #define WM8994_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ 2692*4882a593Smuzhiyun 2693*4882a593Smuzhiyun /* 2694*4882a593Smuzhiyun * R774 (0x306) - AIF1DAC Data 2695*4882a593Smuzhiyun */ 2696*4882a593Smuzhiyun #define WM8994_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ 2697*4882a593Smuzhiyun #define WM8994_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ 2698*4882a593Smuzhiyun #define WM8994_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ 2699*4882a593Smuzhiyun #define WM8994_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ 2700*4882a593Smuzhiyun #define WM8994_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ 2701*4882a593Smuzhiyun #define WM8994_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ 2702*4882a593Smuzhiyun #define WM8994_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ 2703*4882a593Smuzhiyun #define WM8994_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ 2704*4882a593Smuzhiyun 2705*4882a593Smuzhiyun /* 2706*4882a593Smuzhiyun * R775 (0x307) - AIF1ADC Data 2707*4882a593Smuzhiyun */ 2708*4882a593Smuzhiyun #define WM8994_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ 2709*4882a593Smuzhiyun #define WM8994_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ 2710*4882a593Smuzhiyun #define WM8994_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ 2711*4882a593Smuzhiyun #define WM8994_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ 2712*4882a593Smuzhiyun #define WM8994_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ 2713*4882a593Smuzhiyun #define WM8994_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ 2714*4882a593Smuzhiyun #define WM8994_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ 2715*4882a593Smuzhiyun #define WM8994_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ 2716*4882a593Smuzhiyun 2717*4882a593Smuzhiyun /* 2718*4882a593Smuzhiyun * R784 (0x310) - AIF2 Control (1) 2719*4882a593Smuzhiyun */ 2720*4882a593Smuzhiyun #define WM8994_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ 2721*4882a593Smuzhiyun #define WM8994_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ 2722*4882a593Smuzhiyun #define WM8994_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ 2723*4882a593Smuzhiyun #define WM8994_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ 2724*4882a593Smuzhiyun #define WM8994_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ 2725*4882a593Smuzhiyun #define WM8994_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ 2726*4882a593Smuzhiyun #define WM8994_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ 2727*4882a593Smuzhiyun #define WM8994_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ 2728*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ 2729*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ 2730*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ 2731*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ 2732*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ 2733*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ 2734*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ 2735*4882a593Smuzhiyun #define WM8994_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ 2736*4882a593Smuzhiyun #define WM8994_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ 2737*4882a593Smuzhiyun #define WM8994_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ 2738*4882a593Smuzhiyun #define WM8994_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ 2739*4882a593Smuzhiyun #define WM8994_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2740*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ 2741*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ 2742*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ 2743*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ 2744*4882a593Smuzhiyun #define WM8994_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ 2745*4882a593Smuzhiyun #define WM8994_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ 2746*4882a593Smuzhiyun #define WM8994_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ 2747*4882a593Smuzhiyun #define WM8994_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ 2748*4882a593Smuzhiyun #define WM8994_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ 2749*4882a593Smuzhiyun #define WM8994_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ 2750*4882a593Smuzhiyun 2751*4882a593Smuzhiyun /* 2752*4882a593Smuzhiyun * R785 (0x311) - AIF2 Control (2) 2753*4882a593Smuzhiyun */ 2754*4882a593Smuzhiyun #define WM8994_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ 2755*4882a593Smuzhiyun #define WM8994_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ 2756*4882a593Smuzhiyun #define WM8994_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ 2757*4882a593Smuzhiyun #define WM8994_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ 2758*4882a593Smuzhiyun #define WM8994_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ 2759*4882a593Smuzhiyun #define WM8994_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ 2760*4882a593Smuzhiyun #define WM8994_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ 2761*4882a593Smuzhiyun #define WM8994_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ 2762*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ 2763*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ 2764*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ 2765*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ 2766*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ 2767*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ 2768*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ 2769*4882a593Smuzhiyun #define WM8994_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ 2770*4882a593Smuzhiyun #define WM8994_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ 2771*4882a593Smuzhiyun #define WM8994_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ 2772*4882a593Smuzhiyun #define WM8994_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ 2773*4882a593Smuzhiyun #define WM8994_AIF2_MONO 0x0100 /* AIF2_MONO */ 2774*4882a593Smuzhiyun #define WM8994_AIF2_MONO_MASK 0x0100 /* AIF2_MONO */ 2775*4882a593Smuzhiyun #define WM8994_AIF2_MONO_SHIFT 8 /* AIF2_MONO */ 2776*4882a593Smuzhiyun #define WM8994_AIF2_MONO_WIDTH 1 /* AIF2_MONO */ 2777*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ 2778*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ 2779*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ 2780*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ 2781*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ 2782*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ 2783*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ 2784*4882a593Smuzhiyun #define WM8994_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ 2785*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ 2786*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ 2787*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ 2788*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ 2789*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ 2790*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ 2791*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ 2792*4882a593Smuzhiyun #define WM8994_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ 2793*4882a593Smuzhiyun #define WM8994_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ 2794*4882a593Smuzhiyun #define WM8994_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ 2795*4882a593Smuzhiyun #define WM8994_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ 2796*4882a593Smuzhiyun #define WM8994_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ 2797*4882a593Smuzhiyun 2798*4882a593Smuzhiyun /* 2799*4882a593Smuzhiyun * R786 (0x312) - AIF2 Master/Slave 2800*4882a593Smuzhiyun */ 2801*4882a593Smuzhiyun #define WM8994_AIF2_TRI 0x8000 /* AIF2_TRI */ 2802*4882a593Smuzhiyun #define WM8994_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ 2803*4882a593Smuzhiyun #define WM8994_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ 2804*4882a593Smuzhiyun #define WM8994_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2805*4882a593Smuzhiyun #define WM8994_AIF2_MSTR 0x4000 /* AIF2_MSTR */ 2806*4882a593Smuzhiyun #define WM8994_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ 2807*4882a593Smuzhiyun #define WM8994_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ 2808*4882a593Smuzhiyun #define WM8994_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ 2809*4882a593Smuzhiyun #define WM8994_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ 2810*4882a593Smuzhiyun #define WM8994_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ 2811*4882a593Smuzhiyun #define WM8994_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ 2812*4882a593Smuzhiyun #define WM8994_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ 2813*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ 2814*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ 2815*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ 2816*4882a593Smuzhiyun #define WM8994_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ 2817*4882a593Smuzhiyun 2818*4882a593Smuzhiyun /* 2819*4882a593Smuzhiyun * R787 (0x313) - AIF2 BCLK 2820*4882a593Smuzhiyun */ 2821*4882a593Smuzhiyun #define WM8994_AIF2_BCLK_DIV_MASK 0x01F0 /* AIF2_BCLK_DIV - [8:4] */ 2822*4882a593Smuzhiyun #define WM8994_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [8:4] */ 2823*4882a593Smuzhiyun #define WM8994_AIF2_BCLK_DIV_WIDTH 5 /* AIF2_BCLK_DIV - [8:4] */ 2824*4882a593Smuzhiyun 2825*4882a593Smuzhiyun /* 2826*4882a593Smuzhiyun * R788 (0x314) - AIF2ADC LRCLK 2827*4882a593Smuzhiyun */ 2828*4882a593Smuzhiyun #define WM8994_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ 2829*4882a593Smuzhiyun #define WM8994_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ 2830*4882a593Smuzhiyun #define WM8994_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ 2831*4882a593Smuzhiyun #define WM8994_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ 2832*4882a593Smuzhiyun #define WM8994_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ 2833*4882a593Smuzhiyun #define WM8994_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ 2834*4882a593Smuzhiyun #define WM8994_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ 2835*4882a593Smuzhiyun 2836*4882a593Smuzhiyun /* 2837*4882a593Smuzhiyun * R789 (0x315) - AIF2DAC LRCLK 2838*4882a593Smuzhiyun */ 2839*4882a593Smuzhiyun #define WM8994_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ 2840*4882a593Smuzhiyun #define WM8994_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ 2841*4882a593Smuzhiyun #define WM8994_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ 2842*4882a593Smuzhiyun #define WM8994_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ 2843*4882a593Smuzhiyun #define WM8994_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ 2844*4882a593Smuzhiyun #define WM8994_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ 2845*4882a593Smuzhiyun #define WM8994_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ 2846*4882a593Smuzhiyun 2847*4882a593Smuzhiyun /* 2848*4882a593Smuzhiyun * R790 (0x316) - AIF2DAC Data 2849*4882a593Smuzhiyun */ 2850*4882a593Smuzhiyun #define WM8994_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ 2851*4882a593Smuzhiyun #define WM8994_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ 2852*4882a593Smuzhiyun #define WM8994_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ 2853*4882a593Smuzhiyun #define WM8994_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ 2854*4882a593Smuzhiyun #define WM8994_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ 2855*4882a593Smuzhiyun #define WM8994_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ 2856*4882a593Smuzhiyun #define WM8994_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ 2857*4882a593Smuzhiyun #define WM8994_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ 2858*4882a593Smuzhiyun 2859*4882a593Smuzhiyun /* 2860*4882a593Smuzhiyun * R791 (0x317) - AIF2ADC Data 2861*4882a593Smuzhiyun */ 2862*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ 2863*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ 2864*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ 2865*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ 2866*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ 2867*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ 2868*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ 2869*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ 2870*4882a593Smuzhiyun 2871*4882a593Smuzhiyun /* 2872*4882a593Smuzhiyun * R800 (0x320) - AIF3 Control (1) 2873*4882a593Smuzhiyun */ 2874*4882a593Smuzhiyun #define WM8958_AIF3_LRCLK_INV 0x0080 /* AIF3_LRCLK_INV */ 2875*4882a593Smuzhiyun #define WM8958_AIF3_LRCLK_INV_MASK 0x0080 /* AIF3_LRCLK_INV */ 2876*4882a593Smuzhiyun #define WM8958_AIF3_LRCLK_INV_SHIFT 7 /* AIF3_LRCLK_INV */ 2877*4882a593Smuzhiyun #define WM8958_AIF3_LRCLK_INV_WIDTH 1 /* AIF3_LRCLK_INV */ 2878*4882a593Smuzhiyun #define WM8958_AIF3_WL_MASK 0x0060 /* AIF3_WL - [6:5] */ 2879*4882a593Smuzhiyun #define WM8958_AIF3_WL_SHIFT 5 /* AIF3_WL - [6:5] */ 2880*4882a593Smuzhiyun #define WM8958_AIF3_WL_WIDTH 2 /* AIF3_WL - [6:5] */ 2881*4882a593Smuzhiyun #define WM8958_AIF3_FMT_MASK 0x0018 /* AIF3_FMT - [4:3] */ 2882*4882a593Smuzhiyun #define WM8958_AIF3_FMT_SHIFT 3 /* AIF3_FMT - [4:3] */ 2883*4882a593Smuzhiyun #define WM8958_AIF3_FMT_WIDTH 2 /* AIF3_FMT - [4:3] */ 2884*4882a593Smuzhiyun 2885*4882a593Smuzhiyun /* 2886*4882a593Smuzhiyun * R801 (0x321) - AIF3 Control (2) 2887*4882a593Smuzhiyun */ 2888*4882a593Smuzhiyun #define WM8958_AIF3DAC_BOOST_MASK 0x0C00 /* AIF3DAC_BOOST - [11:10] */ 2889*4882a593Smuzhiyun #define WM8958_AIF3DAC_BOOST_SHIFT 10 /* AIF3DAC_BOOST - [11:10] */ 2890*4882a593Smuzhiyun #define WM8958_AIF3DAC_BOOST_WIDTH 2 /* AIF3DAC_BOOST - [11:10] */ 2891*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMP 0x0010 /* AIF3DAC_COMP */ 2892*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMP_MASK 0x0010 /* AIF3DAC_COMP */ 2893*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMP_SHIFT 4 /* AIF3DAC_COMP */ 2894*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMP_WIDTH 1 /* AIF3DAC_COMP */ 2895*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMPMODE 0x0008 /* AIF3DAC_COMPMODE */ 2896*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMPMODE_MASK 0x0008 /* AIF3DAC_COMPMODE */ 2897*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMPMODE_SHIFT 3 /* AIF3DAC_COMPMODE */ 2898*4882a593Smuzhiyun #define WM8958_AIF3DAC_COMPMODE_WIDTH 1 /* AIF3DAC_COMPMODE */ 2899*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMP 0x0004 /* AIF3ADC_COMP */ 2900*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMP_MASK 0x0004 /* AIF3ADC_COMP */ 2901*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMP_SHIFT 2 /* AIF3ADC_COMP */ 2902*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMP_WIDTH 1 /* AIF3ADC_COMP */ 2903*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMPMODE 0x0002 /* AIF3ADC_COMPMODE */ 2904*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMPMODE_MASK 0x0002 /* AIF3ADC_COMPMODE */ 2905*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMPMODE_SHIFT 1 /* AIF3ADC_COMPMODE */ 2906*4882a593Smuzhiyun #define WM8958_AIF3ADC_COMPMODE_WIDTH 1 /* AIF3ADC_COMPMODE */ 2907*4882a593Smuzhiyun #define WM8958_AIF3_LOOPBACK 0x0001 /* AIF3_LOOPBACK */ 2908*4882a593Smuzhiyun #define WM8958_AIF3_LOOPBACK_MASK 0x0001 /* AIF3_LOOPBACK */ 2909*4882a593Smuzhiyun #define WM8958_AIF3_LOOPBACK_SHIFT 0 /* AIF3_LOOPBACK */ 2910*4882a593Smuzhiyun #define WM8958_AIF3_LOOPBACK_WIDTH 1 /* AIF3_LOOPBACK */ 2911*4882a593Smuzhiyun 2912*4882a593Smuzhiyun /* 2913*4882a593Smuzhiyun * R802 (0x322) - AIF3DAC Data 2914*4882a593Smuzhiyun */ 2915*4882a593Smuzhiyun #define WM8958_AIF3DAC_DAT_INV 0x0001 /* AIF3DAC_DAT_INV */ 2916*4882a593Smuzhiyun #define WM8958_AIF3DAC_DAT_INV_MASK 0x0001 /* AIF3DAC_DAT_INV */ 2917*4882a593Smuzhiyun #define WM8958_AIF3DAC_DAT_INV_SHIFT 0 /* AIF3DAC_DAT_INV */ 2918*4882a593Smuzhiyun #define WM8958_AIF3DAC_DAT_INV_WIDTH 1 /* AIF3DAC_DAT_INV */ 2919*4882a593Smuzhiyun 2920*4882a593Smuzhiyun /* 2921*4882a593Smuzhiyun * R803 (0x323) - AIF3ADC Data 2922*4882a593Smuzhiyun */ 2923*4882a593Smuzhiyun #define WM8958_AIF3ADC_DAT_INV 0x0001 /* AIF3ADC_DAT_INV */ 2924*4882a593Smuzhiyun #define WM8958_AIF3ADC_DAT_INV_MASK 0x0001 /* AIF3ADC_DAT_INV */ 2925*4882a593Smuzhiyun #define WM8958_AIF3ADC_DAT_INV_SHIFT 0 /* AIF3ADC_DAT_INV */ 2926*4882a593Smuzhiyun #define WM8958_AIF3ADC_DAT_INV_WIDTH 1 /* AIF3ADC_DAT_INV */ 2927*4882a593Smuzhiyun 2928*4882a593Smuzhiyun /* 2929*4882a593Smuzhiyun * R1024 (0x400) - AIF1 ADC1 Left Volume 2930*4882a593Smuzhiyun */ 2931*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2932*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2933*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2934*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2935*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ 2936*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ 2937*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ 2938*4882a593Smuzhiyun 2939*4882a593Smuzhiyun /* 2940*4882a593Smuzhiyun * R1025 (0x401) - AIF1 ADC1 Right Volume 2941*4882a593Smuzhiyun */ 2942*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2943*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2944*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2945*4882a593Smuzhiyun #define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2946*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ 2947*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ 2948*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ 2949*4882a593Smuzhiyun 2950*4882a593Smuzhiyun /* 2951*4882a593Smuzhiyun * R1026 (0x402) - AIF1 DAC1 Left Volume 2952*4882a593Smuzhiyun */ 2953*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2954*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2955*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2956*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2957*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ 2958*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ 2959*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ 2960*4882a593Smuzhiyun 2961*4882a593Smuzhiyun /* 2962*4882a593Smuzhiyun * R1027 (0x403) - AIF1 DAC1 Right Volume 2963*4882a593Smuzhiyun */ 2964*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2965*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2966*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2967*4882a593Smuzhiyun #define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2968*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ 2969*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ 2970*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ 2971*4882a593Smuzhiyun 2972*4882a593Smuzhiyun /* 2973*4882a593Smuzhiyun * R1028 (0x404) - AIF1 ADC2 Left Volume 2974*4882a593Smuzhiyun */ 2975*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2976*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2977*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2978*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2979*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ 2980*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ 2981*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ 2982*4882a593Smuzhiyun 2983*4882a593Smuzhiyun /* 2984*4882a593Smuzhiyun * R1029 (0x405) - AIF1 ADC2 Right Volume 2985*4882a593Smuzhiyun */ 2986*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2987*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2988*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2989*4882a593Smuzhiyun #define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2990*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ 2991*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ 2992*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ 2993*4882a593Smuzhiyun 2994*4882a593Smuzhiyun /* 2995*4882a593Smuzhiyun * R1030 (0x406) - AIF1 DAC2 Left Volume 2996*4882a593Smuzhiyun */ 2997*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2998*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2999*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 3000*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 3001*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ 3002*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ 3003*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ 3004*4882a593Smuzhiyun 3005*4882a593Smuzhiyun /* 3006*4882a593Smuzhiyun * R1031 (0x407) - AIF1 DAC2 Right Volume 3007*4882a593Smuzhiyun */ 3008*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 3009*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 3010*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 3011*4882a593Smuzhiyun #define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 3012*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ 3013*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ 3014*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ 3015*4882a593Smuzhiyun 3016*4882a593Smuzhiyun /* 3017*4882a593Smuzhiyun * R1040 (0x410) - AIF1 ADC1 Filters 3018*4882a593Smuzhiyun */ 3019*4882a593Smuzhiyun #define WM8994_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ 3020*4882a593Smuzhiyun #define WM8994_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ 3021*4882a593Smuzhiyun #define WM8994_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ 3022*4882a593Smuzhiyun #define WM8994_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ 3023*4882a593Smuzhiyun #define WM8994_AIF1ADC1_HPF_CUT_MASK 0x6000 /* AIF1ADC1_HPF_CUT - [14:13] */ 3024*4882a593Smuzhiyun #define WM8994_AIF1ADC1_HPF_CUT_SHIFT 13 /* AIF1ADC1_HPF_CUT - [14:13] */ 3025*4882a593Smuzhiyun #define WM8994_AIF1ADC1_HPF_CUT_WIDTH 2 /* AIF1ADC1_HPF_CUT - [14:13] */ 3026*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ 3027*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ 3028*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ 3029*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ 3030*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ 3031*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ 3032*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ 3033*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ 3034*4882a593Smuzhiyun 3035*4882a593Smuzhiyun /* 3036*4882a593Smuzhiyun * R1041 (0x411) - AIF1 ADC2 Filters 3037*4882a593Smuzhiyun */ 3038*4882a593Smuzhiyun #define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */ 3039*4882a593Smuzhiyun #define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */ 3040*4882a593Smuzhiyun #define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */ 3041*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ 3042*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ 3043*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ 3044*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ 3045*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ 3046*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ 3047*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ 3048*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ 3049*4882a593Smuzhiyun 3050*4882a593Smuzhiyun /* 3051*4882a593Smuzhiyun * R1056 (0x420) - AIF1 DAC1 Filters (1) 3052*4882a593Smuzhiyun */ 3053*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ 3054*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ 3055*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ 3056*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ 3057*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ 3058*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ 3059*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ 3060*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ 3061*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ 3062*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ 3063*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ 3064*4882a593Smuzhiyun #define WM8994_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ 3065*4882a593Smuzhiyun #define WM8994_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 3066*4882a593Smuzhiyun #define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 3067*4882a593Smuzhiyun #define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ 3068*4882a593Smuzhiyun #define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ 3069*4882a593Smuzhiyun #define WM8994_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ 3070*4882a593Smuzhiyun #define WM8994_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ 3071*4882a593Smuzhiyun #define WM8994_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ 3072*4882a593Smuzhiyun 3073*4882a593Smuzhiyun /* 3074*4882a593Smuzhiyun * R1057 (0x421) - AIF1 DAC1 Filters (2) 3075*4882a593Smuzhiyun */ 3076*4882a593Smuzhiyun #define WM8994_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ 3077*4882a593Smuzhiyun #define WM8994_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ 3078*4882a593Smuzhiyun #define WM8994_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ 3079*4882a593Smuzhiyun #define WM8994_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ 3080*4882a593Smuzhiyun #define WM8994_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ 3081*4882a593Smuzhiyun #define WM8994_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ 3082*4882a593Smuzhiyun #define WM8994_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ 3083*4882a593Smuzhiyun 3084*4882a593Smuzhiyun /* 3085*4882a593Smuzhiyun * R1058 (0x422) - AIF1 DAC2 Filters (1) 3086*4882a593Smuzhiyun */ 3087*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ 3088*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ 3089*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ 3090*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ 3091*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ 3092*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ 3093*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ 3094*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ 3095*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ 3096*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ 3097*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ 3098*4882a593Smuzhiyun #define WM8994_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ 3099*4882a593Smuzhiyun #define WM8994_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 3100*4882a593Smuzhiyun #define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 3101*4882a593Smuzhiyun #define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ 3102*4882a593Smuzhiyun #define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ 3103*4882a593Smuzhiyun #define WM8994_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ 3104*4882a593Smuzhiyun #define WM8994_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ 3105*4882a593Smuzhiyun #define WM8994_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ 3106*4882a593Smuzhiyun 3107*4882a593Smuzhiyun /* 3108*4882a593Smuzhiyun * R1059 (0x423) - AIF1 DAC2 Filters (2) 3109*4882a593Smuzhiyun */ 3110*4882a593Smuzhiyun #define WM8994_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ 3111*4882a593Smuzhiyun #define WM8994_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ 3112*4882a593Smuzhiyun #define WM8994_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ 3113*4882a593Smuzhiyun #define WM8994_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ 3114*4882a593Smuzhiyun #define WM8994_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ 3115*4882a593Smuzhiyun #define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ 3116*4882a593Smuzhiyun #define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ 3117*4882a593Smuzhiyun 3118*4882a593Smuzhiyun /* 3119*4882a593Smuzhiyun * R1072 (0x430) - AIF1 DAC1 Noise Gate 3120*4882a593Smuzhiyun */ 3121*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_HLD_MASK 0x0060 /* AIF1DAC1_NG_HLD - [6:5] */ 3122*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_HLD_SHIFT 5 /* AIF1DAC1_NG_HLD - [6:5] */ 3123*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_HLD_WIDTH 2 /* AIF1DAC1_NG_HLD - [6:5] */ 3124*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_THR_MASK 0x000E /* AIF1DAC1_NG_THR - [3:1] */ 3125*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_THR_SHIFT 1 /* AIF1DAC1_NG_THR - [3:1] */ 3126*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_THR_WIDTH 3 /* AIF1DAC1_NG_THR - [3:1] */ 3127*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_ENA 0x0001 /* AIF1DAC1_NG_ENA */ 3128*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_ENA_MASK 0x0001 /* AIF1DAC1_NG_ENA */ 3129*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_ENA_SHIFT 0 /* AIF1DAC1_NG_ENA */ 3130*4882a593Smuzhiyun #define WM8958_AIF1DAC1_NG_ENA_WIDTH 1 /* AIF1DAC1_NG_ENA */ 3131*4882a593Smuzhiyun 3132*4882a593Smuzhiyun /* 3133*4882a593Smuzhiyun * R1073 (0x431) - AIF1 DAC2 Noise Gate 3134*4882a593Smuzhiyun */ 3135*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_HLD_MASK 0x0060 /* AIF1DAC2_NG_HLD - [6:5] */ 3136*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_HLD_SHIFT 5 /* AIF1DAC2_NG_HLD - [6:5] */ 3137*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_HLD_WIDTH 2 /* AIF1DAC2_NG_HLD - [6:5] */ 3138*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_THR_MASK 0x000E /* AIF1DAC2_NG_THR - [3:1] */ 3139*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_THR_SHIFT 1 /* AIF1DAC2_NG_THR - [3:1] */ 3140*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_THR_WIDTH 3 /* AIF1DAC2_NG_THR - [3:1] */ 3141*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_ENA 0x0001 /* AIF1DAC2_NG_ENA */ 3142*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_ENA_MASK 0x0001 /* AIF1DAC2_NG_ENA */ 3143*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_ENA_SHIFT 0 /* AIF1DAC2_NG_ENA */ 3144*4882a593Smuzhiyun #define WM8958_AIF1DAC2_NG_ENA_WIDTH 1 /* AIF1DAC2_NG_ENA */ 3145*4882a593Smuzhiyun 3146*4882a593Smuzhiyun /* 3147*4882a593Smuzhiyun * R1088 (0x440) - AIF1 DRC1 (1) 3148*4882a593Smuzhiyun */ 3149*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 3150*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 3151*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 3152*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 3153*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 3154*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 3155*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ 3156*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ 3157*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ 3158*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ 3159*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 3160*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 3161*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ 3162*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ 3163*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ 3164*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ 3165*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ 3166*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ 3167*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 3168*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 3169*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ 3170*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ 3171*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ 3172*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ 3173*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ 3174*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ 3175*4882a593Smuzhiyun #define WM8994_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ 3176*4882a593Smuzhiyun #define WM8994_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ 3177*4882a593Smuzhiyun #define WM8994_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ 3178*4882a593Smuzhiyun #define WM8994_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ 3179*4882a593Smuzhiyun #define WM8994_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ 3180*4882a593Smuzhiyun #define WM8994_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ 3181*4882a593Smuzhiyun #define WM8994_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ 3182*4882a593Smuzhiyun #define WM8994_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ 3183*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ 3184*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ 3185*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ 3186*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ 3187*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ 3188*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ 3189*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ 3190*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ 3191*4882a593Smuzhiyun 3192*4882a593Smuzhiyun /* 3193*4882a593Smuzhiyun * R1089 (0x441) - AIF1 DRC1 (2) 3194*4882a593Smuzhiyun */ 3195*4882a593Smuzhiyun #define WM8994_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ 3196*4882a593Smuzhiyun #define WM8994_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ 3197*4882a593Smuzhiyun #define WM8994_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ 3198*4882a593Smuzhiyun #define WM8994_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ 3199*4882a593Smuzhiyun #define WM8994_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ 3200*4882a593Smuzhiyun #define WM8994_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ 3201*4882a593Smuzhiyun #define WM8994_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ 3202*4882a593Smuzhiyun #define WM8994_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ 3203*4882a593Smuzhiyun #define WM8994_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ 3204*4882a593Smuzhiyun #define WM8994_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ 3205*4882a593Smuzhiyun #define WM8994_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ 3206*4882a593Smuzhiyun #define WM8994_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ 3207*4882a593Smuzhiyun 3208*4882a593Smuzhiyun /* 3209*4882a593Smuzhiyun * R1090 (0x442) - AIF1 DRC1 (3) 3210*4882a593Smuzhiyun */ 3211*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 3212*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 3213*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 3214*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ 3215*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ 3216*4882a593Smuzhiyun #define WM8994_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ 3217*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ 3218*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ 3219*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ 3220*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ 3221*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ 3222*4882a593Smuzhiyun #define WM8994_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ 3223*4882a593Smuzhiyun #define WM8994_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ 3224*4882a593Smuzhiyun #define WM8994_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ 3225*4882a593Smuzhiyun #define WM8994_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ 3226*4882a593Smuzhiyun #define WM8994_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ 3227*4882a593Smuzhiyun #define WM8994_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ 3228*4882a593Smuzhiyun #define WM8994_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ 3229*4882a593Smuzhiyun 3230*4882a593Smuzhiyun /* 3231*4882a593Smuzhiyun * R1091 (0x443) - AIF1 DRC1 (4) 3232*4882a593Smuzhiyun */ 3233*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ 3234*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ 3235*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ 3236*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ 3237*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ 3238*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ 3239*4882a593Smuzhiyun 3240*4882a593Smuzhiyun /* 3241*4882a593Smuzhiyun * R1092 (0x444) - AIF1 DRC1 (5) 3242*4882a593Smuzhiyun */ 3243*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ 3244*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 3245*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 3246*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ 3247*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ 3248*4882a593Smuzhiyun #define WM8994_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ 3249*4882a593Smuzhiyun 3250*4882a593Smuzhiyun /* 3251*4882a593Smuzhiyun * R1104 (0x450) - AIF1 DRC2 (1) 3252*4882a593Smuzhiyun */ 3253*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 3254*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 3255*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 3256*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 3257*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 3258*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 3259*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ 3260*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ 3261*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ 3262*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ 3263*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 3264*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 3265*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ 3266*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ 3267*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ 3268*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ 3269*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ 3270*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ 3271*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 3272*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 3273*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ 3274*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ 3275*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ 3276*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ 3277*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ 3278*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ 3279*4882a593Smuzhiyun #define WM8994_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ 3280*4882a593Smuzhiyun #define WM8994_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ 3281*4882a593Smuzhiyun #define WM8994_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ 3282*4882a593Smuzhiyun #define WM8994_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ 3283*4882a593Smuzhiyun #define WM8994_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ 3284*4882a593Smuzhiyun #define WM8994_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ 3285*4882a593Smuzhiyun #define WM8994_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ 3286*4882a593Smuzhiyun #define WM8994_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ 3287*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ 3288*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ 3289*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ 3290*4882a593Smuzhiyun #define WM8994_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ 3291*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ 3292*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ 3293*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ 3294*4882a593Smuzhiyun #define WM8994_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ 3295*4882a593Smuzhiyun 3296*4882a593Smuzhiyun /* 3297*4882a593Smuzhiyun * R1105 (0x451) - AIF1 DRC2 (2) 3298*4882a593Smuzhiyun */ 3299*4882a593Smuzhiyun #define WM8994_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ 3300*4882a593Smuzhiyun #define WM8994_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ 3301*4882a593Smuzhiyun #define WM8994_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ 3302*4882a593Smuzhiyun #define WM8994_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ 3303*4882a593Smuzhiyun #define WM8994_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ 3304*4882a593Smuzhiyun #define WM8994_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ 3305*4882a593Smuzhiyun #define WM8994_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ 3306*4882a593Smuzhiyun #define WM8994_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ 3307*4882a593Smuzhiyun #define WM8994_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ 3308*4882a593Smuzhiyun #define WM8994_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ 3309*4882a593Smuzhiyun #define WM8994_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ 3310*4882a593Smuzhiyun #define WM8994_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ 3311*4882a593Smuzhiyun 3312*4882a593Smuzhiyun /* 3313*4882a593Smuzhiyun * R1106 (0x452) - AIF1 DRC2 (3) 3314*4882a593Smuzhiyun */ 3315*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 3316*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 3317*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 3318*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ 3319*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ 3320*4882a593Smuzhiyun #define WM8994_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ 3321*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ 3322*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ 3323*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ 3324*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ 3325*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ 3326*4882a593Smuzhiyun #define WM8994_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ 3327*4882a593Smuzhiyun #define WM8994_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ 3328*4882a593Smuzhiyun #define WM8994_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ 3329*4882a593Smuzhiyun #define WM8994_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ 3330*4882a593Smuzhiyun #define WM8994_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ 3331*4882a593Smuzhiyun #define WM8994_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ 3332*4882a593Smuzhiyun #define WM8994_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ 3333*4882a593Smuzhiyun 3334*4882a593Smuzhiyun /* 3335*4882a593Smuzhiyun * R1107 (0x453) - AIF1 DRC2 (4) 3336*4882a593Smuzhiyun */ 3337*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ 3338*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ 3339*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ 3340*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ 3341*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ 3342*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ 3343*4882a593Smuzhiyun 3344*4882a593Smuzhiyun /* 3345*4882a593Smuzhiyun * R1108 (0x454) - AIF1 DRC2 (5) 3346*4882a593Smuzhiyun */ 3347*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ 3348*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 3349*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 3350*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ 3351*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ 3352*4882a593Smuzhiyun #define WM8994_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ 3353*4882a593Smuzhiyun 3354*4882a593Smuzhiyun /* 3355*4882a593Smuzhiyun * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) 3356*4882a593Smuzhiyun */ 3357*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 3358*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 3359*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 3360*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 3361*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 3362*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 3363*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 3364*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 3365*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 3366*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ 3367*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ 3368*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ 3369*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ 3370*4882a593Smuzhiyun 3371*4882a593Smuzhiyun /* 3372*4882a593Smuzhiyun * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) 3373*4882a593Smuzhiyun */ 3374*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 3375*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 3376*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 3377*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 3378*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 3379*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 3380*4882a593Smuzhiyun 3381*4882a593Smuzhiyun /* 3382*4882a593Smuzhiyun * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A 3383*4882a593Smuzhiyun */ 3384*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ 3385*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ 3386*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ 3387*4882a593Smuzhiyun 3388*4882a593Smuzhiyun /* 3389*4882a593Smuzhiyun * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B 3390*4882a593Smuzhiyun */ 3391*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ 3392*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ 3393*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ 3394*4882a593Smuzhiyun 3395*4882a593Smuzhiyun /* 3396*4882a593Smuzhiyun * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG 3397*4882a593Smuzhiyun */ 3398*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ 3399*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 3400*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 3401*4882a593Smuzhiyun 3402*4882a593Smuzhiyun /* 3403*4882a593Smuzhiyun * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A 3404*4882a593Smuzhiyun */ 3405*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ 3406*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ 3407*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ 3408*4882a593Smuzhiyun 3409*4882a593Smuzhiyun /* 3410*4882a593Smuzhiyun * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B 3411*4882a593Smuzhiyun */ 3412*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ 3413*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ 3414*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ 3415*4882a593Smuzhiyun 3416*4882a593Smuzhiyun /* 3417*4882a593Smuzhiyun * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C 3418*4882a593Smuzhiyun */ 3419*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ 3420*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ 3421*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ 3422*4882a593Smuzhiyun 3423*4882a593Smuzhiyun /* 3424*4882a593Smuzhiyun * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG 3425*4882a593Smuzhiyun */ 3426*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3427*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3428*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3429*4882a593Smuzhiyun 3430*4882a593Smuzhiyun /* 3431*4882a593Smuzhiyun * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A 3432*4882a593Smuzhiyun */ 3433*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ 3434*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ 3435*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ 3436*4882a593Smuzhiyun 3437*4882a593Smuzhiyun /* 3438*4882a593Smuzhiyun * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B 3439*4882a593Smuzhiyun */ 3440*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ 3441*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ 3442*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ 3443*4882a593Smuzhiyun 3444*4882a593Smuzhiyun /* 3445*4882a593Smuzhiyun * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C 3446*4882a593Smuzhiyun */ 3447*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ 3448*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ 3449*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ 3450*4882a593Smuzhiyun 3451*4882a593Smuzhiyun /* 3452*4882a593Smuzhiyun * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG 3453*4882a593Smuzhiyun */ 3454*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3455*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3456*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3457*4882a593Smuzhiyun 3458*4882a593Smuzhiyun /* 3459*4882a593Smuzhiyun * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A 3460*4882a593Smuzhiyun */ 3461*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ 3462*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ 3463*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ 3464*4882a593Smuzhiyun 3465*4882a593Smuzhiyun /* 3466*4882a593Smuzhiyun * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B 3467*4882a593Smuzhiyun */ 3468*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ 3469*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ 3470*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ 3471*4882a593Smuzhiyun 3472*4882a593Smuzhiyun /* 3473*4882a593Smuzhiyun * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C 3474*4882a593Smuzhiyun */ 3475*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ 3476*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ 3477*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ 3478*4882a593Smuzhiyun 3479*4882a593Smuzhiyun /* 3480*4882a593Smuzhiyun * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG 3481*4882a593Smuzhiyun */ 3482*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3483*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3484*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3485*4882a593Smuzhiyun 3486*4882a593Smuzhiyun /* 3487*4882a593Smuzhiyun * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A 3488*4882a593Smuzhiyun */ 3489*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ 3490*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ 3491*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ 3492*4882a593Smuzhiyun 3493*4882a593Smuzhiyun /* 3494*4882a593Smuzhiyun * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B 3495*4882a593Smuzhiyun */ 3496*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ 3497*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ 3498*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ 3499*4882a593Smuzhiyun 3500*4882a593Smuzhiyun /* 3501*4882a593Smuzhiyun * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG 3502*4882a593Smuzhiyun */ 3503*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3504*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3505*4882a593Smuzhiyun #define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3506*4882a593Smuzhiyun 3507*4882a593Smuzhiyun /* 3508*4882a593Smuzhiyun * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) 3509*4882a593Smuzhiyun */ 3510*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3511*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3512*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3513*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3514*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3515*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3516*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3517*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3518*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3519*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ 3520*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ 3521*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ 3522*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ 3523*4882a593Smuzhiyun 3524*4882a593Smuzhiyun /* 3525*4882a593Smuzhiyun * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) 3526*4882a593Smuzhiyun */ 3527*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3528*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3529*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3530*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3531*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3532*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3533*4882a593Smuzhiyun 3534*4882a593Smuzhiyun /* 3535*4882a593Smuzhiyun * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A 3536*4882a593Smuzhiyun */ 3537*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ 3538*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ 3539*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ 3540*4882a593Smuzhiyun 3541*4882a593Smuzhiyun /* 3542*4882a593Smuzhiyun * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B 3543*4882a593Smuzhiyun */ 3544*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ 3545*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ 3546*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ 3547*4882a593Smuzhiyun 3548*4882a593Smuzhiyun /* 3549*4882a593Smuzhiyun * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG 3550*4882a593Smuzhiyun */ 3551*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3552*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3553*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3554*4882a593Smuzhiyun 3555*4882a593Smuzhiyun /* 3556*4882a593Smuzhiyun * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A 3557*4882a593Smuzhiyun */ 3558*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ 3559*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ 3560*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ 3561*4882a593Smuzhiyun 3562*4882a593Smuzhiyun /* 3563*4882a593Smuzhiyun * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B 3564*4882a593Smuzhiyun */ 3565*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ 3566*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ 3567*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ 3568*4882a593Smuzhiyun 3569*4882a593Smuzhiyun /* 3570*4882a593Smuzhiyun * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C 3571*4882a593Smuzhiyun */ 3572*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ 3573*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ 3574*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ 3575*4882a593Smuzhiyun 3576*4882a593Smuzhiyun /* 3577*4882a593Smuzhiyun * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG 3578*4882a593Smuzhiyun */ 3579*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3580*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3581*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3582*4882a593Smuzhiyun 3583*4882a593Smuzhiyun /* 3584*4882a593Smuzhiyun * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A 3585*4882a593Smuzhiyun */ 3586*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ 3587*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ 3588*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ 3589*4882a593Smuzhiyun 3590*4882a593Smuzhiyun /* 3591*4882a593Smuzhiyun * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B 3592*4882a593Smuzhiyun */ 3593*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ 3594*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ 3595*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ 3596*4882a593Smuzhiyun 3597*4882a593Smuzhiyun /* 3598*4882a593Smuzhiyun * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C 3599*4882a593Smuzhiyun */ 3600*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ 3601*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ 3602*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ 3603*4882a593Smuzhiyun 3604*4882a593Smuzhiyun /* 3605*4882a593Smuzhiyun * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG 3606*4882a593Smuzhiyun */ 3607*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3608*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3609*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3610*4882a593Smuzhiyun 3611*4882a593Smuzhiyun /* 3612*4882a593Smuzhiyun * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A 3613*4882a593Smuzhiyun */ 3614*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ 3615*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ 3616*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ 3617*4882a593Smuzhiyun 3618*4882a593Smuzhiyun /* 3619*4882a593Smuzhiyun * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B 3620*4882a593Smuzhiyun */ 3621*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ 3622*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ 3623*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ 3624*4882a593Smuzhiyun 3625*4882a593Smuzhiyun /* 3626*4882a593Smuzhiyun * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C 3627*4882a593Smuzhiyun */ 3628*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ 3629*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ 3630*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ 3631*4882a593Smuzhiyun 3632*4882a593Smuzhiyun /* 3633*4882a593Smuzhiyun * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG 3634*4882a593Smuzhiyun */ 3635*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3636*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3637*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3638*4882a593Smuzhiyun 3639*4882a593Smuzhiyun /* 3640*4882a593Smuzhiyun * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A 3641*4882a593Smuzhiyun */ 3642*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ 3643*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ 3644*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ 3645*4882a593Smuzhiyun 3646*4882a593Smuzhiyun /* 3647*4882a593Smuzhiyun * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B 3648*4882a593Smuzhiyun */ 3649*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ 3650*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ 3651*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ 3652*4882a593Smuzhiyun 3653*4882a593Smuzhiyun /* 3654*4882a593Smuzhiyun * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG 3655*4882a593Smuzhiyun */ 3656*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3657*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3658*4882a593Smuzhiyun #define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3659*4882a593Smuzhiyun 3660*4882a593Smuzhiyun /* 3661*4882a593Smuzhiyun * R1280 (0x500) - AIF2 ADC Left Volume 3662*4882a593Smuzhiyun */ 3663*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 3664*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 3665*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 3666*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 3667*4882a593Smuzhiyun #define WM8994_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ 3668*4882a593Smuzhiyun #define WM8994_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ 3669*4882a593Smuzhiyun #define WM8994_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ 3670*4882a593Smuzhiyun 3671*4882a593Smuzhiyun /* 3672*4882a593Smuzhiyun * R1281 (0x501) - AIF2 ADC Right Volume 3673*4882a593Smuzhiyun */ 3674*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 3675*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 3676*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 3677*4882a593Smuzhiyun #define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 3678*4882a593Smuzhiyun #define WM8994_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ 3679*4882a593Smuzhiyun #define WM8994_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ 3680*4882a593Smuzhiyun #define WM8994_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ 3681*4882a593Smuzhiyun 3682*4882a593Smuzhiyun /* 3683*4882a593Smuzhiyun * R1282 (0x502) - AIF2 DAC Left Volume 3684*4882a593Smuzhiyun */ 3685*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 3686*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 3687*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 3688*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 3689*4882a593Smuzhiyun #define WM8994_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ 3690*4882a593Smuzhiyun #define WM8994_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ 3691*4882a593Smuzhiyun #define WM8994_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ 3692*4882a593Smuzhiyun 3693*4882a593Smuzhiyun /* 3694*4882a593Smuzhiyun * R1283 (0x503) - AIF2 DAC Right Volume 3695*4882a593Smuzhiyun */ 3696*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 3697*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 3698*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 3699*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 3700*4882a593Smuzhiyun #define WM8994_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ 3701*4882a593Smuzhiyun #define WM8994_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ 3702*4882a593Smuzhiyun #define WM8994_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ 3703*4882a593Smuzhiyun 3704*4882a593Smuzhiyun /* 3705*4882a593Smuzhiyun * R1296 (0x510) - AIF2 ADC Filters 3706*4882a593Smuzhiyun */ 3707*4882a593Smuzhiyun #define WM8994_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ 3708*4882a593Smuzhiyun #define WM8994_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ 3709*4882a593Smuzhiyun #define WM8994_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ 3710*4882a593Smuzhiyun #define WM8994_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ 3711*4882a593Smuzhiyun #define WM8994_AIF2ADC_HPF_CUT_MASK 0x6000 /* AIF2ADC_HPF_CUT - [14:13] */ 3712*4882a593Smuzhiyun #define WM8994_AIF2ADC_HPF_CUT_SHIFT 13 /* AIF2ADC_HPF_CUT - [14:13] */ 3713*4882a593Smuzhiyun #define WM8994_AIF2ADC_HPF_CUT_WIDTH 2 /* AIF2ADC_HPF_CUT - [14:13] */ 3714*4882a593Smuzhiyun #define WM8994_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ 3715*4882a593Smuzhiyun #define WM8994_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ 3716*4882a593Smuzhiyun #define WM8994_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ 3717*4882a593Smuzhiyun #define WM8994_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ 3718*4882a593Smuzhiyun #define WM8994_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ 3719*4882a593Smuzhiyun #define WM8994_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ 3720*4882a593Smuzhiyun #define WM8994_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ 3721*4882a593Smuzhiyun #define WM8994_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ 3722*4882a593Smuzhiyun 3723*4882a593Smuzhiyun /* 3724*4882a593Smuzhiyun * R1312 (0x520) - AIF2 DAC Filters (1) 3725*4882a593Smuzhiyun */ 3726*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ 3727*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ 3728*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ 3729*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ 3730*4882a593Smuzhiyun #define WM8994_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ 3731*4882a593Smuzhiyun #define WM8994_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ 3732*4882a593Smuzhiyun #define WM8994_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ 3733*4882a593Smuzhiyun #define WM8994_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ 3734*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ 3735*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ 3736*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ 3737*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ 3738*4882a593Smuzhiyun #define WM8994_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 3739*4882a593Smuzhiyun #define WM8994_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 3740*4882a593Smuzhiyun #define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ 3741*4882a593Smuzhiyun #define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ 3742*4882a593Smuzhiyun #define WM8994_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ 3743*4882a593Smuzhiyun #define WM8994_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ 3744*4882a593Smuzhiyun #define WM8994_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ 3745*4882a593Smuzhiyun 3746*4882a593Smuzhiyun /* 3747*4882a593Smuzhiyun * R1313 (0x521) - AIF2 DAC Filters (2) 3748*4882a593Smuzhiyun */ 3749*4882a593Smuzhiyun #define WM8994_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ 3750*4882a593Smuzhiyun #define WM8994_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ 3751*4882a593Smuzhiyun #define WM8994_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ 3752*4882a593Smuzhiyun #define WM8994_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ 3753*4882a593Smuzhiyun #define WM8994_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ 3754*4882a593Smuzhiyun #define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ 3755*4882a593Smuzhiyun #define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ 3756*4882a593Smuzhiyun 3757*4882a593Smuzhiyun /* 3758*4882a593Smuzhiyun * R1328 (0x530) - AIF2 DAC Noise Gate 3759*4882a593Smuzhiyun */ 3760*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_HLD_MASK 0x0060 /* AIF2DAC_NG_HLD - [6:5] */ 3761*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_HLD_SHIFT 5 /* AIF2DAC_NG_HLD - [6:5] */ 3762*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_HLD_WIDTH 2 /* AIF2DAC_NG_HLD - [6:5] */ 3763*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_THR_MASK 0x000E /* AIF2DAC_NG_THR - [3:1] */ 3764*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_THR_SHIFT 1 /* AIF2DAC_NG_THR - [3:1] */ 3765*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_THR_WIDTH 3 /* AIF2DAC_NG_THR - [3:1] */ 3766*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_ENA 0x0001 /* AIF2DAC_NG_ENA */ 3767*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_ENA_MASK 0x0001 /* AIF2DAC_NG_ENA */ 3768*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_ENA_SHIFT 0 /* AIF2DAC_NG_ENA */ 3769*4882a593Smuzhiyun #define WM8958_AIF2DAC_NG_ENA_WIDTH 1 /* AIF2DAC_NG_ENA */ 3770*4882a593Smuzhiyun 3771*4882a593Smuzhiyun /* 3772*4882a593Smuzhiyun * R1344 (0x540) - AIF2 DRC (1) 3773*4882a593Smuzhiyun */ 3774*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3775*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3776*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3777*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3778*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3779*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3780*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ 3781*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ 3782*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ 3783*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ 3784*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ 3785*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ 3786*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ 3787*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ 3788*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ 3789*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ 3790*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ 3791*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ 3792*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 3793*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 3794*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ 3795*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ 3796*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ 3797*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ 3798*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ 3799*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ 3800*4882a593Smuzhiyun #define WM8994_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ 3801*4882a593Smuzhiyun #define WM8994_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ 3802*4882a593Smuzhiyun #define WM8994_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ 3803*4882a593Smuzhiyun #define WM8994_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ 3804*4882a593Smuzhiyun #define WM8994_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ 3805*4882a593Smuzhiyun #define WM8994_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ 3806*4882a593Smuzhiyun #define WM8994_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ 3807*4882a593Smuzhiyun #define WM8994_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ 3808*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ 3809*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ 3810*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ 3811*4882a593Smuzhiyun #define WM8994_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ 3812*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ 3813*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ 3814*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ 3815*4882a593Smuzhiyun #define WM8994_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ 3816*4882a593Smuzhiyun 3817*4882a593Smuzhiyun /* 3818*4882a593Smuzhiyun * R1345 (0x541) - AIF2 DRC (2) 3819*4882a593Smuzhiyun */ 3820*4882a593Smuzhiyun #define WM8994_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ 3821*4882a593Smuzhiyun #define WM8994_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ 3822*4882a593Smuzhiyun #define WM8994_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ 3823*4882a593Smuzhiyun #define WM8994_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ 3824*4882a593Smuzhiyun #define WM8994_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ 3825*4882a593Smuzhiyun #define WM8994_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ 3826*4882a593Smuzhiyun #define WM8994_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ 3827*4882a593Smuzhiyun #define WM8994_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ 3828*4882a593Smuzhiyun #define WM8994_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ 3829*4882a593Smuzhiyun #define WM8994_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ 3830*4882a593Smuzhiyun #define WM8994_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ 3831*4882a593Smuzhiyun #define WM8994_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ 3832*4882a593Smuzhiyun 3833*4882a593Smuzhiyun /* 3834*4882a593Smuzhiyun * R1346 (0x542) - AIF2 DRC (3) 3835*4882a593Smuzhiyun */ 3836*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3837*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3838*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3839*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ 3840*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ 3841*4882a593Smuzhiyun #define WM8994_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ 3842*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ 3843*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ 3844*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ 3845*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ 3846*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ 3847*4882a593Smuzhiyun #define WM8994_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ 3848*4882a593Smuzhiyun #define WM8994_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ 3849*4882a593Smuzhiyun #define WM8994_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ 3850*4882a593Smuzhiyun #define WM8994_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ 3851*4882a593Smuzhiyun #define WM8994_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ 3852*4882a593Smuzhiyun #define WM8994_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ 3853*4882a593Smuzhiyun #define WM8994_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ 3854*4882a593Smuzhiyun 3855*4882a593Smuzhiyun /* 3856*4882a593Smuzhiyun * R1347 (0x543) - AIF2 DRC (4) 3857*4882a593Smuzhiyun */ 3858*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ 3859*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ 3860*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ 3861*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ 3862*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ 3863*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ 3864*4882a593Smuzhiyun 3865*4882a593Smuzhiyun /* 3866*4882a593Smuzhiyun * R1348 (0x544) - AIF2 DRC (5) 3867*4882a593Smuzhiyun */ 3868*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ 3869*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 3870*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 3871*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ 3872*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ 3873*4882a593Smuzhiyun #define WM8994_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ 3874*4882a593Smuzhiyun 3875*4882a593Smuzhiyun /* 3876*4882a593Smuzhiyun * R1408 (0x580) - AIF2 EQ Gains (1) 3877*4882a593Smuzhiyun */ 3878*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3879*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3880*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3881*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3882*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3883*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3884*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3885*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3886*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3887*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ 3888*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ 3889*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ 3890*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ 3891*4882a593Smuzhiyun 3892*4882a593Smuzhiyun /* 3893*4882a593Smuzhiyun * R1409 (0x581) - AIF2 EQ Gains (2) 3894*4882a593Smuzhiyun */ 3895*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3896*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3897*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3898*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3899*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3900*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3901*4882a593Smuzhiyun 3902*4882a593Smuzhiyun /* 3903*4882a593Smuzhiyun * R1410 (0x582) - AIF2 EQ Band 1 A 3904*4882a593Smuzhiyun */ 3905*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ 3906*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ 3907*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ 3908*4882a593Smuzhiyun 3909*4882a593Smuzhiyun /* 3910*4882a593Smuzhiyun * R1411 (0x583) - AIF2 EQ Band 1 B 3911*4882a593Smuzhiyun */ 3912*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ 3913*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ 3914*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ 3915*4882a593Smuzhiyun 3916*4882a593Smuzhiyun /* 3917*4882a593Smuzhiyun * R1412 (0x584) - AIF2 EQ Band 1 PG 3918*4882a593Smuzhiyun */ 3919*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ 3920*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ 3921*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ 3922*4882a593Smuzhiyun 3923*4882a593Smuzhiyun /* 3924*4882a593Smuzhiyun * R1413 (0x585) - AIF2 EQ Band 2 A 3925*4882a593Smuzhiyun */ 3926*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ 3927*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ 3928*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ 3929*4882a593Smuzhiyun 3930*4882a593Smuzhiyun /* 3931*4882a593Smuzhiyun * R1414 (0x586) - AIF2 EQ Band 2 B 3932*4882a593Smuzhiyun */ 3933*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ 3934*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ 3935*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ 3936*4882a593Smuzhiyun 3937*4882a593Smuzhiyun /* 3938*4882a593Smuzhiyun * R1415 (0x587) - AIF2 EQ Band 2 C 3939*4882a593Smuzhiyun */ 3940*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ 3941*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ 3942*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ 3943*4882a593Smuzhiyun 3944*4882a593Smuzhiyun /* 3945*4882a593Smuzhiyun * R1416 (0x588) - AIF2 EQ Band 2 PG 3946*4882a593Smuzhiyun */ 3947*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ 3948*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3949*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3950*4882a593Smuzhiyun 3951*4882a593Smuzhiyun /* 3952*4882a593Smuzhiyun * R1417 (0x589) - AIF2 EQ Band 3 A 3953*4882a593Smuzhiyun */ 3954*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ 3955*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ 3956*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ 3957*4882a593Smuzhiyun 3958*4882a593Smuzhiyun /* 3959*4882a593Smuzhiyun * R1418 (0x58A) - AIF2 EQ Band 3 B 3960*4882a593Smuzhiyun */ 3961*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ 3962*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ 3963*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ 3964*4882a593Smuzhiyun 3965*4882a593Smuzhiyun /* 3966*4882a593Smuzhiyun * R1419 (0x58B) - AIF2 EQ Band 3 C 3967*4882a593Smuzhiyun */ 3968*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ 3969*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ 3970*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ 3971*4882a593Smuzhiyun 3972*4882a593Smuzhiyun /* 3973*4882a593Smuzhiyun * R1420 (0x58C) - AIF2 EQ Band 3 PG 3974*4882a593Smuzhiyun */ 3975*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ 3976*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3977*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3978*4882a593Smuzhiyun 3979*4882a593Smuzhiyun /* 3980*4882a593Smuzhiyun * R1421 (0x58D) - AIF2 EQ Band 4 A 3981*4882a593Smuzhiyun */ 3982*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ 3983*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ 3984*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ 3985*4882a593Smuzhiyun 3986*4882a593Smuzhiyun /* 3987*4882a593Smuzhiyun * R1422 (0x58E) - AIF2 EQ Band 4 B 3988*4882a593Smuzhiyun */ 3989*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ 3990*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ 3991*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ 3992*4882a593Smuzhiyun 3993*4882a593Smuzhiyun /* 3994*4882a593Smuzhiyun * R1423 (0x58F) - AIF2 EQ Band 4 C 3995*4882a593Smuzhiyun */ 3996*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ 3997*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ 3998*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ 3999*4882a593Smuzhiyun 4000*4882a593Smuzhiyun /* 4001*4882a593Smuzhiyun * R1424 (0x590) - AIF2 EQ Band 4 PG 4002*4882a593Smuzhiyun */ 4003*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ 4004*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ 4005*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ 4006*4882a593Smuzhiyun 4007*4882a593Smuzhiyun /* 4008*4882a593Smuzhiyun * R1425 (0x591) - AIF2 EQ Band 5 A 4009*4882a593Smuzhiyun */ 4010*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ 4011*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ 4012*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ 4013*4882a593Smuzhiyun 4014*4882a593Smuzhiyun /* 4015*4882a593Smuzhiyun * R1426 (0x592) - AIF2 EQ Band 5 B 4016*4882a593Smuzhiyun */ 4017*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ 4018*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ 4019*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ 4020*4882a593Smuzhiyun 4021*4882a593Smuzhiyun /* 4022*4882a593Smuzhiyun * R1427 (0x593) - AIF2 EQ Band 5 PG 4023*4882a593Smuzhiyun */ 4024*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ 4025*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ 4026*4882a593Smuzhiyun #define WM8994_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ 4027*4882a593Smuzhiyun 4028*4882a593Smuzhiyun /* 4029*4882a593Smuzhiyun * R1536 (0x600) - DAC1 Mixer Volumes 4030*4882a593Smuzhiyun */ 4031*4882a593Smuzhiyun #define WM8994_ADCR_DAC1_VOL_MASK 0x01E0 /* ADCR_DAC1_VOL - [8:5] */ 4032*4882a593Smuzhiyun #define WM8994_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [8:5] */ 4033*4882a593Smuzhiyun #define WM8994_ADCR_DAC1_VOL_WIDTH 4 /* ADCR_DAC1_VOL - [8:5] */ 4034*4882a593Smuzhiyun #define WM8994_ADCL_DAC1_VOL_MASK 0x000F /* ADCL_DAC1_VOL - [3:0] */ 4035*4882a593Smuzhiyun #define WM8994_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [3:0] */ 4036*4882a593Smuzhiyun #define WM8994_ADCL_DAC1_VOL_WIDTH 4 /* ADCL_DAC1_VOL - [3:0] */ 4037*4882a593Smuzhiyun 4038*4882a593Smuzhiyun /* 4039*4882a593Smuzhiyun * R1537 (0x601) - DAC1 Left Mixer Routing 4040*4882a593Smuzhiyun */ 4041*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 4042*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 4043*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 4044*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 4045*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 4046*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 4047*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 4048*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 4049*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ 4050*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ 4051*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ 4052*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ 4053*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ 4054*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ 4055*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ 4056*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ 4057*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ 4058*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ 4059*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ 4060*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ 4061*4882a593Smuzhiyun 4062*4882a593Smuzhiyun /* 4063*4882a593Smuzhiyun * R1538 (0x602) - DAC1 Right Mixer Routing 4064*4882a593Smuzhiyun */ 4065*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 4066*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 4067*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 4068*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 4069*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 4070*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 4071*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 4072*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 4073*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ 4074*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ 4075*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ 4076*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ 4077*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ 4078*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ 4079*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ 4080*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ 4081*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ 4082*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ 4083*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ 4084*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ 4085*4882a593Smuzhiyun 4086*4882a593Smuzhiyun /* 4087*4882a593Smuzhiyun * R1539 (0x603) - DAC2 Mixer Volumes 4088*4882a593Smuzhiyun */ 4089*4882a593Smuzhiyun #define WM8994_ADCR_DAC2_VOL_MASK 0x01E0 /* ADCR_DAC2_VOL - [8:5] */ 4090*4882a593Smuzhiyun #define WM8994_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [8:5] */ 4091*4882a593Smuzhiyun #define WM8994_ADCR_DAC2_VOL_WIDTH 4 /* ADCR_DAC2_VOL - [8:5] */ 4092*4882a593Smuzhiyun #define WM8994_ADCL_DAC2_VOL_MASK 0x000F /* ADCL_DAC2_VOL - [3:0] */ 4093*4882a593Smuzhiyun #define WM8994_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [3:0] */ 4094*4882a593Smuzhiyun #define WM8994_ADCL_DAC2_VOL_WIDTH 4 /* ADCL_DAC2_VOL - [3:0] */ 4095*4882a593Smuzhiyun 4096*4882a593Smuzhiyun /* 4097*4882a593Smuzhiyun * R1540 (0x604) - DAC2 Left Mixer Routing 4098*4882a593Smuzhiyun */ 4099*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 4100*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 4101*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 4102*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 4103*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 4104*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 4105*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 4106*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 4107*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ 4108*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ 4109*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ 4110*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ 4111*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ 4112*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ 4113*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ 4114*4882a593Smuzhiyun #define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ 4115*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ 4116*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ 4117*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ 4118*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ 4119*4882a593Smuzhiyun 4120*4882a593Smuzhiyun /* 4121*4882a593Smuzhiyun * R1541 (0x605) - DAC2 Right Mixer Routing 4122*4882a593Smuzhiyun */ 4123*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 4124*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 4125*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 4126*4882a593Smuzhiyun #define WM8994_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 4127*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 4128*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 4129*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 4130*4882a593Smuzhiyun #define WM8994_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 4131*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ 4132*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ 4133*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ 4134*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ 4135*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ 4136*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ 4137*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ 4138*4882a593Smuzhiyun #define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ 4139*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ 4140*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ 4141*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ 4142*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ 4143*4882a593Smuzhiyun 4144*4882a593Smuzhiyun /* 4145*4882a593Smuzhiyun * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing 4146*4882a593Smuzhiyun */ 4147*4882a593Smuzhiyun #define WM8994_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ 4148*4882a593Smuzhiyun #define WM8994_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ 4149*4882a593Smuzhiyun #define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ 4150*4882a593Smuzhiyun #define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ 4151*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 4152*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 4153*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ 4154*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ 4155*4882a593Smuzhiyun 4156*4882a593Smuzhiyun /* 4157*4882a593Smuzhiyun * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing 4158*4882a593Smuzhiyun */ 4159*4882a593Smuzhiyun #define WM8994_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ 4160*4882a593Smuzhiyun #define WM8994_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ 4161*4882a593Smuzhiyun #define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ 4162*4882a593Smuzhiyun #define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ 4163*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 4164*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 4165*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ 4166*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ 4167*4882a593Smuzhiyun 4168*4882a593Smuzhiyun /* 4169*4882a593Smuzhiyun * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing 4170*4882a593Smuzhiyun */ 4171*4882a593Smuzhiyun #define WM8994_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ 4172*4882a593Smuzhiyun #define WM8994_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ 4173*4882a593Smuzhiyun #define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ 4174*4882a593Smuzhiyun #define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ 4175*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 4176*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 4177*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ 4178*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ 4179*4882a593Smuzhiyun 4180*4882a593Smuzhiyun /* 4181*4882a593Smuzhiyun * R1545 (0x609) - AIF1 ADC2 Right mixer Routing 4182*4882a593Smuzhiyun */ 4183*4882a593Smuzhiyun #define WM8994_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ 4184*4882a593Smuzhiyun #define WM8994_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ 4185*4882a593Smuzhiyun #define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ 4186*4882a593Smuzhiyun #define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ 4187*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 4188*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 4189*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ 4190*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ 4191*4882a593Smuzhiyun 4192*4882a593Smuzhiyun /* 4193*4882a593Smuzhiyun * R1552 (0x610) - DAC1 Left Volume 4194*4882a593Smuzhiyun */ 4195*4882a593Smuzhiyun #define WM8994_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 4196*4882a593Smuzhiyun #define WM8994_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 4197*4882a593Smuzhiyun #define WM8994_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 4198*4882a593Smuzhiyun #define WM8994_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 4199*4882a593Smuzhiyun #define WM8994_DAC1_VU 0x0100 /* DAC1_VU */ 4200*4882a593Smuzhiyun #define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 4201*4882a593Smuzhiyun #define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */ 4202*4882a593Smuzhiyun #define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */ 4203*4882a593Smuzhiyun #define WM8994_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 4204*4882a593Smuzhiyun #define WM8994_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 4205*4882a593Smuzhiyun #define WM8994_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 4206*4882a593Smuzhiyun 4207*4882a593Smuzhiyun /* 4208*4882a593Smuzhiyun * R1553 (0x611) - DAC1 Right Volume 4209*4882a593Smuzhiyun */ 4210*4882a593Smuzhiyun #define WM8994_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 4211*4882a593Smuzhiyun #define WM8994_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 4212*4882a593Smuzhiyun #define WM8994_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 4213*4882a593Smuzhiyun #define WM8994_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 4214*4882a593Smuzhiyun #define WM8994_DAC1_VU 0x0100 /* DAC1_VU */ 4215*4882a593Smuzhiyun #define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 4216*4882a593Smuzhiyun #define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */ 4217*4882a593Smuzhiyun #define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */ 4218*4882a593Smuzhiyun #define WM8994_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 4219*4882a593Smuzhiyun #define WM8994_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 4220*4882a593Smuzhiyun #define WM8994_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 4221*4882a593Smuzhiyun 4222*4882a593Smuzhiyun /* 4223*4882a593Smuzhiyun * R1554 (0x612) - DAC2 Left Volume 4224*4882a593Smuzhiyun */ 4225*4882a593Smuzhiyun #define WM8994_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 4226*4882a593Smuzhiyun #define WM8994_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 4227*4882a593Smuzhiyun #define WM8994_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 4228*4882a593Smuzhiyun #define WM8994_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 4229*4882a593Smuzhiyun #define WM8994_DAC2_VU 0x0100 /* DAC2_VU */ 4230*4882a593Smuzhiyun #define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 4231*4882a593Smuzhiyun #define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */ 4232*4882a593Smuzhiyun #define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */ 4233*4882a593Smuzhiyun #define WM8994_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 4234*4882a593Smuzhiyun #define WM8994_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 4235*4882a593Smuzhiyun #define WM8994_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 4236*4882a593Smuzhiyun 4237*4882a593Smuzhiyun /* 4238*4882a593Smuzhiyun * R1555 (0x613) - DAC2 Right Volume 4239*4882a593Smuzhiyun */ 4240*4882a593Smuzhiyun #define WM8994_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 4241*4882a593Smuzhiyun #define WM8994_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 4242*4882a593Smuzhiyun #define WM8994_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 4243*4882a593Smuzhiyun #define WM8994_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 4244*4882a593Smuzhiyun #define WM8994_DAC2_VU 0x0100 /* DAC2_VU */ 4245*4882a593Smuzhiyun #define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 4246*4882a593Smuzhiyun #define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */ 4247*4882a593Smuzhiyun #define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */ 4248*4882a593Smuzhiyun #define WM8994_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 4249*4882a593Smuzhiyun #define WM8994_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 4250*4882a593Smuzhiyun #define WM8994_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 4251*4882a593Smuzhiyun 4252*4882a593Smuzhiyun /* 4253*4882a593Smuzhiyun * R1556 (0x614) - DAC Softmute 4254*4882a593Smuzhiyun */ 4255*4882a593Smuzhiyun #define WM8994_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 4256*4882a593Smuzhiyun #define WM8994_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 4257*4882a593Smuzhiyun #define WM8994_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 4258*4882a593Smuzhiyun #define WM8994_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 4259*4882a593Smuzhiyun #define WM8994_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 4260*4882a593Smuzhiyun #define WM8994_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 4261*4882a593Smuzhiyun #define WM8994_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 4262*4882a593Smuzhiyun #define WM8994_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 4263*4882a593Smuzhiyun 4264*4882a593Smuzhiyun /* 4265*4882a593Smuzhiyun * R1568 (0x620) - Oversampling 4266*4882a593Smuzhiyun */ 4267*4882a593Smuzhiyun #define WM8994_ADC_OSR128 0x0002 /* ADC_OSR128 */ 4268*4882a593Smuzhiyun #define WM8994_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 4269*4882a593Smuzhiyun #define WM8994_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 4270*4882a593Smuzhiyun #define WM8994_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 4271*4882a593Smuzhiyun #define WM8994_DAC_OSR128 0x0001 /* DAC_OSR128 */ 4272*4882a593Smuzhiyun #define WM8994_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 4273*4882a593Smuzhiyun #define WM8994_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 4274*4882a593Smuzhiyun #define WM8994_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 4275*4882a593Smuzhiyun 4276*4882a593Smuzhiyun /* 4277*4882a593Smuzhiyun * R1569 (0x621) - Sidetone 4278*4882a593Smuzhiyun */ 4279*4882a593Smuzhiyun #define WM8994_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 4280*4882a593Smuzhiyun #define WM8994_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 4281*4882a593Smuzhiyun #define WM8994_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 4282*4882a593Smuzhiyun #define WM8994_ST_HPF 0x0040 /* ST_HPF */ 4283*4882a593Smuzhiyun #define WM8994_ST_HPF_MASK 0x0040 /* ST_HPF */ 4284*4882a593Smuzhiyun #define WM8994_ST_HPF_SHIFT 6 /* ST_HPF */ 4285*4882a593Smuzhiyun #define WM8994_ST_HPF_WIDTH 1 /* ST_HPF */ 4286*4882a593Smuzhiyun #define WM8994_STR_SEL 0x0002 /* STR_SEL */ 4287*4882a593Smuzhiyun #define WM8994_STR_SEL_MASK 0x0002 /* STR_SEL */ 4288*4882a593Smuzhiyun #define WM8994_STR_SEL_SHIFT 1 /* STR_SEL */ 4289*4882a593Smuzhiyun #define WM8994_STR_SEL_WIDTH 1 /* STR_SEL */ 4290*4882a593Smuzhiyun #define WM8994_STL_SEL 0x0001 /* STL_SEL */ 4291*4882a593Smuzhiyun #define WM8994_STL_SEL_MASK 0x0001 /* STL_SEL */ 4292*4882a593Smuzhiyun #define WM8994_STL_SEL_SHIFT 0 /* STL_SEL */ 4293*4882a593Smuzhiyun #define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */ 4294*4882a593Smuzhiyun 4295*4882a593Smuzhiyun /* 4296*4882a593Smuzhiyun * R1797 (0x705) - JACKDET Ctrl 4297*4882a593Smuzhiyun */ 4298*4882a593Smuzhiyun #define WM1811_JACKDET_DB 0x0100 /* JACKDET_DB */ 4299*4882a593Smuzhiyun #define WM1811_JACKDET_DB_MASK 0x0100 /* JACKDET_DB */ 4300*4882a593Smuzhiyun #define WM1811_JACKDET_DB_SHIFT 8 /* JACKDET_DB */ 4301*4882a593Smuzhiyun #define WM1811_JACKDET_DB_WIDTH 1 /* JACKDET_DB */ 4302*4882a593Smuzhiyun #define WM1811_JACKDET_LVL 0x0040 /* JACKDET_LVL */ 4303*4882a593Smuzhiyun #define WM1811_JACKDET_LVL_MASK 0x0040 /* JACKDET_LVL */ 4304*4882a593Smuzhiyun #define WM1811_JACKDET_LVL_SHIFT 6 /* JACKDET_LVL */ 4305*4882a593Smuzhiyun #define WM1811_JACKDET_LVL_WIDTH 1 /* JACKDET_LVL */ 4306*4882a593Smuzhiyun 4307*4882a593Smuzhiyun /* 4308*4882a593Smuzhiyun * R1824 (0x720) - Pull Control (1) 4309*4882a593Smuzhiyun */ 4310*4882a593Smuzhiyun #define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */ 4311*4882a593Smuzhiyun #define WM8994_DMICDAT2_PU_MASK 0x0800 /* DMICDAT2_PU */ 4312*4882a593Smuzhiyun #define WM8994_DMICDAT2_PU_SHIFT 11 /* DMICDAT2_PU */ 4313*4882a593Smuzhiyun #define WM8994_DMICDAT2_PU_WIDTH 1 /* DMICDAT2_PU */ 4314*4882a593Smuzhiyun #define WM8994_DMICDAT2_PD 0x0400 /* DMICDAT2_PD */ 4315*4882a593Smuzhiyun #define WM8994_DMICDAT2_PD_MASK 0x0400 /* DMICDAT2_PD */ 4316*4882a593Smuzhiyun #define WM8994_DMICDAT2_PD_SHIFT 10 /* DMICDAT2_PD */ 4317*4882a593Smuzhiyun #define WM8994_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 4318*4882a593Smuzhiyun #define WM8994_DMICDAT1_PU 0x0200 /* DMICDAT1_PU */ 4319*4882a593Smuzhiyun #define WM8994_DMICDAT1_PU_MASK 0x0200 /* DMICDAT1_PU */ 4320*4882a593Smuzhiyun #define WM8994_DMICDAT1_PU_SHIFT 9 /* DMICDAT1_PU */ 4321*4882a593Smuzhiyun #define WM8994_DMICDAT1_PU_WIDTH 1 /* DMICDAT1_PU */ 4322*4882a593Smuzhiyun #define WM8994_DMICDAT1_PD 0x0100 /* DMICDAT1_PD */ 4323*4882a593Smuzhiyun #define WM8994_DMICDAT1_PD_MASK 0x0100 /* DMICDAT1_PD */ 4324*4882a593Smuzhiyun #define WM8994_DMICDAT1_PD_SHIFT 8 /* DMICDAT1_PD */ 4325*4882a593Smuzhiyun #define WM8994_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 4326*4882a593Smuzhiyun #define WM8994_MCLK1_PU 0x0080 /* MCLK1_PU */ 4327*4882a593Smuzhiyun #define WM8994_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 4328*4882a593Smuzhiyun #define WM8994_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 4329*4882a593Smuzhiyun #define WM8994_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 4330*4882a593Smuzhiyun #define WM8994_MCLK1_PD 0x0040 /* MCLK1_PD */ 4331*4882a593Smuzhiyun #define WM8994_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 4332*4882a593Smuzhiyun #define WM8994_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 4333*4882a593Smuzhiyun #define WM8994_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 4334*4882a593Smuzhiyun #define WM8994_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 4335*4882a593Smuzhiyun #define WM8994_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 4336*4882a593Smuzhiyun #define WM8994_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 4337*4882a593Smuzhiyun #define WM8994_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 4338*4882a593Smuzhiyun #define WM8994_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 4339*4882a593Smuzhiyun #define WM8994_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 4340*4882a593Smuzhiyun #define WM8994_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 4341*4882a593Smuzhiyun #define WM8994_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 4342*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 4343*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 4344*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 4345*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 4346*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 4347*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 4348*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 4349*4882a593Smuzhiyun #define WM8994_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 4350*4882a593Smuzhiyun #define WM8994_BCLK1_PU 0x0002 /* BCLK1_PU */ 4351*4882a593Smuzhiyun #define WM8994_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 4352*4882a593Smuzhiyun #define WM8994_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 4353*4882a593Smuzhiyun #define WM8994_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 4354*4882a593Smuzhiyun #define WM8994_BCLK1_PD 0x0001 /* BCLK1_PD */ 4355*4882a593Smuzhiyun #define WM8994_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 4356*4882a593Smuzhiyun #define WM8994_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 4357*4882a593Smuzhiyun #define WM8994_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 4358*4882a593Smuzhiyun 4359*4882a593Smuzhiyun /* 4360*4882a593Smuzhiyun * R1825 (0x721) - Pull Control (2) 4361*4882a593Smuzhiyun */ 4362*4882a593Smuzhiyun #define WM8994_CSNADDR_PD 0x0100 /* CSNADDR_PD */ 4363*4882a593Smuzhiyun #define WM8994_CSNADDR_PD_MASK 0x0100 /* CSNADDR_PD */ 4364*4882a593Smuzhiyun #define WM8994_CSNADDR_PD_SHIFT 8 /* CSNADDR_PD */ 4365*4882a593Smuzhiyun #define WM8994_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ 4366*4882a593Smuzhiyun #define WM8994_LDO2ENA_PD 0x0040 /* LDO2ENA_PD */ 4367*4882a593Smuzhiyun #define WM8994_LDO2ENA_PD_MASK 0x0040 /* LDO2ENA_PD */ 4368*4882a593Smuzhiyun #define WM8994_LDO2ENA_PD_SHIFT 6 /* LDO2ENA_PD */ 4369*4882a593Smuzhiyun #define WM8994_LDO2ENA_PD_WIDTH 1 /* LDO2ENA_PD */ 4370*4882a593Smuzhiyun #define WM8994_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ 4371*4882a593Smuzhiyun #define WM8994_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ 4372*4882a593Smuzhiyun #define WM8994_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ 4373*4882a593Smuzhiyun #define WM8994_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 4374*4882a593Smuzhiyun #define WM8994_CIFMODE_PD 0x0004 /* CIFMODE_PD */ 4375*4882a593Smuzhiyun #define WM8994_CIFMODE_PD_MASK 0x0004 /* CIFMODE_PD */ 4376*4882a593Smuzhiyun #define WM8994_CIFMODE_PD_SHIFT 2 /* CIFMODE_PD */ 4377*4882a593Smuzhiyun #define WM8994_CIFMODE_PD_WIDTH 1 /* CIFMODE_PD */ 4378*4882a593Smuzhiyun #define WM8994_SPKMODE_PU 0x0002 /* SPKMODE_PU */ 4379*4882a593Smuzhiyun #define WM8994_SPKMODE_PU_MASK 0x0002 /* SPKMODE_PU */ 4380*4882a593Smuzhiyun #define WM8994_SPKMODE_PU_SHIFT 1 /* SPKMODE_PU */ 4381*4882a593Smuzhiyun #define WM8994_SPKMODE_PU_WIDTH 1 /* SPKMODE_PU */ 4382*4882a593Smuzhiyun 4383*4882a593Smuzhiyun /* 4384*4882a593Smuzhiyun * R1840 (0x730) - Interrupt Status 1 4385*4882a593Smuzhiyun */ 4386*4882a593Smuzhiyun #define WM8994_GP11_EINT 0x0400 /* GP11_EINT */ 4387*4882a593Smuzhiyun #define WM8994_GP11_EINT_MASK 0x0400 /* GP11_EINT */ 4388*4882a593Smuzhiyun #define WM8994_GP11_EINT_SHIFT 10 /* GP11_EINT */ 4389*4882a593Smuzhiyun #define WM8994_GP11_EINT_WIDTH 1 /* GP11_EINT */ 4390*4882a593Smuzhiyun #define WM8994_GP10_EINT 0x0200 /* GP10_EINT */ 4391*4882a593Smuzhiyun #define WM8994_GP10_EINT_MASK 0x0200 /* GP10_EINT */ 4392*4882a593Smuzhiyun #define WM8994_GP10_EINT_SHIFT 9 /* GP10_EINT */ 4393*4882a593Smuzhiyun #define WM8994_GP10_EINT_WIDTH 1 /* GP10_EINT */ 4394*4882a593Smuzhiyun #define WM8994_GP9_EINT 0x0100 /* GP9_EINT */ 4395*4882a593Smuzhiyun #define WM8994_GP9_EINT_MASK 0x0100 /* GP9_EINT */ 4396*4882a593Smuzhiyun #define WM8994_GP9_EINT_SHIFT 8 /* GP9_EINT */ 4397*4882a593Smuzhiyun #define WM8994_GP9_EINT_WIDTH 1 /* GP9_EINT */ 4398*4882a593Smuzhiyun #define WM8994_GP8_EINT 0x0080 /* GP8_EINT */ 4399*4882a593Smuzhiyun #define WM8994_GP8_EINT_MASK 0x0080 /* GP8_EINT */ 4400*4882a593Smuzhiyun #define WM8994_GP8_EINT_SHIFT 7 /* GP8_EINT */ 4401*4882a593Smuzhiyun #define WM8994_GP8_EINT_WIDTH 1 /* GP8_EINT */ 4402*4882a593Smuzhiyun #define WM8994_GP7_EINT 0x0040 /* GP7_EINT */ 4403*4882a593Smuzhiyun #define WM8994_GP7_EINT_MASK 0x0040 /* GP7_EINT */ 4404*4882a593Smuzhiyun #define WM8994_GP7_EINT_SHIFT 6 /* GP7_EINT */ 4405*4882a593Smuzhiyun #define WM8994_GP7_EINT_WIDTH 1 /* GP7_EINT */ 4406*4882a593Smuzhiyun #define WM8994_GP6_EINT 0x0020 /* GP6_EINT */ 4407*4882a593Smuzhiyun #define WM8994_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 4408*4882a593Smuzhiyun #define WM8994_GP6_EINT_SHIFT 5 /* GP6_EINT */ 4409*4882a593Smuzhiyun #define WM8994_GP6_EINT_WIDTH 1 /* GP6_EINT */ 4410*4882a593Smuzhiyun #define WM8994_GP5_EINT 0x0010 /* GP5_EINT */ 4411*4882a593Smuzhiyun #define WM8994_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 4412*4882a593Smuzhiyun #define WM8994_GP5_EINT_SHIFT 4 /* GP5_EINT */ 4413*4882a593Smuzhiyun #define WM8994_GP5_EINT_WIDTH 1 /* GP5_EINT */ 4414*4882a593Smuzhiyun #define WM8994_GP4_EINT 0x0008 /* GP4_EINT */ 4415*4882a593Smuzhiyun #define WM8994_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 4416*4882a593Smuzhiyun #define WM8994_GP4_EINT_SHIFT 3 /* GP4_EINT */ 4417*4882a593Smuzhiyun #define WM8994_GP4_EINT_WIDTH 1 /* GP4_EINT */ 4418*4882a593Smuzhiyun #define WM8994_GP3_EINT 0x0004 /* GP3_EINT */ 4419*4882a593Smuzhiyun #define WM8994_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 4420*4882a593Smuzhiyun #define WM8994_GP3_EINT_SHIFT 2 /* GP3_EINT */ 4421*4882a593Smuzhiyun #define WM8994_GP3_EINT_WIDTH 1 /* GP3_EINT */ 4422*4882a593Smuzhiyun #define WM8994_GP2_EINT 0x0002 /* GP2_EINT */ 4423*4882a593Smuzhiyun #define WM8994_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 4424*4882a593Smuzhiyun #define WM8994_GP2_EINT_SHIFT 1 /* GP2_EINT */ 4425*4882a593Smuzhiyun #define WM8994_GP2_EINT_WIDTH 1 /* GP2_EINT */ 4426*4882a593Smuzhiyun #define WM8994_GP1_EINT 0x0001 /* GP1_EINT */ 4427*4882a593Smuzhiyun #define WM8994_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 4428*4882a593Smuzhiyun #define WM8994_GP1_EINT_SHIFT 0 /* GP1_EINT */ 4429*4882a593Smuzhiyun #define WM8994_GP1_EINT_WIDTH 1 /* GP1_EINT */ 4430*4882a593Smuzhiyun 4431*4882a593Smuzhiyun /* 4432*4882a593Smuzhiyun * R1841 (0x731) - Interrupt Status 2 4433*4882a593Smuzhiyun */ 4434*4882a593Smuzhiyun #define WM8994_TEMP_WARN_EINT 0x8000 /* TEMP_WARN_EINT */ 4435*4882a593Smuzhiyun #define WM8994_TEMP_WARN_EINT_MASK 0x8000 /* TEMP_WARN_EINT */ 4436*4882a593Smuzhiyun #define WM8994_TEMP_WARN_EINT_SHIFT 15 /* TEMP_WARN_EINT */ 4437*4882a593Smuzhiyun #define WM8994_TEMP_WARN_EINT_WIDTH 1 /* TEMP_WARN_EINT */ 4438*4882a593Smuzhiyun #define WM8994_DCS_DONE_EINT 0x4000 /* DCS_DONE_EINT */ 4439*4882a593Smuzhiyun #define WM8994_DCS_DONE_EINT_MASK 0x4000 /* DCS_DONE_EINT */ 4440*4882a593Smuzhiyun #define WM8994_DCS_DONE_EINT_SHIFT 14 /* DCS_DONE_EINT */ 4441*4882a593Smuzhiyun #define WM8994_DCS_DONE_EINT_WIDTH 1 /* DCS_DONE_EINT */ 4442*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_EINT 0x2000 /* WSEQ_DONE_EINT */ 4443*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_EINT_MASK 0x2000 /* WSEQ_DONE_EINT */ 4444*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_EINT_SHIFT 13 /* WSEQ_DONE_EINT */ 4445*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 4446*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_EINT 0x1000 /* FIFOS_ERR_EINT */ 4447*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_EINT_MASK 0x1000 /* FIFOS_ERR_EINT */ 4448*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_EINT_SHIFT 12 /* FIFOS_ERR_EINT */ 4449*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 4450*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_EINT 0x0800 /* AIF2DRC_SIG_DET_EINT */ 4451*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* AIF2DRC_SIG_DET_EINT */ 4452*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* AIF2DRC_SIG_DET_EINT */ 4453*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ 4454*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_EINT 0x0400 /* AIF1DRC2_SIG_DET_EINT */ 4455*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* AIF1DRC2_SIG_DET_EINT */ 4456*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* AIF1DRC2_SIG_DET_EINT */ 4457*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ 4458*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_EINT 0x0200 /* AIF1DRC1_SIG_DET_EINT */ 4459*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* AIF1DRC1_SIG_DET_EINT */ 4460*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* AIF1DRC1_SIG_DET_EINT */ 4461*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ 4462*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_EINT 0x0100 /* SRC2_LOCK_EINT */ 4463*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_EINT_MASK 0x0100 /* SRC2_LOCK_EINT */ 4464*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_EINT_SHIFT 8 /* SRC2_LOCK_EINT */ 4465*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ 4466*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_EINT 0x0080 /* SRC1_LOCK_EINT */ 4467*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_EINT_MASK 0x0080 /* SRC1_LOCK_EINT */ 4468*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_EINT_SHIFT 7 /* SRC1_LOCK_EINT */ 4469*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ 4470*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_EINT 0x0040 /* FLL2_LOCK_EINT */ 4471*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_EINT_MASK 0x0040 /* FLL2_LOCK_EINT */ 4472*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_EINT_SHIFT 6 /* FLL2_LOCK_EINT */ 4473*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 4474*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_EINT 0x0020 /* FLL1_LOCK_EINT */ 4475*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_EINT_MASK 0x0020 /* FLL1_LOCK_EINT */ 4476*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_EINT_SHIFT 5 /* FLL1_LOCK_EINT */ 4477*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 4478*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_EINT 0x0010 /* MIC2_SHRT_EINT */ 4479*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_EINT_MASK 0x0010 /* MIC2_SHRT_EINT */ 4480*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_EINT_SHIFT 4 /* MIC2_SHRT_EINT */ 4481*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_EINT_WIDTH 1 /* MIC2_SHRT_EINT */ 4482*4882a593Smuzhiyun #define WM8994_MIC2_DET_EINT 0x0008 /* MIC2_DET_EINT */ 4483*4882a593Smuzhiyun #define WM8994_MIC2_DET_EINT_MASK 0x0008 /* MIC2_DET_EINT */ 4484*4882a593Smuzhiyun #define WM8994_MIC2_DET_EINT_SHIFT 3 /* MIC2_DET_EINT */ 4485*4882a593Smuzhiyun #define WM8994_MIC2_DET_EINT_WIDTH 1 /* MIC2_DET_EINT */ 4486*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_EINT 0x0004 /* MIC1_SHRT_EINT */ 4487*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_EINT_MASK 0x0004 /* MIC1_SHRT_EINT */ 4488*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_EINT_SHIFT 2 /* MIC1_SHRT_EINT */ 4489*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_EINT_WIDTH 1 /* MIC1_SHRT_EINT */ 4490*4882a593Smuzhiyun #define WM8994_MIC1_DET_EINT 0x0002 /* MIC1_DET_EINT */ 4491*4882a593Smuzhiyun #define WM8994_MIC1_DET_EINT_MASK 0x0002 /* MIC1_DET_EINT */ 4492*4882a593Smuzhiyun #define WM8994_MIC1_DET_EINT_SHIFT 1 /* MIC1_DET_EINT */ 4493*4882a593Smuzhiyun #define WM8994_MIC1_DET_EINT_WIDTH 1 /* MIC1_DET_EINT */ 4494*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */ 4495*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */ 4496*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */ 4497*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */ 4498*4882a593Smuzhiyun 4499*4882a593Smuzhiyun /* 4500*4882a593Smuzhiyun * R1842 (0x732) - Interrupt Raw Status 2 4501*4882a593Smuzhiyun */ 4502*4882a593Smuzhiyun #define WM8994_TEMP_WARN_STS 0x8000 /* TEMP_WARN_STS */ 4503*4882a593Smuzhiyun #define WM8994_TEMP_WARN_STS_MASK 0x8000 /* TEMP_WARN_STS */ 4504*4882a593Smuzhiyun #define WM8994_TEMP_WARN_STS_SHIFT 15 /* TEMP_WARN_STS */ 4505*4882a593Smuzhiyun #define WM8994_TEMP_WARN_STS_WIDTH 1 /* TEMP_WARN_STS */ 4506*4882a593Smuzhiyun #define WM8994_DCS_DONE_STS 0x4000 /* DCS_DONE_STS */ 4507*4882a593Smuzhiyun #define WM8994_DCS_DONE_STS_MASK 0x4000 /* DCS_DONE_STS */ 4508*4882a593Smuzhiyun #define WM8994_DCS_DONE_STS_SHIFT 14 /* DCS_DONE_STS */ 4509*4882a593Smuzhiyun #define WM8994_DCS_DONE_STS_WIDTH 1 /* DCS_DONE_STS */ 4510*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_STS 0x2000 /* WSEQ_DONE_STS */ 4511*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_STS_MASK 0x2000 /* WSEQ_DONE_STS */ 4512*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_STS_SHIFT 13 /* WSEQ_DONE_STS */ 4513*4882a593Smuzhiyun #define WM8994_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 4514*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_STS 0x1000 /* FIFOS_ERR_STS */ 4515*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_STS_MASK 0x1000 /* FIFOS_ERR_STS */ 4516*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_STS_SHIFT 12 /* FIFOS_ERR_STS */ 4517*4882a593Smuzhiyun #define WM8994_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 4518*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_STS 0x0800 /* AIF2DRC_SIG_DET_STS */ 4519*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_STS_MASK 0x0800 /* AIF2DRC_SIG_DET_STS */ 4520*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_STS_SHIFT 11 /* AIF2DRC_SIG_DET_STS */ 4521*4882a593Smuzhiyun #define WM8994_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ 4522*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_STS 0x0400 /* AIF1DRC2_SIG_DET_STS */ 4523*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_STS_MASK 0x0400 /* AIF1DRC2_SIG_DET_STS */ 4524*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT 10 /* AIF1DRC2_SIG_DET_STS */ 4525*4882a593Smuzhiyun #define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ 4526*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_STS 0x0200 /* AIF1DRC1_SIG_DET_STS */ 4527*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_STS_MASK 0x0200 /* AIF1DRC1_SIG_DET_STS */ 4528*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT 9 /* AIF1DRC1_SIG_DET_STS */ 4529*4882a593Smuzhiyun #define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ 4530*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_STS 0x0100 /* SRC2_LOCK_STS */ 4531*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_STS_MASK 0x0100 /* SRC2_LOCK_STS */ 4532*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_STS_SHIFT 8 /* SRC2_LOCK_STS */ 4533*4882a593Smuzhiyun #define WM8994_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ 4534*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_STS 0x0080 /* SRC1_LOCK_STS */ 4535*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_STS_MASK 0x0080 /* SRC1_LOCK_STS */ 4536*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_STS_SHIFT 7 /* SRC1_LOCK_STS */ 4537*4882a593Smuzhiyun #define WM8994_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ 4538*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_STS 0x0040 /* FLL2_LOCK_STS */ 4539*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_STS_MASK 0x0040 /* FLL2_LOCK_STS */ 4540*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_STS_SHIFT 6 /* FLL2_LOCK_STS */ 4541*4882a593Smuzhiyun #define WM8994_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 4542*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_STS 0x0020 /* FLL1_LOCK_STS */ 4543*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_STS_MASK 0x0020 /* FLL1_LOCK_STS */ 4544*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_STS_SHIFT 5 /* FLL1_LOCK_STS */ 4545*4882a593Smuzhiyun #define WM8994_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 4546*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_STS 0x0010 /* MIC2_SHRT_STS */ 4547*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_STS_MASK 0x0010 /* MIC2_SHRT_STS */ 4548*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_STS_SHIFT 4 /* MIC2_SHRT_STS */ 4549*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_STS_WIDTH 1 /* MIC2_SHRT_STS */ 4550*4882a593Smuzhiyun #define WM8994_MIC2_DET_STS 0x0008 /* MIC2_DET_STS */ 4551*4882a593Smuzhiyun #define WM8994_MIC2_DET_STS_MASK 0x0008 /* MIC2_DET_STS */ 4552*4882a593Smuzhiyun #define WM8994_MIC2_DET_STS_SHIFT 3 /* MIC2_DET_STS */ 4553*4882a593Smuzhiyun #define WM8994_MIC2_DET_STS_WIDTH 1 /* MIC2_DET_STS */ 4554*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_STS 0x0004 /* MIC1_SHRT_STS */ 4555*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_STS_MASK 0x0004 /* MIC1_SHRT_STS */ 4556*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_STS_SHIFT 2 /* MIC1_SHRT_STS */ 4557*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_STS_WIDTH 1 /* MIC1_SHRT_STS */ 4558*4882a593Smuzhiyun #define WM8994_MIC1_DET_STS 0x0002 /* MIC1_DET_STS */ 4559*4882a593Smuzhiyun #define WM8994_MIC1_DET_STS_MASK 0x0002 /* MIC1_DET_STS */ 4560*4882a593Smuzhiyun #define WM8994_MIC1_DET_STS_SHIFT 1 /* MIC1_DET_STS */ 4561*4882a593Smuzhiyun #define WM8994_MIC1_DET_STS_WIDTH 1 /* MIC1_DET_STS */ 4562*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_STS 0x0001 /* TEMP_SHUT_STS */ 4563*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_STS_MASK 0x0001 /* TEMP_SHUT_STS */ 4564*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_STS_SHIFT 0 /* TEMP_SHUT_STS */ 4565*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_STS_WIDTH 1 /* TEMP_SHUT_STS */ 4566*4882a593Smuzhiyun 4567*4882a593Smuzhiyun /* 4568*4882a593Smuzhiyun * R1848 (0x738) - Interrupt Status 1 Mask 4569*4882a593Smuzhiyun */ 4570*4882a593Smuzhiyun #define WM8994_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ 4571*4882a593Smuzhiyun #define WM8994_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ 4572*4882a593Smuzhiyun #define WM8994_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ 4573*4882a593Smuzhiyun #define WM8994_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ 4574*4882a593Smuzhiyun #define WM8994_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ 4575*4882a593Smuzhiyun #define WM8994_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ 4576*4882a593Smuzhiyun #define WM8994_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ 4577*4882a593Smuzhiyun #define WM8994_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ 4578*4882a593Smuzhiyun #define WM8994_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ 4579*4882a593Smuzhiyun #define WM8994_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ 4580*4882a593Smuzhiyun #define WM8994_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ 4581*4882a593Smuzhiyun #define WM8994_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ 4582*4882a593Smuzhiyun #define WM8994_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ 4583*4882a593Smuzhiyun #define WM8994_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ 4584*4882a593Smuzhiyun #define WM8994_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ 4585*4882a593Smuzhiyun #define WM8994_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ 4586*4882a593Smuzhiyun #define WM8994_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ 4587*4882a593Smuzhiyun #define WM8994_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ 4588*4882a593Smuzhiyun #define WM8994_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ 4589*4882a593Smuzhiyun #define WM8994_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ 4590*4882a593Smuzhiyun #define WM8994_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 4591*4882a593Smuzhiyun #define WM8994_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 4592*4882a593Smuzhiyun #define WM8994_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 4593*4882a593Smuzhiyun #define WM8994_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 4594*4882a593Smuzhiyun #define WM8994_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 4595*4882a593Smuzhiyun #define WM8994_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 4596*4882a593Smuzhiyun #define WM8994_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 4597*4882a593Smuzhiyun #define WM8994_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 4598*4882a593Smuzhiyun #define WM8994_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 4599*4882a593Smuzhiyun #define WM8994_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 4600*4882a593Smuzhiyun #define WM8994_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 4601*4882a593Smuzhiyun #define WM8994_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 4602*4882a593Smuzhiyun #define WM8994_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 4603*4882a593Smuzhiyun #define WM8994_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 4604*4882a593Smuzhiyun #define WM8994_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 4605*4882a593Smuzhiyun #define WM8994_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 4606*4882a593Smuzhiyun #define WM8994_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 4607*4882a593Smuzhiyun #define WM8994_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 4608*4882a593Smuzhiyun #define WM8994_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 4609*4882a593Smuzhiyun #define WM8994_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 4610*4882a593Smuzhiyun #define WM8994_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 4611*4882a593Smuzhiyun #define WM8994_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 4612*4882a593Smuzhiyun #define WM8994_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 4613*4882a593Smuzhiyun #define WM8994_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 4614*4882a593Smuzhiyun 4615*4882a593Smuzhiyun /* 4616*4882a593Smuzhiyun * R1849 (0x739) - Interrupt Status 2 Mask 4617*4882a593Smuzhiyun */ 4618*4882a593Smuzhiyun #define WM8994_IM_TEMP_WARN_EINT 0x8000 /* IM_TEMP_WARN_EINT */ 4619*4882a593Smuzhiyun #define WM8994_IM_TEMP_WARN_EINT_MASK 0x8000 /* IM_TEMP_WARN_EINT */ 4620*4882a593Smuzhiyun #define WM8994_IM_TEMP_WARN_EINT_SHIFT 15 /* IM_TEMP_WARN_EINT */ 4621*4882a593Smuzhiyun #define WM8994_IM_TEMP_WARN_EINT_WIDTH 1 /* IM_TEMP_WARN_EINT */ 4622*4882a593Smuzhiyun #define WM8994_IM_DCS_DONE_EINT 0x4000 /* IM_DCS_DONE_EINT */ 4623*4882a593Smuzhiyun #define WM8994_IM_DCS_DONE_EINT_MASK 0x4000 /* IM_DCS_DONE_EINT */ 4624*4882a593Smuzhiyun #define WM8994_IM_DCS_DONE_EINT_SHIFT 14 /* IM_DCS_DONE_EINT */ 4625*4882a593Smuzhiyun #define WM8994_IM_DCS_DONE_EINT_WIDTH 1 /* IM_DCS_DONE_EINT */ 4626*4882a593Smuzhiyun #define WM8994_IM_WSEQ_DONE_EINT 0x2000 /* IM_WSEQ_DONE_EINT */ 4627*4882a593Smuzhiyun #define WM8994_IM_WSEQ_DONE_EINT_MASK 0x2000 /* IM_WSEQ_DONE_EINT */ 4628*4882a593Smuzhiyun #define WM8994_IM_WSEQ_DONE_EINT_SHIFT 13 /* IM_WSEQ_DONE_EINT */ 4629*4882a593Smuzhiyun #define WM8994_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 4630*4882a593Smuzhiyun #define WM8994_IM_FIFOS_ERR_EINT 0x1000 /* IM_FIFOS_ERR_EINT */ 4631*4882a593Smuzhiyun #define WM8994_IM_FIFOS_ERR_EINT_MASK 0x1000 /* IM_FIFOS_ERR_EINT */ 4632*4882a593Smuzhiyun #define WM8994_IM_FIFOS_ERR_EINT_SHIFT 12 /* IM_FIFOS_ERR_EINT */ 4633*4882a593Smuzhiyun #define WM8994_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 4634*4882a593Smuzhiyun #define WM8994_IM_AIF2DRC_SIG_DET_EINT 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */ 4635*4882a593Smuzhiyun #define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */ 4636*4882a593Smuzhiyun #define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* IM_AIF2DRC_SIG_DET_EINT */ 4637*4882a593Smuzhiyun #define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ 4638*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC2_SIG_DET_EINT 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */ 4639*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */ 4640*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* IM_AIF1DRC2_SIG_DET_EINT */ 4641*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ 4642*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC1_SIG_DET_EINT 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */ 4643*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */ 4644*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* IM_AIF1DRC1_SIG_DET_EINT */ 4645*4882a593Smuzhiyun #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ 4646*4882a593Smuzhiyun #define WM8994_IM_SRC2_LOCK_EINT 0x0100 /* IM_SRC2_LOCK_EINT */ 4647*4882a593Smuzhiyun #define WM8994_IM_SRC2_LOCK_EINT_MASK 0x0100 /* IM_SRC2_LOCK_EINT */ 4648*4882a593Smuzhiyun #define WM8994_IM_SRC2_LOCK_EINT_SHIFT 8 /* IM_SRC2_LOCK_EINT */ 4649*4882a593Smuzhiyun #define WM8994_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ 4650*4882a593Smuzhiyun #define WM8994_IM_SRC1_LOCK_EINT 0x0080 /* IM_SRC1_LOCK_EINT */ 4651*4882a593Smuzhiyun #define WM8994_IM_SRC1_LOCK_EINT_MASK 0x0080 /* IM_SRC1_LOCK_EINT */ 4652*4882a593Smuzhiyun #define WM8994_IM_SRC1_LOCK_EINT_SHIFT 7 /* IM_SRC1_LOCK_EINT */ 4653*4882a593Smuzhiyun #define WM8994_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ 4654*4882a593Smuzhiyun #define WM8994_IM_FLL2_LOCK_EINT 0x0040 /* IM_FLL2_LOCK_EINT */ 4655*4882a593Smuzhiyun #define WM8994_IM_FLL2_LOCK_EINT_MASK 0x0040 /* IM_FLL2_LOCK_EINT */ 4656*4882a593Smuzhiyun #define WM8994_IM_FLL2_LOCK_EINT_SHIFT 6 /* IM_FLL2_LOCK_EINT */ 4657*4882a593Smuzhiyun #define WM8994_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 4658*4882a593Smuzhiyun #define WM8994_IM_FLL1_LOCK_EINT 0x0020 /* IM_FLL1_LOCK_EINT */ 4659*4882a593Smuzhiyun #define WM8994_IM_FLL1_LOCK_EINT_MASK 0x0020 /* IM_FLL1_LOCK_EINT */ 4660*4882a593Smuzhiyun #define WM8994_IM_FLL1_LOCK_EINT_SHIFT 5 /* IM_FLL1_LOCK_EINT */ 4661*4882a593Smuzhiyun #define WM8994_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 4662*4882a593Smuzhiyun #define WM8994_IM_MIC2_SHRT_EINT 0x0010 /* IM_MIC2_SHRT_EINT */ 4663*4882a593Smuzhiyun #define WM8994_IM_MIC2_SHRT_EINT_MASK 0x0010 /* IM_MIC2_SHRT_EINT */ 4664*4882a593Smuzhiyun #define WM8994_IM_MIC2_SHRT_EINT_SHIFT 4 /* IM_MIC2_SHRT_EINT */ 4665*4882a593Smuzhiyun #define WM8994_IM_MIC2_SHRT_EINT_WIDTH 1 /* IM_MIC2_SHRT_EINT */ 4666*4882a593Smuzhiyun #define WM8994_IM_MIC2_DET_EINT 0x0008 /* IM_MIC2_DET_EINT */ 4667*4882a593Smuzhiyun #define WM8994_IM_MIC2_DET_EINT_MASK 0x0008 /* IM_MIC2_DET_EINT */ 4668*4882a593Smuzhiyun #define WM8994_IM_MIC2_DET_EINT_SHIFT 3 /* IM_MIC2_DET_EINT */ 4669*4882a593Smuzhiyun #define WM8994_IM_MIC2_DET_EINT_WIDTH 1 /* IM_MIC2_DET_EINT */ 4670*4882a593Smuzhiyun #define WM8994_IM_MIC1_SHRT_EINT 0x0004 /* IM_MIC1_SHRT_EINT */ 4671*4882a593Smuzhiyun #define WM8994_IM_MIC1_SHRT_EINT_MASK 0x0004 /* IM_MIC1_SHRT_EINT */ 4672*4882a593Smuzhiyun #define WM8994_IM_MIC1_SHRT_EINT_SHIFT 2 /* IM_MIC1_SHRT_EINT */ 4673*4882a593Smuzhiyun #define WM8994_IM_MIC1_SHRT_EINT_WIDTH 1 /* IM_MIC1_SHRT_EINT */ 4674*4882a593Smuzhiyun #define WM8994_IM_MIC1_DET_EINT 0x0002 /* IM_MIC1_DET_EINT */ 4675*4882a593Smuzhiyun #define WM8994_IM_MIC1_DET_EINT_MASK 0x0002 /* IM_MIC1_DET_EINT */ 4676*4882a593Smuzhiyun #define WM8994_IM_MIC1_DET_EINT_SHIFT 1 /* IM_MIC1_DET_EINT */ 4677*4882a593Smuzhiyun #define WM8994_IM_MIC1_DET_EINT_WIDTH 1 /* IM_MIC1_DET_EINT */ 4678*4882a593Smuzhiyun #define WM8994_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */ 4679*4882a593Smuzhiyun #define WM8994_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */ 4680*4882a593Smuzhiyun #define WM8994_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */ 4681*4882a593Smuzhiyun #define WM8994_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */ 4682*4882a593Smuzhiyun 4683*4882a593Smuzhiyun /* 4684*4882a593Smuzhiyun * R1856 (0x740) - Interrupt Control 4685*4882a593Smuzhiyun */ 4686*4882a593Smuzhiyun #define WM8994_IM_IRQ 0x0001 /* IM_IRQ */ 4687*4882a593Smuzhiyun #define WM8994_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 4688*4882a593Smuzhiyun #define WM8994_IM_IRQ_SHIFT 0 /* IM_IRQ */ 4689*4882a593Smuzhiyun #define WM8994_IM_IRQ_WIDTH 1 /* IM_IRQ */ 4690*4882a593Smuzhiyun 4691*4882a593Smuzhiyun /* 4692*4882a593Smuzhiyun * R1864 (0x748) - IRQ Debounce 4693*4882a593Smuzhiyun */ 4694*4882a593Smuzhiyun #define WM8994_TEMP_WARN_DB 0x0020 /* TEMP_WARN_DB */ 4695*4882a593Smuzhiyun #define WM8994_TEMP_WARN_DB_MASK 0x0020 /* TEMP_WARN_DB */ 4696*4882a593Smuzhiyun #define WM8994_TEMP_WARN_DB_SHIFT 5 /* TEMP_WARN_DB */ 4697*4882a593Smuzhiyun #define WM8994_TEMP_WARN_DB_WIDTH 1 /* TEMP_WARN_DB */ 4698*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_DB 0x0010 /* MIC2_SHRT_DB */ 4699*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_DB_MASK 0x0010 /* MIC2_SHRT_DB */ 4700*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_DB_SHIFT 4 /* MIC2_SHRT_DB */ 4701*4882a593Smuzhiyun #define WM8994_MIC2_SHRT_DB_WIDTH 1 /* MIC2_SHRT_DB */ 4702*4882a593Smuzhiyun #define WM8994_MIC2_DET_DB 0x0008 /* MIC2_DET_DB */ 4703*4882a593Smuzhiyun #define WM8994_MIC2_DET_DB_MASK 0x0008 /* MIC2_DET_DB */ 4704*4882a593Smuzhiyun #define WM8994_MIC2_DET_DB_SHIFT 3 /* MIC2_DET_DB */ 4705*4882a593Smuzhiyun #define WM8994_MIC2_DET_DB_WIDTH 1 /* MIC2_DET_DB */ 4706*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_DB 0x0004 /* MIC1_SHRT_DB */ 4707*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_DB_MASK 0x0004 /* MIC1_SHRT_DB */ 4708*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_DB_SHIFT 2 /* MIC1_SHRT_DB */ 4709*4882a593Smuzhiyun #define WM8994_MIC1_SHRT_DB_WIDTH 1 /* MIC1_SHRT_DB */ 4710*4882a593Smuzhiyun #define WM8994_MIC1_DET_DB 0x0002 /* MIC1_DET_DB */ 4711*4882a593Smuzhiyun #define WM8994_MIC1_DET_DB_MASK 0x0002 /* MIC1_DET_DB */ 4712*4882a593Smuzhiyun #define WM8994_MIC1_DET_DB_SHIFT 1 /* MIC1_DET_DB */ 4713*4882a593Smuzhiyun #define WM8994_MIC1_DET_DB_WIDTH 1 /* MIC1_DET_DB */ 4714*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */ 4715*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */ 4716*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ 4717*4882a593Smuzhiyun #define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ 4718*4882a593Smuzhiyun 4719*4882a593Smuzhiyun /* 4720*4882a593Smuzhiyun * R2304 (0x900) - DSP2_Program 4721*4882a593Smuzhiyun */ 4722*4882a593Smuzhiyun #define WM8958_DSP2_ENA 0x0001 /* DSP2_ENA */ 4723*4882a593Smuzhiyun #define WM8958_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */ 4724*4882a593Smuzhiyun #define WM8958_DSP2_ENA_SHIFT 0 /* DSP2_ENA */ 4725*4882a593Smuzhiyun #define WM8958_DSP2_ENA_WIDTH 1 /* DSP2_ENA */ 4726*4882a593Smuzhiyun 4727*4882a593Smuzhiyun /* 4728*4882a593Smuzhiyun * R2305 (0x901) - DSP2_Config 4729*4882a593Smuzhiyun */ 4730*4882a593Smuzhiyun #define WM8958_MBC_SEL_MASK 0x0030 /* MBC_SEL - [5:4] */ 4731*4882a593Smuzhiyun #define WM8958_MBC_SEL_SHIFT 4 /* MBC_SEL - [5:4] */ 4732*4882a593Smuzhiyun #define WM8958_MBC_SEL_WIDTH 2 /* MBC_SEL - [5:4] */ 4733*4882a593Smuzhiyun #define WM8958_MBC_ENA 0x0001 /* MBC_ENA */ 4734*4882a593Smuzhiyun #define WM8958_MBC_ENA_MASK 0x0001 /* MBC_ENA */ 4735*4882a593Smuzhiyun #define WM8958_MBC_ENA_SHIFT 0 /* MBC_ENA */ 4736*4882a593Smuzhiyun #define WM8958_MBC_ENA_WIDTH 1 /* MBC_ENA */ 4737*4882a593Smuzhiyun 4738*4882a593Smuzhiyun /* 4739*4882a593Smuzhiyun * R2560 (0xA00) - DSP2_MagicNum 4740*4882a593Smuzhiyun */ 4741*4882a593Smuzhiyun #define WM8958_DSP2_MAGIC_NUM_MASK 0xFFFF /* DSP2_MAGIC_NUM - [15:0] */ 4742*4882a593Smuzhiyun #define WM8958_DSP2_MAGIC_NUM_SHIFT 0 /* DSP2_MAGIC_NUM - [15:0] */ 4743*4882a593Smuzhiyun #define WM8958_DSP2_MAGIC_NUM_WIDTH 16 /* DSP2_MAGIC_NUM - [15:0] */ 4744*4882a593Smuzhiyun 4745*4882a593Smuzhiyun /* 4746*4882a593Smuzhiyun * R2561 (0xA01) - DSP2_ReleaseYear 4747*4882a593Smuzhiyun */ 4748*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_YEAR_MASK 0xFFFF /* DSP2_RELEASE_YEAR - [15:0] */ 4749*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_YEAR_SHIFT 0 /* DSP2_RELEASE_YEAR - [15:0] */ 4750*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_YEAR_WIDTH 16 /* DSP2_RELEASE_YEAR - [15:0] */ 4751*4882a593Smuzhiyun 4752*4882a593Smuzhiyun /* 4753*4882a593Smuzhiyun * R2562 (0xA02) - DSP2_ReleaseMonthDay 4754*4882a593Smuzhiyun */ 4755*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_MONTH_MASK 0xFF00 /* DSP2_RELEASE_MONTH - [15:8] */ 4756*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_MONTH_SHIFT 8 /* DSP2_RELEASE_MONTH - [15:8] */ 4757*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_MONTH_WIDTH 8 /* DSP2_RELEASE_MONTH - [15:8] */ 4758*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_DAY_MASK 0x00FF /* DSP2_RELEASE_DAY - [7:0] */ 4759*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_DAY_SHIFT 0 /* DSP2_RELEASE_DAY - [7:0] */ 4760*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_DAY_WIDTH 8 /* DSP2_RELEASE_DAY - [7:0] */ 4761*4882a593Smuzhiyun 4762*4882a593Smuzhiyun /* 4763*4882a593Smuzhiyun * R2563 (0xA03) - DSP2_ReleaseTime 4764*4882a593Smuzhiyun */ 4765*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_HOURS_MASK 0xFF00 /* DSP2_RELEASE_HOURS - [15:8] */ 4766*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_HOURS_SHIFT 8 /* DSP2_RELEASE_HOURS - [15:8] */ 4767*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_HOURS_WIDTH 8 /* DSP2_RELEASE_HOURS - [15:8] */ 4768*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_MINS_MASK 0x00FF /* DSP2_RELEASE_MINS - [7:0] */ 4769*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_MINS_SHIFT 0 /* DSP2_RELEASE_MINS - [7:0] */ 4770*4882a593Smuzhiyun #define WM8958_DSP2_RELEASE_MINS_WIDTH 8 /* DSP2_RELEASE_MINS - [7:0] */ 4771*4882a593Smuzhiyun 4772*4882a593Smuzhiyun /* 4773*4882a593Smuzhiyun * R2564 (0xA04) - DSP2_VerMajMin 4774*4882a593Smuzhiyun */ 4775*4882a593Smuzhiyun #define WM8958_DSP2_MAJOR_VER_MASK 0xFF00 /* DSP2_MAJOR_VER - [15:8] */ 4776*4882a593Smuzhiyun #define WM8958_DSP2_MAJOR_VER_SHIFT 8 /* DSP2_MAJOR_VER - [15:8] */ 4777*4882a593Smuzhiyun #define WM8958_DSP2_MAJOR_VER_WIDTH 8 /* DSP2_MAJOR_VER - [15:8] */ 4778*4882a593Smuzhiyun #define WM8958_DSP2_MINOR_VER_MASK 0x00FF /* DSP2_MINOR_VER - [7:0] */ 4779*4882a593Smuzhiyun #define WM8958_DSP2_MINOR_VER_SHIFT 0 /* DSP2_MINOR_VER - [7:0] */ 4780*4882a593Smuzhiyun #define WM8958_DSP2_MINOR_VER_WIDTH 8 /* DSP2_MINOR_VER - [7:0] */ 4781*4882a593Smuzhiyun 4782*4882a593Smuzhiyun /* 4783*4882a593Smuzhiyun * R2565 (0xA05) - DSP2_VerBuild 4784*4882a593Smuzhiyun */ 4785*4882a593Smuzhiyun #define WM8958_DSP2_BUILD_VER_MASK 0xFFFF /* DSP2_BUILD_VER - [15:0] */ 4786*4882a593Smuzhiyun #define WM8958_DSP2_BUILD_VER_SHIFT 0 /* DSP2_BUILD_VER - [15:0] */ 4787*4882a593Smuzhiyun #define WM8958_DSP2_BUILD_VER_WIDTH 16 /* DSP2_BUILD_VER - [15:0] */ 4788*4882a593Smuzhiyun 4789*4882a593Smuzhiyun /* 4790*4882a593Smuzhiyun * R2573 (0xA0D) - DSP2_ExecControl 4791*4882a593Smuzhiyun */ 4792*4882a593Smuzhiyun #define WM8958_DSP2_STOPC 0x0020 /* DSP2_STOPC */ 4793*4882a593Smuzhiyun #define WM8958_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */ 4794*4882a593Smuzhiyun #define WM8958_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */ 4795*4882a593Smuzhiyun #define WM8958_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */ 4796*4882a593Smuzhiyun #define WM8958_DSP2_STOPS 0x0010 /* DSP2_STOPS */ 4797*4882a593Smuzhiyun #define WM8958_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */ 4798*4882a593Smuzhiyun #define WM8958_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */ 4799*4882a593Smuzhiyun #define WM8958_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */ 4800*4882a593Smuzhiyun #define WM8958_DSP2_STOPI 0x0008 /* DSP2_STOPI */ 4801*4882a593Smuzhiyun #define WM8958_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */ 4802*4882a593Smuzhiyun #define WM8958_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */ 4803*4882a593Smuzhiyun #define WM8958_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */ 4804*4882a593Smuzhiyun #define WM8958_DSP2_STOP 0x0004 /* DSP2_STOP */ 4805*4882a593Smuzhiyun #define WM8958_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */ 4806*4882a593Smuzhiyun #define WM8958_DSP2_STOP_SHIFT 2 /* DSP2_STOP */ 4807*4882a593Smuzhiyun #define WM8958_DSP2_STOP_WIDTH 1 /* DSP2_STOP */ 4808*4882a593Smuzhiyun #define WM8958_DSP2_RUNR 0x0002 /* DSP2_RUNR */ 4809*4882a593Smuzhiyun #define WM8958_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */ 4810*4882a593Smuzhiyun #define WM8958_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */ 4811*4882a593Smuzhiyun #define WM8958_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */ 4812*4882a593Smuzhiyun #define WM8958_DSP2_RUN 0x0001 /* DSP2_RUN */ 4813*4882a593Smuzhiyun #define WM8958_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */ 4814*4882a593Smuzhiyun #define WM8958_DSP2_RUN_SHIFT 0 /* DSP2_RUN */ 4815*4882a593Smuzhiyun #define WM8958_DSP2_RUN_WIDTH 1 /* DSP2_RUN */ 4816*4882a593Smuzhiyun 4817*4882a593Smuzhiyun #endif 4818