xref: /OK3568_Linux_fs/kernel/include/linux/mfd/wm8994/pdata.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * include/linux/mfd/wm8994/pdata.h -- Platform data for WM8994
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2009 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef __MFD_WM8994_PDATA_H__
11*4882a593Smuzhiyun #define __MFD_WM8994_PDATA_H__
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define WM8994_NUM_LDO   2
14*4882a593Smuzhiyun #define WM8994_NUM_GPIO 11
15*4882a593Smuzhiyun #define WM8994_NUM_AIF   3
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun struct wm8994_ldo_pdata {
18*4882a593Smuzhiyun 	const struct regulator_init_data *init_data;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define WM8994_CONFIGURE_GPIO 0x10000
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define WM8994_DRC_REGS 5
24*4882a593Smuzhiyun #define WM8994_EQ_REGS  20
25*4882a593Smuzhiyun #define WM8958_MBC_CUTOFF_REGS 20
26*4882a593Smuzhiyun #define WM8958_MBC_COEFF_REGS  48
27*4882a593Smuzhiyun #define WM8958_MBC_COMBINED_REGS 56
28*4882a593Smuzhiyun #define WM8958_VSS_HPF_REGS 2
29*4882a593Smuzhiyun #define WM8958_VSS_REGS 148
30*4882a593Smuzhiyun #define WM8958_ENH_EQ_REGS 32
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /**
33*4882a593Smuzhiyun  * DRC configurations are specified with a label and a set of register
34*4882a593Smuzhiyun  * values to write (the enable bits will be ignored).  At runtime an
35*4882a593Smuzhiyun  * enumerated control will be presented for each DRC block allowing
36*4882a593Smuzhiyun  * the user to choose the configuration to use.
37*4882a593Smuzhiyun  *
38*4882a593Smuzhiyun  * Configurations may be generated by hand or by using the DRC control
39*4882a593Smuzhiyun  * panel provided by the WISCE - see  http://www.wolfsonmicro.com/wisce/
40*4882a593Smuzhiyun  * for details.
41*4882a593Smuzhiyun  */
42*4882a593Smuzhiyun struct wm8994_drc_cfg {
43*4882a593Smuzhiyun         const char *name;
44*4882a593Smuzhiyun         u16 regs[WM8994_DRC_REGS];
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /**
48*4882a593Smuzhiyun  * ReTune Mobile configurations are specified with a label, sample
49*4882a593Smuzhiyun  * rate and set of values to write (the enable bits will be ignored).
50*4882a593Smuzhiyun  *
51*4882a593Smuzhiyun  * Configurations are expected to be generated using the ReTune Mobile
52*4882a593Smuzhiyun  * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/
53*4882a593Smuzhiyun  */
54*4882a593Smuzhiyun struct wm8994_retune_mobile_cfg {
55*4882a593Smuzhiyun         const char *name;
56*4882a593Smuzhiyun         unsigned int rate;
57*4882a593Smuzhiyun         u16 regs[WM8994_EQ_REGS];
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /**
61*4882a593Smuzhiyun  * Multiband compressor configurations are specified with a label and
62*4882a593Smuzhiyun  * two sets of values to write.  Configurations are expected to be
63*4882a593Smuzhiyun  * generated using the multiband compressor configuration panel in
64*4882a593Smuzhiyun  * WISCE - see http://www.wolfsonmicro.com/wisce/
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun struct wm8958_mbc_cfg {
67*4882a593Smuzhiyun 	const char *name;
68*4882a593Smuzhiyun 	u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS];
69*4882a593Smuzhiyun 	u16 coeff_regs[WM8958_MBC_COEFF_REGS];
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	/* Coefficient layout when using MBC+VSS firmware */
72*4882a593Smuzhiyun 	u16 combined_regs[WM8958_MBC_COMBINED_REGS];
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /**
76*4882a593Smuzhiyun  * VSS HPF configurations are specified with a label and two values to
77*4882a593Smuzhiyun  * write.  Configurations are expected to be generated using the
78*4882a593Smuzhiyun  * multiband compressor configuration panel in WISCE - see
79*4882a593Smuzhiyun  * http://www.wolfsonmicro.com/wisce/
80*4882a593Smuzhiyun  */
81*4882a593Smuzhiyun struct wm8958_vss_hpf_cfg {
82*4882a593Smuzhiyun 	const char *name;
83*4882a593Smuzhiyun 	u16 regs[WM8958_VSS_HPF_REGS];
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun  * VSS configurations are specified with a label and array of values
88*4882a593Smuzhiyun  * to write.  Configurations are expected to be generated using the
89*4882a593Smuzhiyun  * multiband compressor configuration panel in WISCE - see
90*4882a593Smuzhiyun  * http://www.wolfsonmicro.com/wisce/
91*4882a593Smuzhiyun  */
92*4882a593Smuzhiyun struct wm8958_vss_cfg {
93*4882a593Smuzhiyun 	const char *name;
94*4882a593Smuzhiyun 	u16 regs[WM8958_VSS_REGS];
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /**
98*4882a593Smuzhiyun  * Enhanced EQ configurations are specified with a label and array of
99*4882a593Smuzhiyun  * values to write.  Configurations are expected to be generated using
100*4882a593Smuzhiyun  * the multiband compressor configuration panel in WISCE - see
101*4882a593Smuzhiyun  * http://www.wolfsonmicro.com/wisce/
102*4882a593Smuzhiyun  */
103*4882a593Smuzhiyun struct wm8958_enh_eq_cfg {
104*4882a593Smuzhiyun 	const char *name;
105*4882a593Smuzhiyun 	u16 regs[WM8958_ENH_EQ_REGS];
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /**
109*4882a593Smuzhiyun  * Microphone detection rates, used to tune response rates and power
110*4882a593Smuzhiyun  * consumption for WM8958/WM1811 microphone detection.
111*4882a593Smuzhiyun  *
112*4882a593Smuzhiyun  * @sysclk: System clock rate to use this configuration for.
113*4882a593Smuzhiyun  * @idle: True if this configuration should use when no accessory is detected,
114*4882a593Smuzhiyun  *        false otherwise.
115*4882a593Smuzhiyun  * @start: Value for MICD_BIAS_START_TIME register field (not shifted).
116*4882a593Smuzhiyun  * @rate: Value for MICD_RATE register field (not shifted).
117*4882a593Smuzhiyun  */
118*4882a593Smuzhiyun struct wm8958_micd_rate {
119*4882a593Smuzhiyun 	int sysclk;
120*4882a593Smuzhiyun 	bool idle;
121*4882a593Smuzhiyun 	int start;
122*4882a593Smuzhiyun 	int rate;
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun struct wm8994_pdata {
126*4882a593Smuzhiyun 	int gpio_base;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/**
129*4882a593Smuzhiyun 	 * Default values for GPIOs if non-zero, WM8994_CONFIGURE_GPIO
130*4882a593Smuzhiyun 	 * can be used for all zero values.
131*4882a593Smuzhiyun 	 */
132*4882a593Smuzhiyun 	int gpio_defaults[WM8994_NUM_GPIO];
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO];
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	int irq_base;  /** Base IRQ number for WM8994, required for IRQs */
137*4882a593Smuzhiyun 	unsigned long irq_flags; /** user irq flags */
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun         int num_drc_cfgs;
140*4882a593Smuzhiyun         struct wm8994_drc_cfg *drc_cfgs;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun         int num_retune_mobile_cfgs;
143*4882a593Smuzhiyun         struct wm8994_retune_mobile_cfg *retune_mobile_cfgs;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	int num_mbc_cfgs;
146*4882a593Smuzhiyun 	struct wm8958_mbc_cfg *mbc_cfgs;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	int num_vss_cfgs;
149*4882a593Smuzhiyun 	struct wm8958_vss_cfg *vss_cfgs;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	int num_vss_hpf_cfgs;
152*4882a593Smuzhiyun 	struct wm8958_vss_hpf_cfg *vss_hpf_cfgs;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	int num_enh_eq_cfgs;
155*4882a593Smuzhiyun 	struct wm8958_enh_eq_cfg *enh_eq_cfgs;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	int num_micd_rates;
158*4882a593Smuzhiyun 	struct wm8958_micd_rate *micd_rates;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	/* Power up delays to add after microphone bias power up (ms) */
161*4882a593Smuzhiyun 	int micb1_delay;
162*4882a593Smuzhiyun 	int micb2_delay;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun         /* LINEOUT can be differential or single ended */
165*4882a593Smuzhiyun         unsigned int lineout1_diff:1;
166*4882a593Smuzhiyun         unsigned int lineout2_diff:1;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun         /* Common mode feedback */
169*4882a593Smuzhiyun         unsigned int lineout1fb:1;
170*4882a593Smuzhiyun         unsigned int lineout2fb:1;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/* Delay between detecting a jack and starting microphone
173*4882a593Smuzhiyun 	 * detect (specified in ms)
174*4882a593Smuzhiyun 	 */
175*4882a593Smuzhiyun 	int micdet_delay;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	/* Delay between microphone detect completing and reporting on
178*4882a593Smuzhiyun 	 * insert (specified in ms)
179*4882a593Smuzhiyun 	 */
180*4882a593Smuzhiyun 	int mic_id_delay;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	/* IRQ for microphone detection if brought out directly as a
183*4882a593Smuzhiyun 	 * signal.
184*4882a593Smuzhiyun 	 */
185*4882a593Smuzhiyun 	int micdet_irq;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun         /* WM8994 microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */
188*4882a593Smuzhiyun         unsigned int micbias1_lvl:1;
189*4882a593Smuzhiyun         unsigned int micbias2_lvl:1;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun         /* WM8994 jack detect threashold levels, see datasheet for values */
192*4882a593Smuzhiyun         unsigned int jd_scthr:2;
193*4882a593Smuzhiyun         unsigned int jd_thr:2;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	/* Configure WM1811 jack detection for use with external capacitor */
196*4882a593Smuzhiyun 	unsigned int jd_ext_cap:1;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	/* WM8958 microphone bias configuration */
199*4882a593Smuzhiyun 	int micbias[2];
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	/* WM8958 microphone detection ranges */
202*4882a593Smuzhiyun 	u16 micd_lvl_sel;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	/* Disable the internal pull downs on the LDOs if they are
205*4882a593Smuzhiyun 	 * always driven (eg, connected to an always on supply or
206*4882a593Smuzhiyun 	 * GPIO that always drives an output.  If they float power
207*4882a593Smuzhiyun 	 * consumption will rise.
208*4882a593Smuzhiyun 	 */
209*4882a593Smuzhiyun 	bool ldo_ena_always_driven;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	/*
212*4882a593Smuzhiyun 	 * SPKMODE must be pulled internally by the device on this
213*4882a593Smuzhiyun 	 * system.
214*4882a593Smuzhiyun 	 */
215*4882a593Smuzhiyun 	bool spkmode_pu;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	/*
218*4882a593Smuzhiyun 	 * CS/ADDR must be pulled internally by the device on this
219*4882a593Smuzhiyun 	 * system.
220*4882a593Smuzhiyun 	 */
221*4882a593Smuzhiyun 	bool csnaddr_pd;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	/**
224*4882a593Smuzhiyun 	 * Maximum number of channels clocks will be generated for,
225*4882a593Smuzhiyun 	 * useful for systems where and I2S bus with multiple data
226*4882a593Smuzhiyun 	 * lines is mastered.
227*4882a593Smuzhiyun 	 */
228*4882a593Smuzhiyun 	int max_channels_clocked[WM8994_NUM_AIF];
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	/**
231*4882a593Smuzhiyun 	 * GPIO for the IRQ pin if host only supports edge triggering
232*4882a593Smuzhiyun 	 */
233*4882a593Smuzhiyun 	int irq_gpio;
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun #endif
237