xref: /OK3568_Linux_fs/kernel/include/linux/mfd/wm8400-audio.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * wm8400 private definitions for audio
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2008 Wolfson Microelectronics plc
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __LINUX_MFD_WM8400_AUDIO_H
9*4882a593Smuzhiyun #define __LINUX_MFD_WM8400_AUDIO_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/mfd/wm8400-audio.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun  * R2 (0x02) - Power Management (1)
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun #define WM8400_CODEC_ENA                        0x8000  /* CODEC_ENA */
17*4882a593Smuzhiyun #define WM8400_CODEC_ENA_MASK                   0x8000  /* CODEC_ENA */
18*4882a593Smuzhiyun #define WM8400_CODEC_ENA_SHIFT                      15  /* CODEC_ENA */
19*4882a593Smuzhiyun #define WM8400_CODEC_ENA_WIDTH                       1  /* CODEC_ENA */
20*4882a593Smuzhiyun #define WM8400_SYSCLK_ENA                       0x4000  /* SYSCLK_ENA */
21*4882a593Smuzhiyun #define WM8400_SYSCLK_ENA_MASK                  0x4000  /* SYSCLK_ENA */
22*4882a593Smuzhiyun #define WM8400_SYSCLK_ENA_SHIFT                     14  /* SYSCLK_ENA */
23*4882a593Smuzhiyun #define WM8400_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
24*4882a593Smuzhiyun #define WM8400_SPK_MIX_ENA                      0x2000  /* SPK_MIX_ENA */
25*4882a593Smuzhiyun #define WM8400_SPK_MIX_ENA_MASK                 0x2000  /* SPK_MIX_ENA */
26*4882a593Smuzhiyun #define WM8400_SPK_MIX_ENA_SHIFT                    13  /* SPK_MIX_ENA */
27*4882a593Smuzhiyun #define WM8400_SPK_MIX_ENA_WIDTH                     1  /* SPK_MIX_ENA */
28*4882a593Smuzhiyun #define WM8400_SPK_ENA                          0x1000  /* SPK_ENA */
29*4882a593Smuzhiyun #define WM8400_SPK_ENA_MASK                     0x1000  /* SPK_ENA */
30*4882a593Smuzhiyun #define WM8400_SPK_ENA_SHIFT                        12  /* SPK_ENA */
31*4882a593Smuzhiyun #define WM8400_SPK_ENA_WIDTH                         1  /* SPK_ENA */
32*4882a593Smuzhiyun #define WM8400_OUT3_ENA                         0x0800  /* OUT3_ENA */
33*4882a593Smuzhiyun #define WM8400_OUT3_ENA_MASK                    0x0800  /* OUT3_ENA */
34*4882a593Smuzhiyun #define WM8400_OUT3_ENA_SHIFT                       11  /* OUT3_ENA */
35*4882a593Smuzhiyun #define WM8400_OUT3_ENA_WIDTH                        1  /* OUT3_ENA */
36*4882a593Smuzhiyun #define WM8400_OUT4_ENA                         0x0400  /* OUT4_ENA */
37*4882a593Smuzhiyun #define WM8400_OUT4_ENA_MASK                    0x0400  /* OUT4_ENA */
38*4882a593Smuzhiyun #define WM8400_OUT4_ENA_SHIFT                       10  /* OUT4_ENA */
39*4882a593Smuzhiyun #define WM8400_OUT4_ENA_WIDTH                        1  /* OUT4_ENA */
40*4882a593Smuzhiyun #define WM8400_LOUT_ENA                         0x0200  /* LOUT_ENA */
41*4882a593Smuzhiyun #define WM8400_LOUT_ENA_MASK                    0x0200  /* LOUT_ENA */
42*4882a593Smuzhiyun #define WM8400_LOUT_ENA_SHIFT                        9  /* LOUT_ENA */
43*4882a593Smuzhiyun #define WM8400_LOUT_ENA_WIDTH                        1  /* LOUT_ENA */
44*4882a593Smuzhiyun #define WM8400_ROUT_ENA                         0x0100  /* ROUT_ENA */
45*4882a593Smuzhiyun #define WM8400_ROUT_ENA_MASK                    0x0100  /* ROUT_ENA */
46*4882a593Smuzhiyun #define WM8400_ROUT_ENA_SHIFT                        8  /* ROUT_ENA */
47*4882a593Smuzhiyun #define WM8400_ROUT_ENA_WIDTH                        1  /* ROUT_ENA */
48*4882a593Smuzhiyun #define WM8400_MIC1BIAS_ENA                     0x0010  /* MIC1BIAS_ENA */
49*4882a593Smuzhiyun #define WM8400_MIC1BIAS_ENA_MASK                0x0010  /* MIC1BIAS_ENA */
50*4882a593Smuzhiyun #define WM8400_MIC1BIAS_ENA_SHIFT                    4  /* MIC1BIAS_ENA */
51*4882a593Smuzhiyun #define WM8400_MIC1BIAS_ENA_WIDTH                    1  /* MIC1BIAS_ENA */
52*4882a593Smuzhiyun #define WM8400_VMID_MODE_MASK                   0x0006  /* VMID_MODE - [2:1] */
53*4882a593Smuzhiyun #define WM8400_VMID_MODE_SHIFT                       1  /* VMID_MODE - [2:1] */
54*4882a593Smuzhiyun #define WM8400_VMID_MODE_WIDTH                       2  /* VMID_MODE - [2:1] */
55*4882a593Smuzhiyun #define WM8400_VREF_ENA                         0x0001  /* VREF_ENA */
56*4882a593Smuzhiyun #define WM8400_VREF_ENA_MASK                    0x0001  /* VREF_ENA */
57*4882a593Smuzhiyun #define WM8400_VREF_ENA_SHIFT                        0  /* VREF_ENA */
58*4882a593Smuzhiyun #define WM8400_VREF_ENA_WIDTH                        1  /* VREF_ENA */
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun  * R3 (0x03) - Power Management (2)
62*4882a593Smuzhiyun  */
63*4882a593Smuzhiyun #define WM8400_FLL_ENA                          0x8000  /* FLL_ENA */
64*4882a593Smuzhiyun #define WM8400_FLL_ENA_MASK                     0x8000  /* FLL_ENA */
65*4882a593Smuzhiyun #define WM8400_FLL_ENA_SHIFT                        15  /* FLL_ENA */
66*4882a593Smuzhiyun #define WM8400_FLL_ENA_WIDTH                         1  /* FLL_ENA */
67*4882a593Smuzhiyun #define WM8400_TSHUT_ENA                        0x4000  /* TSHUT_ENA */
68*4882a593Smuzhiyun #define WM8400_TSHUT_ENA_MASK                   0x4000  /* TSHUT_ENA */
69*4882a593Smuzhiyun #define WM8400_TSHUT_ENA_SHIFT                      14  /* TSHUT_ENA */
70*4882a593Smuzhiyun #define WM8400_TSHUT_ENA_WIDTH                       1  /* TSHUT_ENA */
71*4882a593Smuzhiyun #define WM8400_TSHUT_OPDIS                      0x2000  /* TSHUT_OPDIS */
72*4882a593Smuzhiyun #define WM8400_TSHUT_OPDIS_MASK                 0x2000  /* TSHUT_OPDIS */
73*4882a593Smuzhiyun #define WM8400_TSHUT_OPDIS_SHIFT                    13  /* TSHUT_OPDIS */
74*4882a593Smuzhiyun #define WM8400_TSHUT_OPDIS_WIDTH                     1  /* TSHUT_OPDIS */
75*4882a593Smuzhiyun #define WM8400_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
76*4882a593Smuzhiyun #define WM8400_OPCLK_ENA_MASK                   0x0800  /* OPCLK_ENA */
77*4882a593Smuzhiyun #define WM8400_OPCLK_ENA_SHIFT                      11  /* OPCLK_ENA */
78*4882a593Smuzhiyun #define WM8400_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
79*4882a593Smuzhiyun #define WM8400_AINL_ENA                         0x0200  /* AINL_ENA */
80*4882a593Smuzhiyun #define WM8400_AINL_ENA_MASK                    0x0200  /* AINL_ENA */
81*4882a593Smuzhiyun #define WM8400_AINL_ENA_SHIFT                        9  /* AINL_ENA */
82*4882a593Smuzhiyun #define WM8400_AINL_ENA_WIDTH                        1  /* AINL_ENA */
83*4882a593Smuzhiyun #define WM8400_AINR_ENA                         0x0100  /* AINR_ENA */
84*4882a593Smuzhiyun #define WM8400_AINR_ENA_MASK                    0x0100  /* AINR_ENA */
85*4882a593Smuzhiyun #define WM8400_AINR_ENA_SHIFT                        8  /* AINR_ENA */
86*4882a593Smuzhiyun #define WM8400_AINR_ENA_WIDTH                        1  /* AINR_ENA */
87*4882a593Smuzhiyun #define WM8400_LIN34_ENA                        0x0080  /* LIN34_ENA */
88*4882a593Smuzhiyun #define WM8400_LIN34_ENA_MASK                   0x0080  /* LIN34_ENA */
89*4882a593Smuzhiyun #define WM8400_LIN34_ENA_SHIFT                       7  /* LIN34_ENA */
90*4882a593Smuzhiyun #define WM8400_LIN34_ENA_WIDTH                       1  /* LIN34_ENA */
91*4882a593Smuzhiyun #define WM8400_LIN12_ENA                        0x0040  /* LIN12_ENA */
92*4882a593Smuzhiyun #define WM8400_LIN12_ENA_MASK                   0x0040  /* LIN12_ENA */
93*4882a593Smuzhiyun #define WM8400_LIN12_ENA_SHIFT                       6  /* LIN12_ENA */
94*4882a593Smuzhiyun #define WM8400_LIN12_ENA_WIDTH                       1  /* LIN12_ENA */
95*4882a593Smuzhiyun #define WM8400_RIN34_ENA                        0x0020  /* RIN34_ENA */
96*4882a593Smuzhiyun #define WM8400_RIN34_ENA_MASK                   0x0020  /* RIN34_ENA */
97*4882a593Smuzhiyun #define WM8400_RIN34_ENA_SHIFT                       5  /* RIN34_ENA */
98*4882a593Smuzhiyun #define WM8400_RIN34_ENA_WIDTH                       1  /* RIN34_ENA */
99*4882a593Smuzhiyun #define WM8400_RIN12_ENA                        0x0010  /* RIN12_ENA */
100*4882a593Smuzhiyun #define WM8400_RIN12_ENA_MASK                   0x0010  /* RIN12_ENA */
101*4882a593Smuzhiyun #define WM8400_RIN12_ENA_SHIFT                       4  /* RIN12_ENA */
102*4882a593Smuzhiyun #define WM8400_RIN12_ENA_WIDTH                       1  /* RIN12_ENA */
103*4882a593Smuzhiyun #define WM8400_ADCL_ENA                         0x0002  /* ADCL_ENA */
104*4882a593Smuzhiyun #define WM8400_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
105*4882a593Smuzhiyun #define WM8400_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
106*4882a593Smuzhiyun #define WM8400_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
107*4882a593Smuzhiyun #define WM8400_ADCR_ENA                         0x0001  /* ADCR_ENA */
108*4882a593Smuzhiyun #define WM8400_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
109*4882a593Smuzhiyun #define WM8400_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
110*4882a593Smuzhiyun #define WM8400_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun  * R4 (0x04) - Power Management (3)
114*4882a593Smuzhiyun  */
115*4882a593Smuzhiyun #define WM8400_LON_ENA                          0x2000  /* LON_ENA */
116*4882a593Smuzhiyun #define WM8400_LON_ENA_MASK                     0x2000  /* LON_ENA */
117*4882a593Smuzhiyun #define WM8400_LON_ENA_SHIFT                        13  /* LON_ENA */
118*4882a593Smuzhiyun #define WM8400_LON_ENA_WIDTH                         1  /* LON_ENA */
119*4882a593Smuzhiyun #define WM8400_LOP_ENA                          0x1000  /* LOP_ENA */
120*4882a593Smuzhiyun #define WM8400_LOP_ENA_MASK                     0x1000  /* LOP_ENA */
121*4882a593Smuzhiyun #define WM8400_LOP_ENA_SHIFT                        12  /* LOP_ENA */
122*4882a593Smuzhiyun #define WM8400_LOP_ENA_WIDTH                         1  /* LOP_ENA */
123*4882a593Smuzhiyun #define WM8400_RON_ENA                          0x0800  /* RON_ENA */
124*4882a593Smuzhiyun #define WM8400_RON_ENA_MASK                     0x0800  /* RON_ENA */
125*4882a593Smuzhiyun #define WM8400_RON_ENA_SHIFT                        11  /* RON_ENA */
126*4882a593Smuzhiyun #define WM8400_RON_ENA_WIDTH                         1  /* RON_ENA */
127*4882a593Smuzhiyun #define WM8400_ROP_ENA                          0x0400  /* ROP_ENA */
128*4882a593Smuzhiyun #define WM8400_ROP_ENA_MASK                     0x0400  /* ROP_ENA */
129*4882a593Smuzhiyun #define WM8400_ROP_ENA_SHIFT                        10  /* ROP_ENA */
130*4882a593Smuzhiyun #define WM8400_ROP_ENA_WIDTH                         1  /* ROP_ENA */
131*4882a593Smuzhiyun #define WM8400_LOPGA_ENA                        0x0080  /* LOPGA_ENA */
132*4882a593Smuzhiyun #define WM8400_LOPGA_ENA_MASK                   0x0080  /* LOPGA_ENA */
133*4882a593Smuzhiyun #define WM8400_LOPGA_ENA_SHIFT                       7  /* LOPGA_ENA */
134*4882a593Smuzhiyun #define WM8400_LOPGA_ENA_WIDTH                       1  /* LOPGA_ENA */
135*4882a593Smuzhiyun #define WM8400_ROPGA_ENA                        0x0040  /* ROPGA_ENA */
136*4882a593Smuzhiyun #define WM8400_ROPGA_ENA_MASK                   0x0040  /* ROPGA_ENA */
137*4882a593Smuzhiyun #define WM8400_ROPGA_ENA_SHIFT                       6  /* ROPGA_ENA */
138*4882a593Smuzhiyun #define WM8400_ROPGA_ENA_WIDTH                       1  /* ROPGA_ENA */
139*4882a593Smuzhiyun #define WM8400_LOMIX_ENA                        0x0020  /* LOMIX_ENA */
140*4882a593Smuzhiyun #define WM8400_LOMIX_ENA_MASK                   0x0020  /* LOMIX_ENA */
141*4882a593Smuzhiyun #define WM8400_LOMIX_ENA_SHIFT                       5  /* LOMIX_ENA */
142*4882a593Smuzhiyun #define WM8400_LOMIX_ENA_WIDTH                       1  /* LOMIX_ENA */
143*4882a593Smuzhiyun #define WM8400_ROMIX_ENA                        0x0010  /* ROMIX_ENA */
144*4882a593Smuzhiyun #define WM8400_ROMIX_ENA_MASK                   0x0010  /* ROMIX_ENA */
145*4882a593Smuzhiyun #define WM8400_ROMIX_ENA_SHIFT                       4  /* ROMIX_ENA */
146*4882a593Smuzhiyun #define WM8400_ROMIX_ENA_WIDTH                       1  /* ROMIX_ENA */
147*4882a593Smuzhiyun #define WM8400_DACL_ENA                         0x0002  /* DACL_ENA */
148*4882a593Smuzhiyun #define WM8400_DACL_ENA_MASK                    0x0002  /* DACL_ENA */
149*4882a593Smuzhiyun #define WM8400_DACL_ENA_SHIFT                        1  /* DACL_ENA */
150*4882a593Smuzhiyun #define WM8400_DACL_ENA_WIDTH                        1  /* DACL_ENA */
151*4882a593Smuzhiyun #define WM8400_DACR_ENA                         0x0001  /* DACR_ENA */
152*4882a593Smuzhiyun #define WM8400_DACR_ENA_MASK                    0x0001  /* DACR_ENA */
153*4882a593Smuzhiyun #define WM8400_DACR_ENA_SHIFT                        0  /* DACR_ENA */
154*4882a593Smuzhiyun #define WM8400_DACR_ENA_WIDTH                        1  /* DACR_ENA */
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun /*
157*4882a593Smuzhiyun  * R5 (0x05) - Audio Interface (1)
158*4882a593Smuzhiyun  */
159*4882a593Smuzhiyun #define WM8400_AIFADCL_SRC                      0x8000  /* AIFADCL_SRC */
160*4882a593Smuzhiyun #define WM8400_AIFADCL_SRC_MASK                 0x8000  /* AIFADCL_SRC */
161*4882a593Smuzhiyun #define WM8400_AIFADCL_SRC_SHIFT                    15  /* AIFADCL_SRC */
162*4882a593Smuzhiyun #define WM8400_AIFADCL_SRC_WIDTH                     1  /* AIFADCL_SRC */
163*4882a593Smuzhiyun #define WM8400_AIFADCR_SRC                      0x4000  /* AIFADCR_SRC */
164*4882a593Smuzhiyun #define WM8400_AIFADCR_SRC_MASK                 0x4000  /* AIFADCR_SRC */
165*4882a593Smuzhiyun #define WM8400_AIFADCR_SRC_SHIFT                    14  /* AIFADCR_SRC */
166*4882a593Smuzhiyun #define WM8400_AIFADCR_SRC_WIDTH                     1  /* AIFADCR_SRC */
167*4882a593Smuzhiyun #define WM8400_AIFADC_TDM                       0x2000  /* AIFADC_TDM */
168*4882a593Smuzhiyun #define WM8400_AIFADC_TDM_MASK                  0x2000  /* AIFADC_TDM */
169*4882a593Smuzhiyun #define WM8400_AIFADC_TDM_SHIFT                     13  /* AIFADC_TDM */
170*4882a593Smuzhiyun #define WM8400_AIFADC_TDM_WIDTH                      1  /* AIFADC_TDM */
171*4882a593Smuzhiyun #define WM8400_AIFADC_TDM_CHAN                  0x1000  /* AIFADC_TDM_CHAN */
172*4882a593Smuzhiyun #define WM8400_AIFADC_TDM_CHAN_MASK             0x1000  /* AIFADC_TDM_CHAN */
173*4882a593Smuzhiyun #define WM8400_AIFADC_TDM_CHAN_SHIFT                12  /* AIFADC_TDM_CHAN */
174*4882a593Smuzhiyun #define WM8400_AIFADC_TDM_CHAN_WIDTH                 1  /* AIFADC_TDM_CHAN */
175*4882a593Smuzhiyun #define WM8400_AIF_BCLK_INV                     0x0100  /* AIF_BCLK_INV */
176*4882a593Smuzhiyun #define WM8400_AIF_BCLK_INV_MASK                0x0100  /* AIF_BCLK_INV */
177*4882a593Smuzhiyun #define WM8400_AIF_BCLK_INV_SHIFT                    8  /* AIF_BCLK_INV */
178*4882a593Smuzhiyun #define WM8400_AIF_BCLK_INV_WIDTH                    1  /* AIF_BCLK_INV */
179*4882a593Smuzhiyun #define WM8400_AIF_LRCLK_INV                    0x0080  /* AIF_LRCLK_INV */
180*4882a593Smuzhiyun #define WM8400_AIF_LRCLK_INV_MASK               0x0080  /* AIF_LRCLK_INV */
181*4882a593Smuzhiyun #define WM8400_AIF_LRCLK_INV_SHIFT                   7  /* AIF_LRCLK_INV */
182*4882a593Smuzhiyun #define WM8400_AIF_LRCLK_INV_WIDTH                   1  /* AIF_LRCLK_INV */
183*4882a593Smuzhiyun #define WM8400_AIF_WL_MASK                      0x0060  /* AIF_WL - [6:5] */
184*4882a593Smuzhiyun #define WM8400_AIF_WL_SHIFT                          5  /* AIF_WL - [6:5] */
185*4882a593Smuzhiyun #define WM8400_AIF_WL_WIDTH                          2  /* AIF_WL - [6:5] */
186*4882a593Smuzhiyun #define WM8400_AIF_WL_16BITS			(0 << 5)
187*4882a593Smuzhiyun #define WM8400_AIF_WL_20BITS			(1 << 5)
188*4882a593Smuzhiyun #define WM8400_AIF_WL_24BITS			(2 << 5)
189*4882a593Smuzhiyun #define WM8400_AIF_WL_32BITS			(3 << 5)
190*4882a593Smuzhiyun #define WM8400_AIF_FMT_MASK                     0x0018  /* AIF_FMT - [4:3] */
191*4882a593Smuzhiyun #define WM8400_AIF_FMT_SHIFT                         3  /* AIF_FMT - [4:3] */
192*4882a593Smuzhiyun #define WM8400_AIF_FMT_WIDTH                         2  /* AIF_FMT - [4:3] */
193*4882a593Smuzhiyun #define WM8400_AIF_FMT_RIGHTJ			(0 << 3)
194*4882a593Smuzhiyun #define WM8400_AIF_FMT_LEFTJ			(1 << 3)
195*4882a593Smuzhiyun #define WM8400_AIF_FMT_I2S			(2 << 3)
196*4882a593Smuzhiyun #define WM8400_AIF_FMT_DSP			(3 << 3)
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun /*
199*4882a593Smuzhiyun  * R6 (0x06) - Audio Interface (2)
200*4882a593Smuzhiyun  */
201*4882a593Smuzhiyun #define WM8400_DACL_SRC                         0x8000  /* DACL_SRC */
202*4882a593Smuzhiyun #define WM8400_DACL_SRC_MASK                    0x8000  /* DACL_SRC */
203*4882a593Smuzhiyun #define WM8400_DACL_SRC_SHIFT                       15  /* DACL_SRC */
204*4882a593Smuzhiyun #define WM8400_DACL_SRC_WIDTH                        1  /* DACL_SRC */
205*4882a593Smuzhiyun #define WM8400_DACR_SRC                         0x4000  /* DACR_SRC */
206*4882a593Smuzhiyun #define WM8400_DACR_SRC_MASK                    0x4000  /* DACR_SRC */
207*4882a593Smuzhiyun #define WM8400_DACR_SRC_SHIFT                       14  /* DACR_SRC */
208*4882a593Smuzhiyun #define WM8400_DACR_SRC_WIDTH                        1  /* DACR_SRC */
209*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM                       0x2000  /* AIFDAC_TDM */
210*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM_MASK                  0x2000  /* AIFDAC_TDM */
211*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM_SHIFT                     13  /* AIFDAC_TDM */
212*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM_WIDTH                      1  /* AIFDAC_TDM */
213*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM_CHAN                  0x1000  /* AIFDAC_TDM_CHAN */
214*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM_CHAN_MASK             0x1000  /* AIFDAC_TDM_CHAN */
215*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM_CHAN_SHIFT                12  /* AIFDAC_TDM_CHAN */
216*4882a593Smuzhiyun #define WM8400_AIFDAC_TDM_CHAN_WIDTH                 1  /* AIFDAC_TDM_CHAN */
217*4882a593Smuzhiyun #define WM8400_DAC_BOOST_MASK                   0x0C00  /* DAC_BOOST - [11:10] */
218*4882a593Smuzhiyun #define WM8400_DAC_BOOST_SHIFT                      10  /* DAC_BOOST - [11:10] */
219*4882a593Smuzhiyun #define WM8400_DAC_BOOST_WIDTH                       2  /* DAC_BOOST - [11:10] */
220*4882a593Smuzhiyun #define WM8400_DAC_COMP                         0x0010  /* DAC_COMP */
221*4882a593Smuzhiyun #define WM8400_DAC_COMP_MASK                    0x0010  /* DAC_COMP */
222*4882a593Smuzhiyun #define WM8400_DAC_COMP_SHIFT                        4  /* DAC_COMP */
223*4882a593Smuzhiyun #define WM8400_DAC_COMP_WIDTH                        1  /* DAC_COMP */
224*4882a593Smuzhiyun #define WM8400_DAC_COMPMODE                     0x0008  /* DAC_COMPMODE */
225*4882a593Smuzhiyun #define WM8400_DAC_COMPMODE_MASK                0x0008  /* DAC_COMPMODE */
226*4882a593Smuzhiyun #define WM8400_DAC_COMPMODE_SHIFT                    3  /* DAC_COMPMODE */
227*4882a593Smuzhiyun #define WM8400_DAC_COMPMODE_WIDTH                    1  /* DAC_COMPMODE */
228*4882a593Smuzhiyun #define WM8400_ADC_COMP                         0x0004  /* ADC_COMP */
229*4882a593Smuzhiyun #define WM8400_ADC_COMP_MASK                    0x0004  /* ADC_COMP */
230*4882a593Smuzhiyun #define WM8400_ADC_COMP_SHIFT                        2  /* ADC_COMP */
231*4882a593Smuzhiyun #define WM8400_ADC_COMP_WIDTH                        1  /* ADC_COMP */
232*4882a593Smuzhiyun #define WM8400_ADC_COMPMODE                     0x0002  /* ADC_COMPMODE */
233*4882a593Smuzhiyun #define WM8400_ADC_COMPMODE_MASK                0x0002  /* ADC_COMPMODE */
234*4882a593Smuzhiyun #define WM8400_ADC_COMPMODE_SHIFT                    1  /* ADC_COMPMODE */
235*4882a593Smuzhiyun #define WM8400_ADC_COMPMODE_WIDTH                    1  /* ADC_COMPMODE */
236*4882a593Smuzhiyun #define WM8400_LOOPBACK                         0x0001  /* LOOPBACK */
237*4882a593Smuzhiyun #define WM8400_LOOPBACK_MASK                    0x0001  /* LOOPBACK */
238*4882a593Smuzhiyun #define WM8400_LOOPBACK_SHIFT                        0  /* LOOPBACK */
239*4882a593Smuzhiyun #define WM8400_LOOPBACK_WIDTH                        1  /* LOOPBACK */
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun /*
242*4882a593Smuzhiyun  * R7 (0x07) - Clocking (1)
243*4882a593Smuzhiyun  */
244*4882a593Smuzhiyun #define WM8400_TOCLK_RATE                       0x8000  /* TOCLK_RATE */
245*4882a593Smuzhiyun #define WM8400_TOCLK_RATE_MASK                  0x8000  /* TOCLK_RATE */
246*4882a593Smuzhiyun #define WM8400_TOCLK_RATE_SHIFT                     15  /* TOCLK_RATE */
247*4882a593Smuzhiyun #define WM8400_TOCLK_RATE_WIDTH                      1  /* TOCLK_RATE */
248*4882a593Smuzhiyun #define WM8400_TOCLK_ENA                        0x4000  /* TOCLK_ENA */
249*4882a593Smuzhiyun #define WM8400_TOCLK_ENA_MASK                   0x4000  /* TOCLK_ENA */
250*4882a593Smuzhiyun #define WM8400_TOCLK_ENA_SHIFT                      14  /* TOCLK_ENA */
251*4882a593Smuzhiyun #define WM8400_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
252*4882a593Smuzhiyun #define WM8400_OPCLKDIV_MASK                    0x1E00  /* OPCLKDIV - [12:9] */
253*4882a593Smuzhiyun #define WM8400_OPCLKDIV_SHIFT                        9  /* OPCLKDIV - [12:9] */
254*4882a593Smuzhiyun #define WM8400_OPCLKDIV_WIDTH                        4  /* OPCLKDIV - [12:9] */
255*4882a593Smuzhiyun #define WM8400_DCLKDIV_MASK                     0x01C0  /* DCLKDIV - [8:6] */
256*4882a593Smuzhiyun #define WM8400_DCLKDIV_SHIFT                         6  /* DCLKDIV - [8:6] */
257*4882a593Smuzhiyun #define WM8400_DCLKDIV_WIDTH                         3  /* DCLKDIV - [8:6] */
258*4882a593Smuzhiyun #define WM8400_BCLK_DIV_MASK                    0x001E  /* BCLK_DIV - [4:1] */
259*4882a593Smuzhiyun #define WM8400_BCLK_DIV_SHIFT                        1  /* BCLK_DIV - [4:1] */
260*4882a593Smuzhiyun #define WM8400_BCLK_DIV_WIDTH                        4  /* BCLK_DIV - [4:1] */
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun /*
263*4882a593Smuzhiyun  * R8 (0x08) - Clocking (2)
264*4882a593Smuzhiyun  */
265*4882a593Smuzhiyun #define WM8400_MCLK_SRC                         0x8000  /* MCLK_SRC */
266*4882a593Smuzhiyun #define WM8400_MCLK_SRC_MASK                    0x8000  /* MCLK_SRC */
267*4882a593Smuzhiyun #define WM8400_MCLK_SRC_SHIFT                       15  /* MCLK_SRC */
268*4882a593Smuzhiyun #define WM8400_MCLK_SRC_WIDTH                        1  /* MCLK_SRC */
269*4882a593Smuzhiyun #define WM8400_SYSCLK_SRC                       0x4000  /* SYSCLK_SRC */
270*4882a593Smuzhiyun #define WM8400_SYSCLK_SRC_MASK                  0x4000  /* SYSCLK_SRC */
271*4882a593Smuzhiyun #define WM8400_SYSCLK_SRC_SHIFT                     14  /* SYSCLK_SRC */
272*4882a593Smuzhiyun #define WM8400_SYSCLK_SRC_WIDTH                      1  /* SYSCLK_SRC */
273*4882a593Smuzhiyun #define WM8400_CLK_FORCE                        0x2000  /* CLK_FORCE */
274*4882a593Smuzhiyun #define WM8400_CLK_FORCE_MASK                   0x2000  /* CLK_FORCE */
275*4882a593Smuzhiyun #define WM8400_CLK_FORCE_SHIFT                      13  /* CLK_FORCE */
276*4882a593Smuzhiyun #define WM8400_CLK_FORCE_WIDTH                       1  /* CLK_FORCE */
277*4882a593Smuzhiyun #define WM8400_MCLK_DIV_MASK                    0x1800  /* MCLK_DIV - [12:11] */
278*4882a593Smuzhiyun #define WM8400_MCLK_DIV_SHIFT                       11  /* MCLK_DIV - [12:11] */
279*4882a593Smuzhiyun #define WM8400_MCLK_DIV_WIDTH                        2  /* MCLK_DIV - [12:11] */
280*4882a593Smuzhiyun #define WM8400_MCLK_INV                         0x0400  /* MCLK_INV */
281*4882a593Smuzhiyun #define WM8400_MCLK_INV_MASK                    0x0400  /* MCLK_INV */
282*4882a593Smuzhiyun #define WM8400_MCLK_INV_SHIFT                       10  /* MCLK_INV */
283*4882a593Smuzhiyun #define WM8400_MCLK_INV_WIDTH                        1  /* MCLK_INV */
284*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_MASK                  0x00E0  /* ADC_CLKDIV - [7:5] */
285*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_SHIFT                      5  /* ADC_CLKDIV - [7:5] */
286*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_WIDTH                      3  /* ADC_CLKDIV - [7:5] */
287*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_MASK                  0x001C  /* DAC_CLKDIV - [4:2] */
288*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_SHIFT                      2  /* DAC_CLKDIV - [4:2] */
289*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_WIDTH                      3  /* DAC_CLKDIV - [4:2] */
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun /*
292*4882a593Smuzhiyun  * R9 (0x09) - Audio Interface (3)
293*4882a593Smuzhiyun  */
294*4882a593Smuzhiyun #define WM8400_AIF_MSTR1                        0x8000  /* AIF_MSTR1 */
295*4882a593Smuzhiyun #define WM8400_AIF_MSTR1_MASK                   0x8000  /* AIF_MSTR1 */
296*4882a593Smuzhiyun #define WM8400_AIF_MSTR1_SHIFT                      15  /* AIF_MSTR1 */
297*4882a593Smuzhiyun #define WM8400_AIF_MSTR1_WIDTH                       1  /* AIF_MSTR1 */
298*4882a593Smuzhiyun #define WM8400_AIF_MSTR2                        0x4000  /* AIF_MSTR2 */
299*4882a593Smuzhiyun #define WM8400_AIF_MSTR2_MASK                   0x4000  /* AIF_MSTR2 */
300*4882a593Smuzhiyun #define WM8400_AIF_MSTR2_SHIFT                      14  /* AIF_MSTR2 */
301*4882a593Smuzhiyun #define WM8400_AIF_MSTR2_WIDTH                       1  /* AIF_MSTR2 */
302*4882a593Smuzhiyun #define WM8400_AIF_SEL                          0x2000  /* AIF_SEL */
303*4882a593Smuzhiyun #define WM8400_AIF_SEL_MASK                     0x2000  /* AIF_SEL */
304*4882a593Smuzhiyun #define WM8400_AIF_SEL_SHIFT                        13  /* AIF_SEL */
305*4882a593Smuzhiyun #define WM8400_AIF_SEL_WIDTH                         1  /* AIF_SEL */
306*4882a593Smuzhiyun #define WM8400_ADCLRC_DIR                       0x0800  /* ADCLRC_DIR */
307*4882a593Smuzhiyun #define WM8400_ADCLRC_DIR_MASK                  0x0800  /* ADCLRC_DIR */
308*4882a593Smuzhiyun #define WM8400_ADCLRC_DIR_SHIFT                     11  /* ADCLRC_DIR */
309*4882a593Smuzhiyun #define WM8400_ADCLRC_DIR_WIDTH                      1  /* ADCLRC_DIR */
310*4882a593Smuzhiyun #define WM8400_ADCLRC_RATE_MASK                 0x07FF  /* ADCLRC_RATE - [10:0] */
311*4882a593Smuzhiyun #define WM8400_ADCLRC_RATE_SHIFT                     0  /* ADCLRC_RATE - [10:0] */
312*4882a593Smuzhiyun #define WM8400_ADCLRC_RATE_WIDTH                    11  /* ADCLRC_RATE - [10:0] */
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun /*
315*4882a593Smuzhiyun  * R10 (0x0A) - Audio Interface (4)
316*4882a593Smuzhiyun  */
317*4882a593Smuzhiyun #define WM8400_ALRCGPIO1                        0x8000  /* ALRCGPIO1 */
318*4882a593Smuzhiyun #define WM8400_ALRCGPIO1_MASK                   0x8000  /* ALRCGPIO1 */
319*4882a593Smuzhiyun #define WM8400_ALRCGPIO1_SHIFT                      15  /* ALRCGPIO1 */
320*4882a593Smuzhiyun #define WM8400_ALRCGPIO1_WIDTH                       1  /* ALRCGPIO1 */
321*4882a593Smuzhiyun #define WM8400_ALRCBGPIO6                       0x4000  /* ALRCBGPIO6 */
322*4882a593Smuzhiyun #define WM8400_ALRCBGPIO6_MASK                  0x4000  /* ALRCBGPIO6 */
323*4882a593Smuzhiyun #define WM8400_ALRCBGPIO6_SHIFT                     14  /* ALRCBGPIO6 */
324*4882a593Smuzhiyun #define WM8400_ALRCBGPIO6_WIDTH                      1  /* ALRCBGPIO6 */
325*4882a593Smuzhiyun #define WM8400_AIF_TRIS                         0x2000  /* AIF_TRIS */
326*4882a593Smuzhiyun #define WM8400_AIF_TRIS_MASK                    0x2000  /* AIF_TRIS */
327*4882a593Smuzhiyun #define WM8400_AIF_TRIS_SHIFT                       13  /* AIF_TRIS */
328*4882a593Smuzhiyun #define WM8400_AIF_TRIS_WIDTH                        1  /* AIF_TRIS */
329*4882a593Smuzhiyun #define WM8400_DACLRC_DIR                       0x0800  /* DACLRC_DIR */
330*4882a593Smuzhiyun #define WM8400_DACLRC_DIR_MASK                  0x0800  /* DACLRC_DIR */
331*4882a593Smuzhiyun #define WM8400_DACLRC_DIR_SHIFT                     11  /* DACLRC_DIR */
332*4882a593Smuzhiyun #define WM8400_DACLRC_DIR_WIDTH                      1  /* DACLRC_DIR */
333*4882a593Smuzhiyun #define WM8400_DACLRC_RATE_MASK                 0x07FF  /* DACLRC_RATE - [10:0] */
334*4882a593Smuzhiyun #define WM8400_DACLRC_RATE_SHIFT                     0  /* DACLRC_RATE - [10:0] */
335*4882a593Smuzhiyun #define WM8400_DACLRC_RATE_WIDTH                    11  /* DACLRC_RATE - [10:0] */
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun /*
338*4882a593Smuzhiyun  * R11 (0x0B) - DAC CTRL
339*4882a593Smuzhiyun  */
340*4882a593Smuzhiyun #define WM8400_DAC_SDMCLK_RATE                  0x2000  /* DAC_SDMCLK_RATE */
341*4882a593Smuzhiyun #define WM8400_DAC_SDMCLK_RATE_MASK             0x2000  /* DAC_SDMCLK_RATE */
342*4882a593Smuzhiyun #define WM8400_DAC_SDMCLK_RATE_SHIFT                13  /* DAC_SDMCLK_RATE */
343*4882a593Smuzhiyun #define WM8400_DAC_SDMCLK_RATE_WIDTH                 1  /* DAC_SDMCLK_RATE */
344*4882a593Smuzhiyun #define WM8400_AIF_LRCLKRATE                    0x0400  /* AIF_LRCLKRATE */
345*4882a593Smuzhiyun #define WM8400_AIF_LRCLKRATE_MASK               0x0400  /* AIF_LRCLKRATE */
346*4882a593Smuzhiyun #define WM8400_AIF_LRCLKRATE_SHIFT                  10  /* AIF_LRCLKRATE */
347*4882a593Smuzhiyun #define WM8400_AIF_LRCLKRATE_WIDTH                   1  /* AIF_LRCLKRATE */
348*4882a593Smuzhiyun #define WM8400_DAC_MONO                         0x0200  /* DAC_MONO */
349*4882a593Smuzhiyun #define WM8400_DAC_MONO_MASK                    0x0200  /* DAC_MONO */
350*4882a593Smuzhiyun #define WM8400_DAC_MONO_SHIFT                        9  /* DAC_MONO */
351*4882a593Smuzhiyun #define WM8400_DAC_MONO_WIDTH                        1  /* DAC_MONO */
352*4882a593Smuzhiyun #define WM8400_DAC_SB_FILT                      0x0100  /* DAC_SB_FILT */
353*4882a593Smuzhiyun #define WM8400_DAC_SB_FILT_MASK                 0x0100  /* DAC_SB_FILT */
354*4882a593Smuzhiyun #define WM8400_DAC_SB_FILT_SHIFT                     8  /* DAC_SB_FILT */
355*4882a593Smuzhiyun #define WM8400_DAC_SB_FILT_WIDTH                     1  /* DAC_SB_FILT */
356*4882a593Smuzhiyun #define WM8400_DAC_MUTERATE                     0x0080  /* DAC_MUTERATE */
357*4882a593Smuzhiyun #define WM8400_DAC_MUTERATE_MASK                0x0080  /* DAC_MUTERATE */
358*4882a593Smuzhiyun #define WM8400_DAC_MUTERATE_SHIFT                    7  /* DAC_MUTERATE */
359*4882a593Smuzhiyun #define WM8400_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
360*4882a593Smuzhiyun #define WM8400_DAC_MUTEMODE                     0x0040  /* DAC_MUTEMODE */
361*4882a593Smuzhiyun #define WM8400_DAC_MUTEMODE_MASK                0x0040  /* DAC_MUTEMODE */
362*4882a593Smuzhiyun #define WM8400_DAC_MUTEMODE_SHIFT                    6  /* DAC_MUTEMODE */
363*4882a593Smuzhiyun #define WM8400_DAC_MUTEMODE_WIDTH                    1  /* DAC_MUTEMODE */
364*4882a593Smuzhiyun #define WM8400_DEEMP_MASK                       0x0030  /* DEEMP - [5:4] */
365*4882a593Smuzhiyun #define WM8400_DEEMP_SHIFT                           4  /* DEEMP - [5:4] */
366*4882a593Smuzhiyun #define WM8400_DEEMP_WIDTH                           2  /* DEEMP - [5:4] */
367*4882a593Smuzhiyun #define WM8400_DAC_MUTE                         0x0004  /* DAC_MUTE */
368*4882a593Smuzhiyun #define WM8400_DAC_MUTE_MASK                    0x0004  /* DAC_MUTE */
369*4882a593Smuzhiyun #define WM8400_DAC_MUTE_SHIFT                        2  /* DAC_MUTE */
370*4882a593Smuzhiyun #define WM8400_DAC_MUTE_WIDTH                        1  /* DAC_MUTE */
371*4882a593Smuzhiyun #define WM8400_DACL_DATINV                      0x0002  /* DACL_DATINV */
372*4882a593Smuzhiyun #define WM8400_DACL_DATINV_MASK                 0x0002  /* DACL_DATINV */
373*4882a593Smuzhiyun #define WM8400_DACL_DATINV_SHIFT                     1  /* DACL_DATINV */
374*4882a593Smuzhiyun #define WM8400_DACL_DATINV_WIDTH                     1  /* DACL_DATINV */
375*4882a593Smuzhiyun #define WM8400_DACR_DATINV                      0x0001  /* DACR_DATINV */
376*4882a593Smuzhiyun #define WM8400_DACR_DATINV_MASK                 0x0001  /* DACR_DATINV */
377*4882a593Smuzhiyun #define WM8400_DACR_DATINV_SHIFT                     0  /* DACR_DATINV */
378*4882a593Smuzhiyun #define WM8400_DACR_DATINV_WIDTH                     1  /* DACR_DATINV */
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun /*
381*4882a593Smuzhiyun  * R12 (0x0C) - Left DAC Digital Volume
382*4882a593Smuzhiyun  */
383*4882a593Smuzhiyun #define WM8400_DAC_VU                           0x0100  /* DAC_VU */
384*4882a593Smuzhiyun #define WM8400_DAC_VU_MASK                      0x0100  /* DAC_VU */
385*4882a593Smuzhiyun #define WM8400_DAC_VU_SHIFT                          8  /* DAC_VU */
386*4882a593Smuzhiyun #define WM8400_DAC_VU_WIDTH                          1  /* DAC_VU */
387*4882a593Smuzhiyun #define WM8400_DACL_VOL_MASK                    0x00FF  /* DACL_VOL - [7:0] */
388*4882a593Smuzhiyun #define WM8400_DACL_VOL_SHIFT                        0  /* DACL_VOL - [7:0] */
389*4882a593Smuzhiyun #define WM8400_DACL_VOL_WIDTH                        8  /* DACL_VOL - [7:0] */
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun /*
392*4882a593Smuzhiyun  * R13 (0x0D) - Right DAC Digital Volume
393*4882a593Smuzhiyun  */
394*4882a593Smuzhiyun #define WM8400_DAC_VU                           0x0100  /* DAC_VU */
395*4882a593Smuzhiyun #define WM8400_DAC_VU_MASK                      0x0100  /* DAC_VU */
396*4882a593Smuzhiyun #define WM8400_DAC_VU_SHIFT                          8  /* DAC_VU */
397*4882a593Smuzhiyun #define WM8400_DAC_VU_WIDTH                          1  /* DAC_VU */
398*4882a593Smuzhiyun #define WM8400_DACR_VOL_MASK                    0x00FF  /* DACR_VOL - [7:0] */
399*4882a593Smuzhiyun #define WM8400_DACR_VOL_SHIFT                        0  /* DACR_VOL - [7:0] */
400*4882a593Smuzhiyun #define WM8400_DACR_VOL_WIDTH                        8  /* DACR_VOL - [7:0] */
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun /*
403*4882a593Smuzhiyun  * R14 (0x0E) - Digital Side Tone
404*4882a593Smuzhiyun  */
405*4882a593Smuzhiyun #define WM8400_ADCL_DAC_SVOL_MASK               0x1E00  /*   ADCL_DAC_SVOL - [12:9] */
406*4882a593Smuzhiyun #define WM8400_ADCL_DAC_SVOL_SHIFT                   9  /*   ADCL_DAC_SVOL - [12:9] */
407*4882a593Smuzhiyun #define WM8400_ADCL_DAC_SVOL_WIDTH                   4  /*   ADCL_DAC_SVOL - [12:9] */
408*4882a593Smuzhiyun #define WM8400_ADCR_DAC_SVOL_MASK               0x01E0  /* ADCR_DAC_SVOL - [8:5] */
409*4882a593Smuzhiyun #define WM8400_ADCR_DAC_SVOL_SHIFT                   5  /* ADCR_DAC_SVOL - [8:5] */
410*4882a593Smuzhiyun #define WM8400_ADCR_DAC_SVOL_WIDTH                   4  /* ADCR_DAC_SVOL - [8:5] */
411*4882a593Smuzhiyun #define WM8400_ADC_TO_DACL_MASK                 0x000C  /* ADC_TO_DACL - [3:2] */
412*4882a593Smuzhiyun #define WM8400_ADC_TO_DACL_SHIFT                     2  /* ADC_TO_DACL - [3:2] */
413*4882a593Smuzhiyun #define WM8400_ADC_TO_DACL_WIDTH                     2  /* ADC_TO_DACL - [3:2] */
414*4882a593Smuzhiyun #define WM8400_ADC_TO_DACR_MASK                 0x0003  /* ADC_TO_DACR - [1:0] */
415*4882a593Smuzhiyun #define WM8400_ADC_TO_DACR_SHIFT                     0  /* ADC_TO_DACR - [1:0] */
416*4882a593Smuzhiyun #define WM8400_ADC_TO_DACR_WIDTH                     2  /* ADC_TO_DACR - [1:0] */
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun /*
419*4882a593Smuzhiyun  * R15 (0x0F) - ADC CTRL
420*4882a593Smuzhiyun  */
421*4882a593Smuzhiyun #define WM8400_ADC_HPF_ENA                      0x0100  /* ADC_HPF_ENA */
422*4882a593Smuzhiyun #define WM8400_ADC_HPF_ENA_MASK                 0x0100  /* ADC_HPF_ENA */
423*4882a593Smuzhiyun #define WM8400_ADC_HPF_ENA_SHIFT                     8  /* ADC_HPF_ENA */
424*4882a593Smuzhiyun #define WM8400_ADC_HPF_ENA_WIDTH                     1  /* ADC_HPF_ENA */
425*4882a593Smuzhiyun #define WM8400_ADC_HPF_CUT_MASK                 0x0060  /* ADC_HPF_CUT - [6:5] */
426*4882a593Smuzhiyun #define WM8400_ADC_HPF_CUT_SHIFT                     5  /* ADC_HPF_CUT - [6:5] */
427*4882a593Smuzhiyun #define WM8400_ADC_HPF_CUT_WIDTH                     2  /* ADC_HPF_CUT - [6:5] */
428*4882a593Smuzhiyun #define WM8400_ADCL_DATINV                      0x0002  /* ADCL_DATINV */
429*4882a593Smuzhiyun #define WM8400_ADCL_DATINV_MASK                 0x0002  /* ADCL_DATINV */
430*4882a593Smuzhiyun #define WM8400_ADCL_DATINV_SHIFT                     1  /* ADCL_DATINV */
431*4882a593Smuzhiyun #define WM8400_ADCL_DATINV_WIDTH                     1  /* ADCL_DATINV */
432*4882a593Smuzhiyun #define WM8400_ADCR_DATINV                      0x0001  /* ADCR_DATINV */
433*4882a593Smuzhiyun #define WM8400_ADCR_DATINV_MASK                 0x0001  /* ADCR_DATINV */
434*4882a593Smuzhiyun #define WM8400_ADCR_DATINV_SHIFT                     0  /* ADCR_DATINV */
435*4882a593Smuzhiyun #define WM8400_ADCR_DATINV_WIDTH                     1  /* ADCR_DATINV */
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun /*
438*4882a593Smuzhiyun  * R16 (0x10) - Left ADC Digital Volume
439*4882a593Smuzhiyun  */
440*4882a593Smuzhiyun #define WM8400_ADC_VU                           0x0100  /* ADC_VU */
441*4882a593Smuzhiyun #define WM8400_ADC_VU_MASK                      0x0100  /* ADC_VU */
442*4882a593Smuzhiyun #define WM8400_ADC_VU_SHIFT                          8  /* ADC_VU */
443*4882a593Smuzhiyun #define WM8400_ADC_VU_WIDTH                          1  /* ADC_VU */
444*4882a593Smuzhiyun #define WM8400_ADCL_VOL_MASK                    0x00FF  /* ADCL_VOL - [7:0] */
445*4882a593Smuzhiyun #define WM8400_ADCL_VOL_SHIFT                        0  /* ADCL_VOL - [7:0] */
446*4882a593Smuzhiyun #define WM8400_ADCL_VOL_WIDTH                        8  /* ADCL_VOL - [7:0] */
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun /*
449*4882a593Smuzhiyun  * R17 (0x11) - Right ADC Digital Volume
450*4882a593Smuzhiyun  */
451*4882a593Smuzhiyun #define WM8400_ADC_VU                           0x0100  /* ADC_VU */
452*4882a593Smuzhiyun #define WM8400_ADC_VU_MASK                      0x0100  /* ADC_VU */
453*4882a593Smuzhiyun #define WM8400_ADC_VU_SHIFT                          8  /* ADC_VU */
454*4882a593Smuzhiyun #define WM8400_ADC_VU_WIDTH                          1  /* ADC_VU */
455*4882a593Smuzhiyun #define WM8400_ADCR_VOL_MASK                    0x00FF  /* ADCR_VOL - [7:0] */
456*4882a593Smuzhiyun #define WM8400_ADCR_VOL_SHIFT                        0  /* ADCR_VOL - [7:0] */
457*4882a593Smuzhiyun #define WM8400_ADCR_VOL_WIDTH                        8  /* ADCR_VOL - [7:0] */
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun /*
460*4882a593Smuzhiyun  * R24 (0x18) - Left Line Input 1&2 Volume
461*4882a593Smuzhiyun  */
462*4882a593Smuzhiyun #define WM8400_IPVU                             0x0100  /* IPVU */
463*4882a593Smuzhiyun #define WM8400_IPVU_MASK                        0x0100  /* IPVU */
464*4882a593Smuzhiyun #define WM8400_IPVU_SHIFT                            8  /* IPVU */
465*4882a593Smuzhiyun #define WM8400_IPVU_WIDTH                            1  /* IPVU */
466*4882a593Smuzhiyun #define WM8400_LI12MUTE                         0x0080  /* LI12MUTE */
467*4882a593Smuzhiyun #define WM8400_LI12MUTE_MASK                    0x0080  /* LI12MUTE */
468*4882a593Smuzhiyun #define WM8400_LI12MUTE_SHIFT                        7  /* LI12MUTE */
469*4882a593Smuzhiyun #define WM8400_LI12MUTE_WIDTH                        1  /* LI12MUTE */
470*4882a593Smuzhiyun #define WM8400_LI12ZC                           0x0040  /* LI12ZC */
471*4882a593Smuzhiyun #define WM8400_LI12ZC_MASK                      0x0040  /* LI12ZC */
472*4882a593Smuzhiyun #define WM8400_LI12ZC_SHIFT                          6  /* LI12ZC */
473*4882a593Smuzhiyun #define WM8400_LI12ZC_WIDTH                          1  /* LI12ZC */
474*4882a593Smuzhiyun #define WM8400_LIN12VOL_MASK                    0x001F  /* LIN12VOL - [4:0] */
475*4882a593Smuzhiyun #define WM8400_LIN12VOL_SHIFT                        0  /* LIN12VOL - [4:0] */
476*4882a593Smuzhiyun #define WM8400_LIN12VOL_WIDTH                        5  /* LIN12VOL - [4:0] */
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun /*
479*4882a593Smuzhiyun  * R25 (0x19) - Left Line Input 3&4 Volume
480*4882a593Smuzhiyun  */
481*4882a593Smuzhiyun #define WM8400_IPVU                             0x0100  /* IPVU */
482*4882a593Smuzhiyun #define WM8400_IPVU_MASK                        0x0100  /* IPVU */
483*4882a593Smuzhiyun #define WM8400_IPVU_SHIFT                            8  /* IPVU */
484*4882a593Smuzhiyun #define WM8400_IPVU_WIDTH                            1  /* IPVU */
485*4882a593Smuzhiyun #define WM8400_LI34MUTE                         0x0080  /* LI34MUTE */
486*4882a593Smuzhiyun #define WM8400_LI34MUTE_MASK                    0x0080  /* LI34MUTE */
487*4882a593Smuzhiyun #define WM8400_LI34MUTE_SHIFT                        7  /* LI34MUTE */
488*4882a593Smuzhiyun #define WM8400_LI34MUTE_WIDTH                        1  /* LI34MUTE */
489*4882a593Smuzhiyun #define WM8400_LI34ZC                           0x0040  /* LI34ZC */
490*4882a593Smuzhiyun #define WM8400_LI34ZC_MASK                      0x0040  /* LI34ZC */
491*4882a593Smuzhiyun #define WM8400_LI34ZC_SHIFT                          6  /* LI34ZC */
492*4882a593Smuzhiyun #define WM8400_LI34ZC_WIDTH                          1  /* LI34ZC */
493*4882a593Smuzhiyun #define WM8400_LIN34VOL_MASK                    0x001F  /* LIN34VOL - [4:0] */
494*4882a593Smuzhiyun #define WM8400_LIN34VOL_SHIFT                        0  /* LIN34VOL - [4:0] */
495*4882a593Smuzhiyun #define WM8400_LIN34VOL_WIDTH                        5  /* LIN34VOL - [4:0] */
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun /*
498*4882a593Smuzhiyun  * R26 (0x1A) - Right Line Input 1&2 Volume
499*4882a593Smuzhiyun  */
500*4882a593Smuzhiyun #define WM8400_IPVU                             0x0100  /* IPVU */
501*4882a593Smuzhiyun #define WM8400_IPVU_MASK                        0x0100  /* IPVU */
502*4882a593Smuzhiyun #define WM8400_IPVU_SHIFT                            8  /* IPVU */
503*4882a593Smuzhiyun #define WM8400_IPVU_WIDTH                            1  /* IPVU */
504*4882a593Smuzhiyun #define WM8400_RI12MUTE                         0x0080  /* RI12MUTE */
505*4882a593Smuzhiyun #define WM8400_RI12MUTE_MASK                    0x0080  /* RI12MUTE */
506*4882a593Smuzhiyun #define WM8400_RI12MUTE_SHIFT                        7  /* RI12MUTE */
507*4882a593Smuzhiyun #define WM8400_RI12MUTE_WIDTH                        1  /* RI12MUTE */
508*4882a593Smuzhiyun #define WM8400_RI12ZC                           0x0040  /* RI12ZC */
509*4882a593Smuzhiyun #define WM8400_RI12ZC_MASK                      0x0040  /* RI12ZC */
510*4882a593Smuzhiyun #define WM8400_RI12ZC_SHIFT                          6  /* RI12ZC */
511*4882a593Smuzhiyun #define WM8400_RI12ZC_WIDTH                          1  /* RI12ZC */
512*4882a593Smuzhiyun #define WM8400_RIN12VOL_MASK                    0x001F  /* RIN12VOL - [4:0] */
513*4882a593Smuzhiyun #define WM8400_RIN12VOL_SHIFT                        0  /* RIN12VOL - [4:0] */
514*4882a593Smuzhiyun #define WM8400_RIN12VOL_WIDTH                        5  /* RIN12VOL - [4:0] */
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun /*
517*4882a593Smuzhiyun  * R27 (0x1B) - Right Line Input 3&4 Volume
518*4882a593Smuzhiyun  */
519*4882a593Smuzhiyun #define WM8400_IPVU                             0x0100  /* IPVU */
520*4882a593Smuzhiyun #define WM8400_IPVU_MASK                        0x0100  /* IPVU */
521*4882a593Smuzhiyun #define WM8400_IPVU_SHIFT                            8  /* IPVU */
522*4882a593Smuzhiyun #define WM8400_IPVU_WIDTH                            1  /* IPVU */
523*4882a593Smuzhiyun #define WM8400_RI34MUTE                         0x0080  /* RI34MUTE */
524*4882a593Smuzhiyun #define WM8400_RI34MUTE_MASK                    0x0080  /* RI34MUTE */
525*4882a593Smuzhiyun #define WM8400_RI34MUTE_SHIFT                        7  /* RI34MUTE */
526*4882a593Smuzhiyun #define WM8400_RI34MUTE_WIDTH                        1  /* RI34MUTE */
527*4882a593Smuzhiyun #define WM8400_RI34ZC                           0x0040  /* RI34ZC */
528*4882a593Smuzhiyun #define WM8400_RI34ZC_MASK                      0x0040  /* RI34ZC */
529*4882a593Smuzhiyun #define WM8400_RI34ZC_SHIFT                          6  /* RI34ZC */
530*4882a593Smuzhiyun #define WM8400_RI34ZC_WIDTH                          1  /* RI34ZC */
531*4882a593Smuzhiyun #define WM8400_RIN34VOL_MASK                    0x001F  /* RIN34VOL - [4:0] */
532*4882a593Smuzhiyun #define WM8400_RIN34VOL_SHIFT                        0  /* RIN34VOL - [4:0] */
533*4882a593Smuzhiyun #define WM8400_RIN34VOL_WIDTH                        5  /* RIN34VOL - [4:0] */
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun /*
536*4882a593Smuzhiyun  * R28 (0x1C) - Left Output Volume
537*4882a593Smuzhiyun  */
538*4882a593Smuzhiyun #define WM8400_OPVU                             0x0100  /* OPVU */
539*4882a593Smuzhiyun #define WM8400_OPVU_MASK                        0x0100  /* OPVU */
540*4882a593Smuzhiyun #define WM8400_OPVU_SHIFT                            8  /* OPVU */
541*4882a593Smuzhiyun #define WM8400_OPVU_WIDTH                            1  /* OPVU */
542*4882a593Smuzhiyun #define WM8400_LOZC                             0x0080  /* LOZC */
543*4882a593Smuzhiyun #define WM8400_LOZC_MASK                        0x0080  /* LOZC */
544*4882a593Smuzhiyun #define WM8400_LOZC_SHIFT                            7  /* LOZC */
545*4882a593Smuzhiyun #define WM8400_LOZC_WIDTH                            1  /* LOZC */
546*4882a593Smuzhiyun #define WM8400_LOUTVOL_MASK                     0x007F  /* LOUTVOL - [6:0] */
547*4882a593Smuzhiyun #define WM8400_LOUTVOL_SHIFT                         0  /* LOUTVOL - [6:0] */
548*4882a593Smuzhiyun #define WM8400_LOUTVOL_WIDTH                         7  /* LOUTVOL - [6:0] */
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun /*
551*4882a593Smuzhiyun  * R29 (0x1D) - Right Output Volume
552*4882a593Smuzhiyun  */
553*4882a593Smuzhiyun #define WM8400_OPVU                             0x0100  /* OPVU */
554*4882a593Smuzhiyun #define WM8400_OPVU_MASK                        0x0100  /* OPVU */
555*4882a593Smuzhiyun #define WM8400_OPVU_SHIFT                            8  /* OPVU */
556*4882a593Smuzhiyun #define WM8400_OPVU_WIDTH                            1  /* OPVU */
557*4882a593Smuzhiyun #define WM8400_ROZC                             0x0080  /* ROZC */
558*4882a593Smuzhiyun #define WM8400_ROZC_MASK                        0x0080  /* ROZC */
559*4882a593Smuzhiyun #define WM8400_ROZC_SHIFT                            7  /* ROZC */
560*4882a593Smuzhiyun #define WM8400_ROZC_WIDTH                            1  /* ROZC */
561*4882a593Smuzhiyun #define WM8400_ROUTVOL_MASK                     0x007F  /* ROUTVOL - [6:0] */
562*4882a593Smuzhiyun #define WM8400_ROUTVOL_SHIFT                         0  /* ROUTVOL - [6:0] */
563*4882a593Smuzhiyun #define WM8400_ROUTVOL_WIDTH                         7  /* ROUTVOL - [6:0] */
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun /*
566*4882a593Smuzhiyun  * R30 (0x1E) - Line Outputs Volume
567*4882a593Smuzhiyun  */
568*4882a593Smuzhiyun #define WM8400_LONMUTE                          0x0040  /* LONMUTE */
569*4882a593Smuzhiyun #define WM8400_LONMUTE_MASK                     0x0040  /* LONMUTE */
570*4882a593Smuzhiyun #define WM8400_LONMUTE_SHIFT                         6  /* LONMUTE */
571*4882a593Smuzhiyun #define WM8400_LONMUTE_WIDTH                         1  /* LONMUTE */
572*4882a593Smuzhiyun #define WM8400_LOPMUTE                          0x0020  /* LOPMUTE */
573*4882a593Smuzhiyun #define WM8400_LOPMUTE_MASK                     0x0020  /* LOPMUTE */
574*4882a593Smuzhiyun #define WM8400_LOPMUTE_SHIFT                         5  /* LOPMUTE */
575*4882a593Smuzhiyun #define WM8400_LOPMUTE_WIDTH                         1  /* LOPMUTE */
576*4882a593Smuzhiyun #define WM8400_LOATTN                           0x0010  /* LOATTN */
577*4882a593Smuzhiyun #define WM8400_LOATTN_MASK                      0x0010  /* LOATTN */
578*4882a593Smuzhiyun #define WM8400_LOATTN_SHIFT                          4  /* LOATTN */
579*4882a593Smuzhiyun #define WM8400_LOATTN_WIDTH                          1  /* LOATTN */
580*4882a593Smuzhiyun #define WM8400_RONMUTE                          0x0004  /* RONMUTE */
581*4882a593Smuzhiyun #define WM8400_RONMUTE_MASK                     0x0004  /* RONMUTE */
582*4882a593Smuzhiyun #define WM8400_RONMUTE_SHIFT                         2  /* RONMUTE */
583*4882a593Smuzhiyun #define WM8400_RONMUTE_WIDTH                         1  /* RONMUTE */
584*4882a593Smuzhiyun #define WM8400_ROPMUTE                          0x0002  /* ROPMUTE */
585*4882a593Smuzhiyun #define WM8400_ROPMUTE_MASK                     0x0002  /* ROPMUTE */
586*4882a593Smuzhiyun #define WM8400_ROPMUTE_SHIFT                         1  /* ROPMUTE */
587*4882a593Smuzhiyun #define WM8400_ROPMUTE_WIDTH                         1  /* ROPMUTE */
588*4882a593Smuzhiyun #define WM8400_ROATTN                           0x0001  /* ROATTN */
589*4882a593Smuzhiyun #define WM8400_ROATTN_MASK                      0x0001  /* ROATTN */
590*4882a593Smuzhiyun #define WM8400_ROATTN_SHIFT                          0  /* ROATTN */
591*4882a593Smuzhiyun #define WM8400_ROATTN_WIDTH                          1  /* ROATTN */
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun /*
594*4882a593Smuzhiyun  * R31 (0x1F) - Out3/4 Volume
595*4882a593Smuzhiyun  */
596*4882a593Smuzhiyun #define WM8400_OUT3MUTE                         0x0020  /* OUT3MUTE */
597*4882a593Smuzhiyun #define WM8400_OUT3MUTE_MASK                    0x0020  /* OUT3MUTE */
598*4882a593Smuzhiyun #define WM8400_OUT3MUTE_SHIFT                        5  /* OUT3MUTE */
599*4882a593Smuzhiyun #define WM8400_OUT3MUTE_WIDTH                        1  /* OUT3MUTE */
600*4882a593Smuzhiyun #define WM8400_OUT3ATTN                         0x0010  /* OUT3ATTN */
601*4882a593Smuzhiyun #define WM8400_OUT3ATTN_MASK                    0x0010  /* OUT3ATTN */
602*4882a593Smuzhiyun #define WM8400_OUT3ATTN_SHIFT                        4  /* OUT3ATTN */
603*4882a593Smuzhiyun #define WM8400_OUT3ATTN_WIDTH                        1  /* OUT3ATTN */
604*4882a593Smuzhiyun #define WM8400_OUT4MUTE                         0x0002  /* OUT4MUTE */
605*4882a593Smuzhiyun #define WM8400_OUT4MUTE_MASK                    0x0002  /* OUT4MUTE */
606*4882a593Smuzhiyun #define WM8400_OUT4MUTE_SHIFT                        1  /* OUT4MUTE */
607*4882a593Smuzhiyun #define WM8400_OUT4MUTE_WIDTH                        1  /* OUT4MUTE */
608*4882a593Smuzhiyun #define WM8400_OUT4ATTN                         0x0001  /* OUT4ATTN */
609*4882a593Smuzhiyun #define WM8400_OUT4ATTN_MASK                    0x0001  /* OUT4ATTN */
610*4882a593Smuzhiyun #define WM8400_OUT4ATTN_SHIFT                        0  /* OUT4ATTN */
611*4882a593Smuzhiyun #define WM8400_OUT4ATTN_WIDTH                        1  /* OUT4ATTN */
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun /*
614*4882a593Smuzhiyun  * R32 (0x20) - Left OPGA Volume
615*4882a593Smuzhiyun  */
616*4882a593Smuzhiyun #define WM8400_OPVU                             0x0100  /* OPVU */
617*4882a593Smuzhiyun #define WM8400_OPVU_MASK                        0x0100  /* OPVU */
618*4882a593Smuzhiyun #define WM8400_OPVU_SHIFT                            8  /* OPVU */
619*4882a593Smuzhiyun #define WM8400_OPVU_WIDTH                            1  /* OPVU */
620*4882a593Smuzhiyun #define WM8400_LOPGAZC                          0x0080  /* LOPGAZC */
621*4882a593Smuzhiyun #define WM8400_LOPGAZC_MASK                     0x0080  /* LOPGAZC */
622*4882a593Smuzhiyun #define WM8400_LOPGAZC_SHIFT                         7  /* LOPGAZC */
623*4882a593Smuzhiyun #define WM8400_LOPGAZC_WIDTH                         1  /* LOPGAZC */
624*4882a593Smuzhiyun #define WM8400_LOPGAVOL_MASK                    0x007F  /* LOPGAVOL - [6:0] */
625*4882a593Smuzhiyun #define WM8400_LOPGAVOL_SHIFT                        0  /* LOPGAVOL - [6:0] */
626*4882a593Smuzhiyun #define WM8400_LOPGAVOL_WIDTH                        7  /* LOPGAVOL - [6:0] */
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun /*
629*4882a593Smuzhiyun  * R33 (0x21) - Right OPGA Volume
630*4882a593Smuzhiyun  */
631*4882a593Smuzhiyun #define WM8400_OPVU                             0x0100  /* OPVU */
632*4882a593Smuzhiyun #define WM8400_OPVU_MASK                        0x0100  /* OPVU */
633*4882a593Smuzhiyun #define WM8400_OPVU_SHIFT                            8  /* OPVU */
634*4882a593Smuzhiyun #define WM8400_OPVU_WIDTH                            1  /* OPVU */
635*4882a593Smuzhiyun #define WM8400_ROPGAZC                          0x0080  /* ROPGAZC */
636*4882a593Smuzhiyun #define WM8400_ROPGAZC_MASK                     0x0080  /* ROPGAZC */
637*4882a593Smuzhiyun #define WM8400_ROPGAZC_SHIFT                         7  /* ROPGAZC */
638*4882a593Smuzhiyun #define WM8400_ROPGAZC_WIDTH                         1  /* ROPGAZC */
639*4882a593Smuzhiyun #define WM8400_ROPGAVOL_MASK                    0x007F  /* ROPGAVOL - [6:0] */
640*4882a593Smuzhiyun #define WM8400_ROPGAVOL_SHIFT                        0  /* ROPGAVOL - [6:0] */
641*4882a593Smuzhiyun #define WM8400_ROPGAVOL_WIDTH                        7  /* ROPGAVOL - [6:0] */
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun /*
644*4882a593Smuzhiyun  * R34 (0x22) - Speaker Volume
645*4882a593Smuzhiyun  */
646*4882a593Smuzhiyun #define WM8400_SPKATTN_MASK                     0x0003  /* SPKATTN - [1:0] */
647*4882a593Smuzhiyun #define WM8400_SPKATTN_SHIFT                         0  /* SPKATTN - [1:0] */
648*4882a593Smuzhiyun #define WM8400_SPKATTN_WIDTH                         2  /* SPKATTN - [1:0] */
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun /*
651*4882a593Smuzhiyun  * R35 (0x23) - ClassD1
652*4882a593Smuzhiyun  */
653*4882a593Smuzhiyun #define WM8400_CDMODE                           0x0100  /* CDMODE */
654*4882a593Smuzhiyun #define WM8400_CDMODE_MASK                      0x0100  /* CDMODE */
655*4882a593Smuzhiyun #define WM8400_CDMODE_SHIFT                          8  /* CDMODE */
656*4882a593Smuzhiyun #define WM8400_CDMODE_WIDTH                          1  /* CDMODE */
657*4882a593Smuzhiyun #define WM8400_CLASSD_CLK_SEL                   0x0080  /* CLASSD_CLK_SEL */
658*4882a593Smuzhiyun #define WM8400_CLASSD_CLK_SEL_MASK              0x0080  /* CLASSD_CLK_SEL */
659*4882a593Smuzhiyun #define WM8400_CLASSD_CLK_SEL_SHIFT                  7  /* CLASSD_CLK_SEL */
660*4882a593Smuzhiyun #define WM8400_CLASSD_CLK_SEL_WIDTH                  1  /* CLASSD_CLK_SEL */
661*4882a593Smuzhiyun #define WM8400_CD_SRCTRL                        0x0040  /* CD_SRCTRL */
662*4882a593Smuzhiyun #define WM8400_CD_SRCTRL_MASK                   0x0040  /* CD_SRCTRL */
663*4882a593Smuzhiyun #define WM8400_CD_SRCTRL_SHIFT                       6  /* CD_SRCTRL */
664*4882a593Smuzhiyun #define WM8400_CD_SRCTRL_WIDTH                       1  /* CD_SRCTRL */
665*4882a593Smuzhiyun #define WM8400_SPKNOPOP                         0x0020  /* SPKNOPOP */
666*4882a593Smuzhiyun #define WM8400_SPKNOPOP_MASK                    0x0020  /* SPKNOPOP */
667*4882a593Smuzhiyun #define WM8400_SPKNOPOP_SHIFT                        5  /* SPKNOPOP */
668*4882a593Smuzhiyun #define WM8400_SPKNOPOP_WIDTH                        1  /* SPKNOPOP */
669*4882a593Smuzhiyun #define WM8400_DBLERATE                         0x0010  /* DBLERATE */
670*4882a593Smuzhiyun #define WM8400_DBLERATE_MASK                    0x0010  /* DBLERATE */
671*4882a593Smuzhiyun #define WM8400_DBLERATE_SHIFT                        4  /* DBLERATE */
672*4882a593Smuzhiyun #define WM8400_DBLERATE_WIDTH                        1  /* DBLERATE */
673*4882a593Smuzhiyun #define WM8400_LOOPTEST                         0x0008  /* LOOPTEST */
674*4882a593Smuzhiyun #define WM8400_LOOPTEST_MASK                    0x0008  /* LOOPTEST */
675*4882a593Smuzhiyun #define WM8400_LOOPTEST_SHIFT                        3  /* LOOPTEST */
676*4882a593Smuzhiyun #define WM8400_LOOPTEST_WIDTH                        1  /* LOOPTEST */
677*4882a593Smuzhiyun #define WM8400_HALFABBIAS                       0x0004  /* HALFABBIAS */
678*4882a593Smuzhiyun #define WM8400_HALFABBIAS_MASK                  0x0004  /* HALFABBIAS */
679*4882a593Smuzhiyun #define WM8400_HALFABBIAS_SHIFT                      2  /* HALFABBIAS */
680*4882a593Smuzhiyun #define WM8400_HALFABBIAS_WIDTH                      1  /* HALFABBIAS */
681*4882a593Smuzhiyun #define WM8400_TRIDEL_MASK                      0x0003  /* TRIDEL - [1:0] */
682*4882a593Smuzhiyun #define WM8400_TRIDEL_SHIFT                          0  /* TRIDEL - [1:0] */
683*4882a593Smuzhiyun #define WM8400_TRIDEL_WIDTH                          2  /* TRIDEL - [1:0] */
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun /*
686*4882a593Smuzhiyun  * R37 (0x25) - ClassD3
687*4882a593Smuzhiyun  */
688*4882a593Smuzhiyun #define WM8400_DCGAIN_MASK                      0x0038  /* DCGAIN - [5:3] */
689*4882a593Smuzhiyun #define WM8400_DCGAIN_SHIFT                          3  /* DCGAIN - [5:3] */
690*4882a593Smuzhiyun #define WM8400_DCGAIN_WIDTH                          3  /* DCGAIN - [5:3] */
691*4882a593Smuzhiyun #define WM8400_ACGAIN_MASK                      0x0007  /* ACGAIN - [2:0] */
692*4882a593Smuzhiyun #define WM8400_ACGAIN_SHIFT                          0  /* ACGAIN - [2:0] */
693*4882a593Smuzhiyun #define WM8400_ACGAIN_WIDTH                          3  /* ACGAIN - [2:0] */
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun /*
696*4882a593Smuzhiyun  * R39 (0x27) - Input Mixer1
697*4882a593Smuzhiyun  */
698*4882a593Smuzhiyun #define WM8400_AINLMODE_MASK                    0x000C  /* AINLMODE - [3:2] */
699*4882a593Smuzhiyun #define WM8400_AINLMODE_SHIFT                        2  /* AINLMODE - [3:2] */
700*4882a593Smuzhiyun #define WM8400_AINLMODE_WIDTH                        2  /* AINLMODE - [3:2] */
701*4882a593Smuzhiyun #define WM8400_AINRMODE_MASK                    0x0003  /* AINRMODE - [1:0] */
702*4882a593Smuzhiyun #define WM8400_AINRMODE_SHIFT                        0  /* AINRMODE - [1:0] */
703*4882a593Smuzhiyun #define WM8400_AINRMODE_WIDTH                        2  /* AINRMODE - [1:0] */
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun /*
706*4882a593Smuzhiyun  * R40 (0x28) - Input Mixer2
707*4882a593Smuzhiyun  */
708*4882a593Smuzhiyun #define WM8400_LMP4                             0x0080  /* LMP4 */
709*4882a593Smuzhiyun #define WM8400_LMP4_MASK                        0x0080  /* LMP4 */
710*4882a593Smuzhiyun #define WM8400_LMP4_SHIFT                            7  /* LMP4 */
711*4882a593Smuzhiyun #define WM8400_LMP4_WIDTH                            1  /* LMP4 */
712*4882a593Smuzhiyun #define WM8400_LMN3                             0x0040  /* LMN3 */
713*4882a593Smuzhiyun #define WM8400_LMN3_MASK                        0x0040  /* LMN3 */
714*4882a593Smuzhiyun #define WM8400_LMN3_SHIFT                            6  /* LMN3 */
715*4882a593Smuzhiyun #define WM8400_LMN3_WIDTH                            1  /* LMN3 */
716*4882a593Smuzhiyun #define WM8400_LMP2                             0x0020  /* LMP2 */
717*4882a593Smuzhiyun #define WM8400_LMP2_MASK                        0x0020  /* LMP2 */
718*4882a593Smuzhiyun #define WM8400_LMP2_SHIFT                            5  /* LMP2 */
719*4882a593Smuzhiyun #define WM8400_LMP2_WIDTH                            1  /* LMP2 */
720*4882a593Smuzhiyun #define WM8400_LMN1                             0x0010  /* LMN1 */
721*4882a593Smuzhiyun #define WM8400_LMN1_MASK                        0x0010  /* LMN1 */
722*4882a593Smuzhiyun #define WM8400_LMN1_SHIFT                            4  /* LMN1 */
723*4882a593Smuzhiyun #define WM8400_LMN1_WIDTH                            1  /* LMN1 */
724*4882a593Smuzhiyun #define WM8400_RMP4                             0x0008  /* RMP4 */
725*4882a593Smuzhiyun #define WM8400_RMP4_MASK                        0x0008  /* RMP4 */
726*4882a593Smuzhiyun #define WM8400_RMP4_SHIFT                            3  /* RMP4 */
727*4882a593Smuzhiyun #define WM8400_RMP4_WIDTH                            1  /* RMP4 */
728*4882a593Smuzhiyun #define WM8400_RMN3                             0x0004  /* RMN3 */
729*4882a593Smuzhiyun #define WM8400_RMN3_MASK                        0x0004  /* RMN3 */
730*4882a593Smuzhiyun #define WM8400_RMN3_SHIFT                            2  /* RMN3 */
731*4882a593Smuzhiyun #define WM8400_RMN3_WIDTH                            1  /* RMN3 */
732*4882a593Smuzhiyun #define WM8400_RMP2                             0x0002  /* RMP2 */
733*4882a593Smuzhiyun #define WM8400_RMP2_MASK                        0x0002  /* RMP2 */
734*4882a593Smuzhiyun #define WM8400_RMP2_SHIFT                            1  /* RMP2 */
735*4882a593Smuzhiyun #define WM8400_RMP2_WIDTH                            1  /* RMP2 */
736*4882a593Smuzhiyun #define WM8400_RMN1                             0x0001  /* RMN1 */
737*4882a593Smuzhiyun #define WM8400_RMN1_MASK                        0x0001  /* RMN1 */
738*4882a593Smuzhiyun #define WM8400_RMN1_SHIFT                            0  /* RMN1 */
739*4882a593Smuzhiyun #define WM8400_RMN1_WIDTH                            1  /* RMN1 */
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun /*
742*4882a593Smuzhiyun  * R41 (0x29) - Input Mixer3
743*4882a593Smuzhiyun  */
744*4882a593Smuzhiyun #define WM8400_L34MNB                           0x0100  /* L34MNB */
745*4882a593Smuzhiyun #define WM8400_L34MNB_MASK                      0x0100  /* L34MNB */
746*4882a593Smuzhiyun #define WM8400_L34MNB_SHIFT                          8  /* L34MNB */
747*4882a593Smuzhiyun #define WM8400_L34MNB_WIDTH                          1  /* L34MNB */
748*4882a593Smuzhiyun #define WM8400_L34MNBST                         0x0080  /* L34MNBST */
749*4882a593Smuzhiyun #define WM8400_L34MNBST_MASK                    0x0080  /* L34MNBST */
750*4882a593Smuzhiyun #define WM8400_L34MNBST_SHIFT                        7  /* L34MNBST */
751*4882a593Smuzhiyun #define WM8400_L34MNBST_WIDTH                        1  /* L34MNBST */
752*4882a593Smuzhiyun #define WM8400_L12MNB                           0x0020  /* L12MNB */
753*4882a593Smuzhiyun #define WM8400_L12MNB_MASK                      0x0020  /* L12MNB */
754*4882a593Smuzhiyun #define WM8400_L12MNB_SHIFT                          5  /* L12MNB */
755*4882a593Smuzhiyun #define WM8400_L12MNB_WIDTH                          1  /* L12MNB */
756*4882a593Smuzhiyun #define WM8400_L12MNBST                         0x0010  /* L12MNBST */
757*4882a593Smuzhiyun #define WM8400_L12MNBST_MASK                    0x0010  /* L12MNBST */
758*4882a593Smuzhiyun #define WM8400_L12MNBST_SHIFT                        4  /* L12MNBST */
759*4882a593Smuzhiyun #define WM8400_L12MNBST_WIDTH                        1  /* L12MNBST */
760*4882a593Smuzhiyun #define WM8400_LDBVOL_MASK                      0x0007  /* LDBVOL - [2:0] */
761*4882a593Smuzhiyun #define WM8400_LDBVOL_SHIFT                          0  /* LDBVOL - [2:0] */
762*4882a593Smuzhiyun #define WM8400_LDBVOL_WIDTH                          3  /* LDBVOL - [2:0] */
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun /*
765*4882a593Smuzhiyun  * R42 (0x2A) - Input Mixer4
766*4882a593Smuzhiyun  */
767*4882a593Smuzhiyun #define WM8400_R34MNB                           0x0100  /* R34MNB */
768*4882a593Smuzhiyun #define WM8400_R34MNB_MASK                      0x0100  /* R34MNB */
769*4882a593Smuzhiyun #define WM8400_R34MNB_SHIFT                          8  /* R34MNB */
770*4882a593Smuzhiyun #define WM8400_R34MNB_WIDTH                          1  /* R34MNB */
771*4882a593Smuzhiyun #define WM8400_R34MNBST                         0x0080  /* R34MNBST */
772*4882a593Smuzhiyun #define WM8400_R34MNBST_MASK                    0x0080  /* R34MNBST */
773*4882a593Smuzhiyun #define WM8400_R34MNBST_SHIFT                        7  /* R34MNBST */
774*4882a593Smuzhiyun #define WM8400_R34MNBST_WIDTH                        1  /* R34MNBST */
775*4882a593Smuzhiyun #define WM8400_R12MNB                           0x0020  /* R12MNB */
776*4882a593Smuzhiyun #define WM8400_R12MNB_MASK                      0x0020  /* R12MNB */
777*4882a593Smuzhiyun #define WM8400_R12MNB_SHIFT                          5  /* R12MNB */
778*4882a593Smuzhiyun #define WM8400_R12MNB_WIDTH                          1  /* R12MNB */
779*4882a593Smuzhiyun #define WM8400_R12MNBST                         0x0010  /* R12MNBST */
780*4882a593Smuzhiyun #define WM8400_R12MNBST_MASK                    0x0010  /* R12MNBST */
781*4882a593Smuzhiyun #define WM8400_R12MNBST_SHIFT                        4  /* R12MNBST */
782*4882a593Smuzhiyun #define WM8400_R12MNBST_WIDTH                        1  /* R12MNBST */
783*4882a593Smuzhiyun #define WM8400_RDBVOL_MASK                      0x0007  /* RDBVOL - [2:0] */
784*4882a593Smuzhiyun #define WM8400_RDBVOL_SHIFT                          0  /* RDBVOL - [2:0] */
785*4882a593Smuzhiyun #define WM8400_RDBVOL_WIDTH                          3  /* RDBVOL - [2:0] */
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun /*
788*4882a593Smuzhiyun  * R43 (0x2B) - Input Mixer5
789*4882a593Smuzhiyun  */
790*4882a593Smuzhiyun #define WM8400_LI2BVOL_MASK                     0x01C0  /* LI2BVOL - [8:6] */
791*4882a593Smuzhiyun #define WM8400_LI2BVOL_SHIFT                         6  /* LI2BVOL - [8:6] */
792*4882a593Smuzhiyun #define WM8400_LI2BVOL_WIDTH                         3  /* LI2BVOL - [8:6] */
793*4882a593Smuzhiyun #define WM8400_LR4BVOL_MASK                     0x0038  /* LR4BVOL - [5:3] */
794*4882a593Smuzhiyun #define WM8400_LR4BVOL_SHIFT                         3  /* LR4BVOL - [5:3] */
795*4882a593Smuzhiyun #define WM8400_LR4BVOL_WIDTH                         3  /* LR4BVOL - [5:3] */
796*4882a593Smuzhiyun #define WM8400_LL4BVOL_MASK                     0x0007  /* LL4BVOL - [2:0] */
797*4882a593Smuzhiyun #define WM8400_LL4BVOL_SHIFT                         0  /* LL4BVOL - [2:0] */
798*4882a593Smuzhiyun #define WM8400_LL4BVOL_WIDTH                         3  /* LL4BVOL - [2:0] */
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun /*
801*4882a593Smuzhiyun  * R44 (0x2C) - Input Mixer6
802*4882a593Smuzhiyun  */
803*4882a593Smuzhiyun #define WM8400_RI2BVOL_MASK                     0x01C0  /* RI2BVOL - [8:6] */
804*4882a593Smuzhiyun #define WM8400_RI2BVOL_SHIFT                         6  /* RI2BVOL - [8:6] */
805*4882a593Smuzhiyun #define WM8400_RI2BVOL_WIDTH                         3  /* RI2BVOL - [8:6] */
806*4882a593Smuzhiyun #define WM8400_RL4BVOL_MASK                     0x0038  /* RL4BVOL - [5:3] */
807*4882a593Smuzhiyun #define WM8400_RL4BVOL_SHIFT                         3  /* RL4BVOL - [5:3] */
808*4882a593Smuzhiyun #define WM8400_RL4BVOL_WIDTH                         3  /* RL4BVOL - [5:3] */
809*4882a593Smuzhiyun #define WM8400_RR4BVOL_MASK                     0x0007  /* RR4BVOL - [2:0] */
810*4882a593Smuzhiyun #define WM8400_RR4BVOL_SHIFT                         0  /* RR4BVOL - [2:0] */
811*4882a593Smuzhiyun #define WM8400_RR4BVOL_WIDTH                         3  /* RR4BVOL - [2:0] */
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun /*
814*4882a593Smuzhiyun  * R45 (0x2D) - Output Mixer1
815*4882a593Smuzhiyun  */
816*4882a593Smuzhiyun #define WM8400_LRBLO                            0x0080  /* LRBLO */
817*4882a593Smuzhiyun #define WM8400_LRBLO_MASK                       0x0080  /* LRBLO */
818*4882a593Smuzhiyun #define WM8400_LRBLO_SHIFT                           7  /* LRBLO */
819*4882a593Smuzhiyun #define WM8400_LRBLO_WIDTH                           1  /* LRBLO */
820*4882a593Smuzhiyun #define WM8400_LLBLO                            0x0040  /* LLBLO */
821*4882a593Smuzhiyun #define WM8400_LLBLO_MASK                       0x0040  /* LLBLO */
822*4882a593Smuzhiyun #define WM8400_LLBLO_SHIFT                           6  /* LLBLO */
823*4882a593Smuzhiyun #define WM8400_LLBLO_WIDTH                           1  /* LLBLO */
824*4882a593Smuzhiyun #define WM8400_LRI3LO                           0x0020  /* LRI3LO */
825*4882a593Smuzhiyun #define WM8400_LRI3LO_MASK                      0x0020  /* LRI3LO */
826*4882a593Smuzhiyun #define WM8400_LRI3LO_SHIFT                          5  /* LRI3LO */
827*4882a593Smuzhiyun #define WM8400_LRI3LO_WIDTH                          1  /* LRI3LO */
828*4882a593Smuzhiyun #define WM8400_LLI3LO                           0x0010  /* LLI3LO */
829*4882a593Smuzhiyun #define WM8400_LLI3LO_MASK                      0x0010  /* LLI3LO */
830*4882a593Smuzhiyun #define WM8400_LLI3LO_SHIFT                          4  /* LLI3LO */
831*4882a593Smuzhiyun #define WM8400_LLI3LO_WIDTH                          1  /* LLI3LO */
832*4882a593Smuzhiyun #define WM8400_LR12LO                           0x0008  /* LR12LO */
833*4882a593Smuzhiyun #define WM8400_LR12LO_MASK                      0x0008  /* LR12LO */
834*4882a593Smuzhiyun #define WM8400_LR12LO_SHIFT                          3  /* LR12LO */
835*4882a593Smuzhiyun #define WM8400_LR12LO_WIDTH                          1  /* LR12LO */
836*4882a593Smuzhiyun #define WM8400_LL12LO                           0x0004  /* LL12LO */
837*4882a593Smuzhiyun #define WM8400_LL12LO_MASK                      0x0004  /* LL12LO */
838*4882a593Smuzhiyun #define WM8400_LL12LO_SHIFT                          2  /* LL12LO */
839*4882a593Smuzhiyun #define WM8400_LL12LO_WIDTH                          1  /* LL12LO */
840*4882a593Smuzhiyun #define WM8400_LDLO                             0x0001  /* LDLO */
841*4882a593Smuzhiyun #define WM8400_LDLO_MASK                        0x0001  /* LDLO */
842*4882a593Smuzhiyun #define WM8400_LDLO_SHIFT                            0  /* LDLO */
843*4882a593Smuzhiyun #define WM8400_LDLO_WIDTH                            1  /* LDLO */
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun /*
846*4882a593Smuzhiyun  * R46 (0x2E) - Output Mixer2
847*4882a593Smuzhiyun  */
848*4882a593Smuzhiyun #define WM8400_RLBRO                            0x0080  /* RLBRO */
849*4882a593Smuzhiyun #define WM8400_RLBRO_MASK                       0x0080  /* RLBRO */
850*4882a593Smuzhiyun #define WM8400_RLBRO_SHIFT                           7  /* RLBRO */
851*4882a593Smuzhiyun #define WM8400_RLBRO_WIDTH                           1  /* RLBRO */
852*4882a593Smuzhiyun #define WM8400_RRBRO                            0x0040  /* RRBRO */
853*4882a593Smuzhiyun #define WM8400_RRBRO_MASK                       0x0040  /* RRBRO */
854*4882a593Smuzhiyun #define WM8400_RRBRO_SHIFT                           6  /* RRBRO */
855*4882a593Smuzhiyun #define WM8400_RRBRO_WIDTH                           1  /* RRBRO */
856*4882a593Smuzhiyun #define WM8400_RLI3RO                           0x0020  /* RLI3RO */
857*4882a593Smuzhiyun #define WM8400_RLI3RO_MASK                      0x0020  /* RLI3RO */
858*4882a593Smuzhiyun #define WM8400_RLI3RO_SHIFT                          5  /* RLI3RO */
859*4882a593Smuzhiyun #define WM8400_RLI3RO_WIDTH                          1  /* RLI3RO */
860*4882a593Smuzhiyun #define WM8400_RRI3RO                           0x0010  /* RRI3RO */
861*4882a593Smuzhiyun #define WM8400_RRI3RO_MASK                      0x0010  /* RRI3RO */
862*4882a593Smuzhiyun #define WM8400_RRI3RO_SHIFT                          4  /* RRI3RO */
863*4882a593Smuzhiyun #define WM8400_RRI3RO_WIDTH                          1  /* RRI3RO */
864*4882a593Smuzhiyun #define WM8400_RL12RO                           0x0008  /* RL12RO */
865*4882a593Smuzhiyun #define WM8400_RL12RO_MASK                      0x0008  /* RL12RO */
866*4882a593Smuzhiyun #define WM8400_RL12RO_SHIFT                          3  /* RL12RO */
867*4882a593Smuzhiyun #define WM8400_RL12RO_WIDTH                          1  /* RL12RO */
868*4882a593Smuzhiyun #define WM8400_RR12RO                           0x0004  /* RR12RO */
869*4882a593Smuzhiyun #define WM8400_RR12RO_MASK                      0x0004  /* RR12RO */
870*4882a593Smuzhiyun #define WM8400_RR12RO_SHIFT                          2  /* RR12RO */
871*4882a593Smuzhiyun #define WM8400_RR12RO_WIDTH                          1  /* RR12RO */
872*4882a593Smuzhiyun #define WM8400_RDRO                             0x0001  /* RDRO */
873*4882a593Smuzhiyun #define WM8400_RDRO_MASK                        0x0001  /* RDRO */
874*4882a593Smuzhiyun #define WM8400_RDRO_SHIFT                            0  /* RDRO */
875*4882a593Smuzhiyun #define WM8400_RDRO_WIDTH                            1  /* RDRO */
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun /*
878*4882a593Smuzhiyun  * R47 (0x2F) - Output Mixer3
879*4882a593Smuzhiyun  */
880*4882a593Smuzhiyun #define WM8400_LLI3LOVOL_MASK                   0x01C0  /* LLI3LOVOL - [8:6] */
881*4882a593Smuzhiyun #define WM8400_LLI3LOVOL_SHIFT                       6  /* LLI3LOVOL - [8:6] */
882*4882a593Smuzhiyun #define WM8400_LLI3LOVOL_WIDTH                       3  /* LLI3LOVOL - [8:6] */
883*4882a593Smuzhiyun #define WM8400_LR12LOVOL_MASK                   0x0038  /* LR12LOVOL - [5:3] */
884*4882a593Smuzhiyun #define WM8400_LR12LOVOL_SHIFT                       3  /* LR12LOVOL - [5:3] */
885*4882a593Smuzhiyun #define WM8400_LR12LOVOL_WIDTH                       3  /* LR12LOVOL - [5:3] */
886*4882a593Smuzhiyun #define WM8400_LL12LOVOL_MASK                   0x0007  /* LL12LOVOL - [2:0] */
887*4882a593Smuzhiyun #define WM8400_LL12LOVOL_SHIFT                       0  /* LL12LOVOL - [2:0] */
888*4882a593Smuzhiyun #define WM8400_LL12LOVOL_WIDTH                       3  /* LL12LOVOL - [2:0] */
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun /*
891*4882a593Smuzhiyun  * R48 (0x30) - Output Mixer4
892*4882a593Smuzhiyun  */
893*4882a593Smuzhiyun #define WM8400_RRI3ROVOL_MASK                   0x01C0  /* RRI3ROVOL - [8:6] */
894*4882a593Smuzhiyun #define WM8400_RRI3ROVOL_SHIFT                       6  /* RRI3ROVOL - [8:6] */
895*4882a593Smuzhiyun #define WM8400_RRI3ROVOL_WIDTH                       3  /* RRI3ROVOL - [8:6] */
896*4882a593Smuzhiyun #define WM8400_RL12ROVOL_MASK                   0x0038  /* RL12ROVOL - [5:3] */
897*4882a593Smuzhiyun #define WM8400_RL12ROVOL_SHIFT                       3  /* RL12ROVOL - [5:3] */
898*4882a593Smuzhiyun #define WM8400_RL12ROVOL_WIDTH                       3  /* RL12ROVOL - [5:3] */
899*4882a593Smuzhiyun #define WM8400_RR12ROVOL_MASK                   0x0007  /* RR12ROVOL - [2:0] */
900*4882a593Smuzhiyun #define WM8400_RR12ROVOL_SHIFT                       0  /* RR12ROVOL - [2:0] */
901*4882a593Smuzhiyun #define WM8400_RR12ROVOL_WIDTH                       3  /* RR12ROVOL - [2:0] */
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun /*
904*4882a593Smuzhiyun  * R49 (0x31) - Output Mixer5
905*4882a593Smuzhiyun  */
906*4882a593Smuzhiyun #define WM8400_LRI3LOVOL_MASK                   0x01C0  /* LRI3LOVOL - [8:6] */
907*4882a593Smuzhiyun #define WM8400_LRI3LOVOL_SHIFT                       6  /* LRI3LOVOL - [8:6] */
908*4882a593Smuzhiyun #define WM8400_LRI3LOVOL_WIDTH                       3  /* LRI3LOVOL - [8:6] */
909*4882a593Smuzhiyun #define WM8400_LRBLOVOL_MASK                    0x0038  /* LRBLOVOL - [5:3] */
910*4882a593Smuzhiyun #define WM8400_LRBLOVOL_SHIFT                        3  /* LRBLOVOL - [5:3] */
911*4882a593Smuzhiyun #define WM8400_LRBLOVOL_WIDTH                        3  /* LRBLOVOL - [5:3] */
912*4882a593Smuzhiyun #define WM8400_LLBLOVOL_MASK                    0x0007  /* LLBLOVOL - [2:0] */
913*4882a593Smuzhiyun #define WM8400_LLBLOVOL_SHIFT                        0  /* LLBLOVOL - [2:0] */
914*4882a593Smuzhiyun #define WM8400_LLBLOVOL_WIDTH                        3  /* LLBLOVOL - [2:0] */
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun /*
917*4882a593Smuzhiyun  * R50 (0x32) - Output Mixer6
918*4882a593Smuzhiyun  */
919*4882a593Smuzhiyun #define WM8400_RLI3ROVOL_MASK                   0x01C0  /* RLI3ROVOL - [8:6] */
920*4882a593Smuzhiyun #define WM8400_RLI3ROVOL_SHIFT                       6  /* RLI3ROVOL - [8:6] */
921*4882a593Smuzhiyun #define WM8400_RLI3ROVOL_WIDTH                       3  /* RLI3ROVOL - [8:6] */
922*4882a593Smuzhiyun #define WM8400_RLBROVOL_MASK                    0x0038  /* RLBROVOL - [5:3] */
923*4882a593Smuzhiyun #define WM8400_RLBROVOL_SHIFT                        3  /* RLBROVOL - [5:3] */
924*4882a593Smuzhiyun #define WM8400_RLBROVOL_WIDTH                        3  /* RLBROVOL - [5:3] */
925*4882a593Smuzhiyun #define WM8400_RRBROVOL_MASK                    0x0007  /* RRBROVOL - [2:0] */
926*4882a593Smuzhiyun #define WM8400_RRBROVOL_SHIFT                        0  /* RRBROVOL - [2:0] */
927*4882a593Smuzhiyun #define WM8400_RRBROVOL_WIDTH                        3  /* RRBROVOL - [2:0] */
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun /*
930*4882a593Smuzhiyun  * R51 (0x33) - Out3/4 Mixer
931*4882a593Smuzhiyun  */
932*4882a593Smuzhiyun #define WM8400_VSEL_MASK                        0x0180  /* VSEL - [8:7] */
933*4882a593Smuzhiyun #define WM8400_VSEL_SHIFT                            7  /* VSEL - [8:7] */
934*4882a593Smuzhiyun #define WM8400_VSEL_WIDTH                            2  /* VSEL - [8:7] */
935*4882a593Smuzhiyun #define WM8400_LI4O3                            0x0020  /* LI4O3 */
936*4882a593Smuzhiyun #define WM8400_LI4O3_MASK                       0x0020  /* LI4O3 */
937*4882a593Smuzhiyun #define WM8400_LI4O3_SHIFT                           5  /* LI4O3 */
938*4882a593Smuzhiyun #define WM8400_LI4O3_WIDTH                           1  /* LI4O3 */
939*4882a593Smuzhiyun #define WM8400_LPGAO3                           0x0010  /* LPGAO3 */
940*4882a593Smuzhiyun #define WM8400_LPGAO3_MASK                      0x0010  /* LPGAO3 */
941*4882a593Smuzhiyun #define WM8400_LPGAO3_SHIFT                          4  /* LPGAO3 */
942*4882a593Smuzhiyun #define WM8400_LPGAO3_WIDTH                          1  /* LPGAO3 */
943*4882a593Smuzhiyun #define WM8400_RI4O4                            0x0002  /* RI4O4 */
944*4882a593Smuzhiyun #define WM8400_RI4O4_MASK                       0x0002  /* RI4O4 */
945*4882a593Smuzhiyun #define WM8400_RI4O4_SHIFT                           1  /* RI4O4 */
946*4882a593Smuzhiyun #define WM8400_RI4O4_WIDTH                           1  /* RI4O4 */
947*4882a593Smuzhiyun #define WM8400_RPGAO4                           0x0001  /* RPGAO4 */
948*4882a593Smuzhiyun #define WM8400_RPGAO4_MASK                      0x0001  /* RPGAO4 */
949*4882a593Smuzhiyun #define WM8400_RPGAO4_SHIFT                          0  /* RPGAO4 */
950*4882a593Smuzhiyun #define WM8400_RPGAO4_WIDTH                          1  /* RPGAO4 */
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun /*
953*4882a593Smuzhiyun  * R52 (0x34) - Line Mixer1
954*4882a593Smuzhiyun  */
955*4882a593Smuzhiyun #define WM8400_LLOPGALON                        0x0040  /* LLOPGALON */
956*4882a593Smuzhiyun #define WM8400_LLOPGALON_MASK                   0x0040  /* LLOPGALON */
957*4882a593Smuzhiyun #define WM8400_LLOPGALON_SHIFT                       6  /* LLOPGALON */
958*4882a593Smuzhiyun #define WM8400_LLOPGALON_WIDTH                       1  /* LLOPGALON */
959*4882a593Smuzhiyun #define WM8400_LROPGALON                        0x0020  /* LROPGALON */
960*4882a593Smuzhiyun #define WM8400_LROPGALON_MASK                   0x0020  /* LROPGALON */
961*4882a593Smuzhiyun #define WM8400_LROPGALON_SHIFT                       5  /* LROPGALON */
962*4882a593Smuzhiyun #define WM8400_LROPGALON_WIDTH                       1  /* LROPGALON */
963*4882a593Smuzhiyun #define WM8400_LOPLON                           0x0010  /* LOPLON */
964*4882a593Smuzhiyun #define WM8400_LOPLON_MASK                      0x0010  /* LOPLON */
965*4882a593Smuzhiyun #define WM8400_LOPLON_SHIFT                          4  /* LOPLON */
966*4882a593Smuzhiyun #define WM8400_LOPLON_WIDTH                          1  /* LOPLON */
967*4882a593Smuzhiyun #define WM8400_LR12LOP                          0x0004  /* LR12LOP */
968*4882a593Smuzhiyun #define WM8400_LR12LOP_MASK                     0x0004  /* LR12LOP */
969*4882a593Smuzhiyun #define WM8400_LR12LOP_SHIFT                         2  /* LR12LOP */
970*4882a593Smuzhiyun #define WM8400_LR12LOP_WIDTH                         1  /* LR12LOP */
971*4882a593Smuzhiyun #define WM8400_LL12LOP                          0x0002  /* LL12LOP */
972*4882a593Smuzhiyun #define WM8400_LL12LOP_MASK                     0x0002  /* LL12LOP */
973*4882a593Smuzhiyun #define WM8400_LL12LOP_SHIFT                         1  /* LL12LOP */
974*4882a593Smuzhiyun #define WM8400_LL12LOP_WIDTH                         1  /* LL12LOP */
975*4882a593Smuzhiyun #define WM8400_LLOPGALOP                        0x0001  /* LLOPGALOP */
976*4882a593Smuzhiyun #define WM8400_LLOPGALOP_MASK                   0x0001  /* LLOPGALOP */
977*4882a593Smuzhiyun #define WM8400_LLOPGALOP_SHIFT                       0  /* LLOPGALOP */
978*4882a593Smuzhiyun #define WM8400_LLOPGALOP_WIDTH                       1  /* LLOPGALOP */
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun /*
981*4882a593Smuzhiyun  * R53 (0x35) - Line Mixer2
982*4882a593Smuzhiyun  */
983*4882a593Smuzhiyun #define WM8400_RROPGARON                        0x0040  /* RROPGARON */
984*4882a593Smuzhiyun #define WM8400_RROPGARON_MASK                   0x0040  /* RROPGARON */
985*4882a593Smuzhiyun #define WM8400_RROPGARON_SHIFT                       6  /* RROPGARON */
986*4882a593Smuzhiyun #define WM8400_RROPGARON_WIDTH                       1  /* RROPGARON */
987*4882a593Smuzhiyun #define WM8400_RLOPGARON                        0x0020  /* RLOPGARON */
988*4882a593Smuzhiyun #define WM8400_RLOPGARON_MASK                   0x0020  /* RLOPGARON */
989*4882a593Smuzhiyun #define WM8400_RLOPGARON_SHIFT                       5  /* RLOPGARON */
990*4882a593Smuzhiyun #define WM8400_RLOPGARON_WIDTH                       1  /* RLOPGARON */
991*4882a593Smuzhiyun #define WM8400_ROPRON                           0x0010  /* ROPRON */
992*4882a593Smuzhiyun #define WM8400_ROPRON_MASK                      0x0010  /* ROPRON */
993*4882a593Smuzhiyun #define WM8400_ROPRON_SHIFT                          4  /* ROPRON */
994*4882a593Smuzhiyun #define WM8400_ROPRON_WIDTH                          1  /* ROPRON */
995*4882a593Smuzhiyun #define WM8400_RL12ROP                          0x0004  /* RL12ROP */
996*4882a593Smuzhiyun #define WM8400_RL12ROP_MASK                     0x0004  /* RL12ROP */
997*4882a593Smuzhiyun #define WM8400_RL12ROP_SHIFT                         2  /* RL12ROP */
998*4882a593Smuzhiyun #define WM8400_RL12ROP_WIDTH                         1  /* RL12ROP */
999*4882a593Smuzhiyun #define WM8400_RR12ROP                          0x0002  /* RR12ROP */
1000*4882a593Smuzhiyun #define WM8400_RR12ROP_MASK                     0x0002  /* RR12ROP */
1001*4882a593Smuzhiyun #define WM8400_RR12ROP_SHIFT                         1  /* RR12ROP */
1002*4882a593Smuzhiyun #define WM8400_RR12ROP_WIDTH                         1  /* RR12ROP */
1003*4882a593Smuzhiyun #define WM8400_RROPGAROP                        0x0001  /* RROPGAROP */
1004*4882a593Smuzhiyun #define WM8400_RROPGAROP_MASK                   0x0001  /* RROPGAROP */
1005*4882a593Smuzhiyun #define WM8400_RROPGAROP_SHIFT                       0  /* RROPGAROP */
1006*4882a593Smuzhiyun #define WM8400_RROPGAROP_WIDTH                       1  /* RROPGAROP */
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun /*
1009*4882a593Smuzhiyun  * R54 (0x36) - Speaker Mixer
1010*4882a593Smuzhiyun  */
1011*4882a593Smuzhiyun #define WM8400_LB2SPK                           0x0080  /* LB2SPK */
1012*4882a593Smuzhiyun #define WM8400_LB2SPK_MASK                      0x0080  /* LB2SPK */
1013*4882a593Smuzhiyun #define WM8400_LB2SPK_SHIFT                          7  /* LB2SPK */
1014*4882a593Smuzhiyun #define WM8400_LB2SPK_WIDTH                          1  /* LB2SPK */
1015*4882a593Smuzhiyun #define WM8400_RB2SPK                           0x0040  /* RB2SPK */
1016*4882a593Smuzhiyun #define WM8400_RB2SPK_MASK                      0x0040  /* RB2SPK */
1017*4882a593Smuzhiyun #define WM8400_RB2SPK_SHIFT                          6  /* RB2SPK */
1018*4882a593Smuzhiyun #define WM8400_RB2SPK_WIDTH                          1  /* RB2SPK */
1019*4882a593Smuzhiyun #define WM8400_LI2SPK                           0x0020  /* LI2SPK */
1020*4882a593Smuzhiyun #define WM8400_LI2SPK_MASK                      0x0020  /* LI2SPK */
1021*4882a593Smuzhiyun #define WM8400_LI2SPK_SHIFT                          5  /* LI2SPK */
1022*4882a593Smuzhiyun #define WM8400_LI2SPK_WIDTH                          1  /* LI2SPK */
1023*4882a593Smuzhiyun #define WM8400_RI2SPK                           0x0010  /* RI2SPK */
1024*4882a593Smuzhiyun #define WM8400_RI2SPK_MASK                      0x0010  /* RI2SPK */
1025*4882a593Smuzhiyun #define WM8400_RI2SPK_SHIFT                          4  /* RI2SPK */
1026*4882a593Smuzhiyun #define WM8400_RI2SPK_WIDTH                          1  /* RI2SPK */
1027*4882a593Smuzhiyun #define WM8400_LOPGASPK                         0x0008  /* LOPGASPK */
1028*4882a593Smuzhiyun #define WM8400_LOPGASPK_MASK                    0x0008  /* LOPGASPK */
1029*4882a593Smuzhiyun #define WM8400_LOPGASPK_SHIFT                        3  /* LOPGASPK */
1030*4882a593Smuzhiyun #define WM8400_LOPGASPK_WIDTH                        1  /* LOPGASPK */
1031*4882a593Smuzhiyun #define WM8400_ROPGASPK                         0x0004  /* ROPGASPK */
1032*4882a593Smuzhiyun #define WM8400_ROPGASPK_MASK                    0x0004  /* ROPGASPK */
1033*4882a593Smuzhiyun #define WM8400_ROPGASPK_SHIFT                        2  /* ROPGASPK */
1034*4882a593Smuzhiyun #define WM8400_ROPGASPK_WIDTH                        1  /* ROPGASPK */
1035*4882a593Smuzhiyun #define WM8400_LDSPK                            0x0002  /* LDSPK */
1036*4882a593Smuzhiyun #define WM8400_LDSPK_MASK                       0x0002  /* LDSPK */
1037*4882a593Smuzhiyun #define WM8400_LDSPK_SHIFT                           1  /* LDSPK */
1038*4882a593Smuzhiyun #define WM8400_LDSPK_WIDTH                           1  /* LDSPK */
1039*4882a593Smuzhiyun #define WM8400_RDSPK                            0x0001  /* RDSPK */
1040*4882a593Smuzhiyun #define WM8400_RDSPK_MASK                       0x0001  /* RDSPK */
1041*4882a593Smuzhiyun #define WM8400_RDSPK_SHIFT                           0  /* RDSPK */
1042*4882a593Smuzhiyun #define WM8400_RDSPK_WIDTH                           1  /* RDSPK */
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun /*
1045*4882a593Smuzhiyun  * R55 (0x37) - Additional Control
1046*4882a593Smuzhiyun  */
1047*4882a593Smuzhiyun #define WM8400_VROI                             0x0001  /* VROI */
1048*4882a593Smuzhiyun #define WM8400_VROI_MASK                        0x0001  /* VROI */
1049*4882a593Smuzhiyun #define WM8400_VROI_SHIFT                            0  /* VROI */
1050*4882a593Smuzhiyun #define WM8400_VROI_WIDTH                            1  /* VROI */
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun /*
1053*4882a593Smuzhiyun  * R56 (0x38) - AntiPOP1
1054*4882a593Smuzhiyun  */
1055*4882a593Smuzhiyun #define WM8400_DIS_LLINE                        0x0020  /* DIS_LLINE */
1056*4882a593Smuzhiyun #define WM8400_DIS_LLINE_MASK                   0x0020  /* DIS_LLINE */
1057*4882a593Smuzhiyun #define WM8400_DIS_LLINE_SHIFT                       5  /* DIS_LLINE */
1058*4882a593Smuzhiyun #define WM8400_DIS_LLINE_WIDTH                       1  /* DIS_LLINE */
1059*4882a593Smuzhiyun #define WM8400_DIS_RLINE                        0x0010  /* DIS_RLINE */
1060*4882a593Smuzhiyun #define WM8400_DIS_RLINE_MASK                   0x0010  /* DIS_RLINE */
1061*4882a593Smuzhiyun #define WM8400_DIS_RLINE_SHIFT                       4  /* DIS_RLINE */
1062*4882a593Smuzhiyun #define WM8400_DIS_RLINE_WIDTH                       1  /* DIS_RLINE */
1063*4882a593Smuzhiyun #define WM8400_DIS_OUT3                         0x0008  /* DIS_OUT3 */
1064*4882a593Smuzhiyun #define WM8400_DIS_OUT3_MASK                    0x0008  /* DIS_OUT3 */
1065*4882a593Smuzhiyun #define WM8400_DIS_OUT3_SHIFT                        3  /* DIS_OUT3 */
1066*4882a593Smuzhiyun #define WM8400_DIS_OUT3_WIDTH                        1  /* DIS_OUT3 */
1067*4882a593Smuzhiyun #define WM8400_DIS_OUT4                         0x0004  /* DIS_OUT4 */
1068*4882a593Smuzhiyun #define WM8400_DIS_OUT4_MASK                    0x0004  /* DIS_OUT4 */
1069*4882a593Smuzhiyun #define WM8400_DIS_OUT4_SHIFT                        2  /* DIS_OUT4 */
1070*4882a593Smuzhiyun #define WM8400_DIS_OUT4_WIDTH                        1  /* DIS_OUT4 */
1071*4882a593Smuzhiyun #define WM8400_DIS_LOUT                         0x0002  /* DIS_LOUT */
1072*4882a593Smuzhiyun #define WM8400_DIS_LOUT_MASK                    0x0002  /* DIS_LOUT */
1073*4882a593Smuzhiyun #define WM8400_DIS_LOUT_SHIFT                        1  /* DIS_LOUT */
1074*4882a593Smuzhiyun #define WM8400_DIS_LOUT_WIDTH                        1  /* DIS_LOUT */
1075*4882a593Smuzhiyun #define WM8400_DIS_ROUT                         0x0001  /* DIS_ROUT */
1076*4882a593Smuzhiyun #define WM8400_DIS_ROUT_MASK                    0x0001  /* DIS_ROUT */
1077*4882a593Smuzhiyun #define WM8400_DIS_ROUT_SHIFT                        0  /* DIS_ROUT */
1078*4882a593Smuzhiyun #define WM8400_DIS_ROUT_WIDTH                        1  /* DIS_ROUT */
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun /*
1081*4882a593Smuzhiyun  * R57 (0x39) - AntiPOP2
1082*4882a593Smuzhiyun  */
1083*4882a593Smuzhiyun #define WM8400_SOFTST                           0x0040  /* SOFTST */
1084*4882a593Smuzhiyun #define WM8400_SOFTST_MASK                      0x0040  /* SOFTST */
1085*4882a593Smuzhiyun #define WM8400_SOFTST_SHIFT                          6  /* SOFTST */
1086*4882a593Smuzhiyun #define WM8400_SOFTST_WIDTH                          1  /* SOFTST */
1087*4882a593Smuzhiyun #define WM8400_BUFIOEN                          0x0008  /* BUFIOEN */
1088*4882a593Smuzhiyun #define WM8400_BUFIOEN_MASK                     0x0008  /* BUFIOEN */
1089*4882a593Smuzhiyun #define WM8400_BUFIOEN_SHIFT                         3  /* BUFIOEN */
1090*4882a593Smuzhiyun #define WM8400_BUFIOEN_WIDTH                         1  /* BUFIOEN */
1091*4882a593Smuzhiyun #define WM8400_BUFDCOPEN                        0x0004  /* BUFDCOPEN */
1092*4882a593Smuzhiyun #define WM8400_BUFDCOPEN_MASK                   0x0004  /* BUFDCOPEN */
1093*4882a593Smuzhiyun #define WM8400_BUFDCOPEN_SHIFT                       2  /* BUFDCOPEN */
1094*4882a593Smuzhiyun #define WM8400_BUFDCOPEN_WIDTH                       1  /* BUFDCOPEN */
1095*4882a593Smuzhiyun #define WM8400_POBCTRL                          0x0002  /* POBCTRL */
1096*4882a593Smuzhiyun #define WM8400_POBCTRL_MASK                     0x0002  /* POBCTRL */
1097*4882a593Smuzhiyun #define WM8400_POBCTRL_SHIFT                         1  /* POBCTRL */
1098*4882a593Smuzhiyun #define WM8400_POBCTRL_WIDTH                         1  /* POBCTRL */
1099*4882a593Smuzhiyun #define WM8400_VMIDTOG                          0x0001  /* VMIDTOG */
1100*4882a593Smuzhiyun #define WM8400_VMIDTOG_MASK                     0x0001  /* VMIDTOG */
1101*4882a593Smuzhiyun #define WM8400_VMIDTOG_SHIFT                         0  /* VMIDTOG */
1102*4882a593Smuzhiyun #define WM8400_VMIDTOG_WIDTH                         1  /* VMIDTOG */
1103*4882a593Smuzhiyun 
1104*4882a593Smuzhiyun /*
1105*4882a593Smuzhiyun  * R58 (0x3A) - MICBIAS
1106*4882a593Smuzhiyun  */
1107*4882a593Smuzhiyun #define WM8400_MCDSCTH_MASK                     0x00C0  /* MCDSCTH - [7:6] */
1108*4882a593Smuzhiyun #define WM8400_MCDSCTH_SHIFT                         6  /* MCDSCTH - [7:6] */
1109*4882a593Smuzhiyun #define WM8400_MCDSCTH_WIDTH                         2  /* MCDSCTH - [7:6] */
1110*4882a593Smuzhiyun #define WM8400_MCDTHR_MASK                      0x0038  /* MCDTHR - [5:3] */
1111*4882a593Smuzhiyun #define WM8400_MCDTHR_SHIFT                          3  /* MCDTHR - [5:3] */
1112*4882a593Smuzhiyun #define WM8400_MCDTHR_WIDTH                          3  /* MCDTHR - [5:3] */
1113*4882a593Smuzhiyun #define WM8400_MCD                              0x0004  /* MCD */
1114*4882a593Smuzhiyun #define WM8400_MCD_MASK                         0x0004  /* MCD */
1115*4882a593Smuzhiyun #define WM8400_MCD_SHIFT                             2  /* MCD */
1116*4882a593Smuzhiyun #define WM8400_MCD_WIDTH                             1  /* MCD */
1117*4882a593Smuzhiyun #define WM8400_MBSEL                            0x0001  /* MBSEL */
1118*4882a593Smuzhiyun #define WM8400_MBSEL_MASK                       0x0001  /* MBSEL */
1119*4882a593Smuzhiyun #define WM8400_MBSEL_SHIFT                           0  /* MBSEL */
1120*4882a593Smuzhiyun #define WM8400_MBSEL_WIDTH                           1  /* MBSEL */
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun /*
1123*4882a593Smuzhiyun  * R60 (0x3C) - FLL Control 1
1124*4882a593Smuzhiyun  */
1125*4882a593Smuzhiyun #define WM8400_FLL_REF_FREQ                     0x1000  /* FLL_REF_FREQ */
1126*4882a593Smuzhiyun #define WM8400_FLL_REF_FREQ_MASK                0x1000  /* FLL_REF_FREQ */
1127*4882a593Smuzhiyun #define WM8400_FLL_REF_FREQ_SHIFT                   12  /* FLL_REF_FREQ */
1128*4882a593Smuzhiyun #define WM8400_FLL_REF_FREQ_WIDTH                    1  /* FLL_REF_FREQ */
1129*4882a593Smuzhiyun #define WM8400_FLL_CLK_SRC_MASK                 0x0C00  /* FLL_CLK_SRC - [11:10] */
1130*4882a593Smuzhiyun #define WM8400_FLL_CLK_SRC_SHIFT                    10  /* FLL_CLK_SRC - [11:10] */
1131*4882a593Smuzhiyun #define WM8400_FLL_CLK_SRC_WIDTH                     2  /* FLL_CLK_SRC - [11:10] */
1132*4882a593Smuzhiyun #define WM8400_FLL_FRAC                         0x0200  /* FLL_FRAC */
1133*4882a593Smuzhiyun #define WM8400_FLL_FRAC_MASK                    0x0200  /* FLL_FRAC */
1134*4882a593Smuzhiyun #define WM8400_FLL_FRAC_SHIFT                        9  /* FLL_FRAC */
1135*4882a593Smuzhiyun #define WM8400_FLL_FRAC_WIDTH                        1  /* FLL_FRAC */
1136*4882a593Smuzhiyun #define WM8400_FLL_OSC_ENA                      0x0100  /* FLL_OSC_ENA */
1137*4882a593Smuzhiyun #define WM8400_FLL_OSC_ENA_MASK                 0x0100  /* FLL_OSC_ENA */
1138*4882a593Smuzhiyun #define WM8400_FLL_OSC_ENA_SHIFT                     8  /* FLL_OSC_ENA */
1139*4882a593Smuzhiyun #define WM8400_FLL_OSC_ENA_WIDTH                     1  /* FLL_OSC_ENA */
1140*4882a593Smuzhiyun #define WM8400_FLL_CTRL_RATE_MASK               0x00E0  /* FLL_CTRL_RATE - [7:5] */
1141*4882a593Smuzhiyun #define WM8400_FLL_CTRL_RATE_SHIFT                   5  /* FLL_CTRL_RATE - [7:5] */
1142*4882a593Smuzhiyun #define WM8400_FLL_CTRL_RATE_WIDTH                   3  /* FLL_CTRL_RATE - [7:5] */
1143*4882a593Smuzhiyun #define WM8400_FLL_FRATIO_MASK                  0x001F  /* FLL_FRATIO - [4:0] */
1144*4882a593Smuzhiyun #define WM8400_FLL_FRATIO_SHIFT                      0  /* FLL_FRATIO - [4:0] */
1145*4882a593Smuzhiyun #define WM8400_FLL_FRATIO_WIDTH                      5  /* FLL_FRATIO - [4:0] */
1146*4882a593Smuzhiyun 
1147*4882a593Smuzhiyun /*
1148*4882a593Smuzhiyun  * R61 (0x3D) - FLL Control 2
1149*4882a593Smuzhiyun  */
1150*4882a593Smuzhiyun #define WM8400_FLL_K_MASK                       0xFFFF  /* FLL_K - [15:0] */
1151*4882a593Smuzhiyun #define WM8400_FLL_K_SHIFT                           0  /* FLL_K - [15:0] */
1152*4882a593Smuzhiyun #define WM8400_FLL_K_WIDTH                          16  /* FLL_K - [15:0] */
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun /*
1155*4882a593Smuzhiyun  * R62 (0x3E) - FLL Control 3
1156*4882a593Smuzhiyun  */
1157*4882a593Smuzhiyun #define WM8400_FLL_N_MASK                       0x03FF  /* FLL_N - [9:0] */
1158*4882a593Smuzhiyun #define WM8400_FLL_N_SHIFT                           0  /* FLL_N - [9:0] */
1159*4882a593Smuzhiyun #define WM8400_FLL_N_WIDTH                          10  /* FLL_N - [9:0] */
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun /*
1162*4882a593Smuzhiyun  * R63 (0x3F) - FLL Control 4
1163*4882a593Smuzhiyun  */
1164*4882a593Smuzhiyun #define WM8400_FLL_TRK_GAIN_MASK                0x0078  /* FLL_TRK_GAIN - [6:3] */
1165*4882a593Smuzhiyun #define WM8400_FLL_TRK_GAIN_SHIFT                    3  /* FLL_TRK_GAIN - [6:3] */
1166*4882a593Smuzhiyun #define WM8400_FLL_TRK_GAIN_WIDTH                    4  /* FLL_TRK_GAIN - [6:3] */
1167*4882a593Smuzhiyun #define WM8400_FLL_OUTDIV_MASK                  0x0007  /* FLL_OUTDIV - [2:0] */
1168*4882a593Smuzhiyun #define WM8400_FLL_OUTDIV_SHIFT                      0  /* FLL_OUTDIV - [2:0] */
1169*4882a593Smuzhiyun #define WM8400_FLL_OUTDIV_WIDTH                      3  /* FLL_OUTDIV - [2:0] */
1170*4882a593Smuzhiyun 
1171*4882a593Smuzhiyun struct wm8400;
1172*4882a593Smuzhiyun void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400);
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun #endif
1175