1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * rtc.h -- RTC driver for Wolfson WM8350 PMIC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2007 Wolfson Microelectronics PLC 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __LINUX_MFD_WM8350_RTC_H 9*4882a593Smuzhiyun #define __LINUX_MFD_WM8350_RTC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/platform_device.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Register values. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define WM8350_RTC_SECONDS_MINUTES 0x10 17*4882a593Smuzhiyun #define WM8350_RTC_HOURS_DAY 0x11 18*4882a593Smuzhiyun #define WM8350_RTC_DATE_MONTH 0x12 19*4882a593Smuzhiyun #define WM8350_RTC_YEAR 0x13 20*4882a593Smuzhiyun #define WM8350_ALARM_SECONDS_MINUTES 0x14 21*4882a593Smuzhiyun #define WM8350_ALARM_HOURS_DAY 0x15 22*4882a593Smuzhiyun #define WM8350_ALARM_DATE_MONTH 0x16 23*4882a593Smuzhiyun #define WM8350_RTC_TIME_CONTROL 0x17 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * R16 (0x10) - RTC Seconds/Minutes 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define WM8350_RTC_MINS_MASK 0x7F00 29*4882a593Smuzhiyun #define WM8350_RTC_MINS_SHIFT 8 30*4882a593Smuzhiyun #define WM8350_RTC_SECS_MASK 0x007F 31*4882a593Smuzhiyun #define WM8350_RTC_SECS_SHIFT 0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * R17 (0x11) - RTC Hours/Day 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define WM8350_RTC_DAY_MASK 0x0700 37*4882a593Smuzhiyun #define WM8350_RTC_DAY_SHIFT 8 38*4882a593Smuzhiyun #define WM8350_RTC_HPM_MASK 0x0020 39*4882a593Smuzhiyun #define WM8350_RTC_HPM_SHIFT 5 40*4882a593Smuzhiyun #define WM8350_RTC_HRS_MASK 0x001F 41*4882a593Smuzhiyun #define WM8350_RTC_HRS_SHIFT 0 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Bit values for R21 (0x15) */ 44*4882a593Smuzhiyun #define WM8350_RTC_DAY_SUN 1 45*4882a593Smuzhiyun #define WM8350_RTC_DAY_MON 2 46*4882a593Smuzhiyun #define WM8350_RTC_DAY_TUE 3 47*4882a593Smuzhiyun #define WM8350_RTC_DAY_WED 4 48*4882a593Smuzhiyun #define WM8350_RTC_DAY_THU 5 49*4882a593Smuzhiyun #define WM8350_RTC_DAY_FRI 6 50*4882a593Smuzhiyun #define WM8350_RTC_DAY_SAT 7 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define WM8350_RTC_HPM_AM 0 53*4882a593Smuzhiyun #define WM8350_RTC_HPM_PM 1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * R18 (0x12) - RTC Date/Month 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define WM8350_RTC_MTH_MASK 0x1F00 59*4882a593Smuzhiyun #define WM8350_RTC_MTH_SHIFT 8 60*4882a593Smuzhiyun #define WM8350_RTC_DATE_MASK 0x003F 61*4882a593Smuzhiyun #define WM8350_RTC_DATE_SHIFT 0 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Bit values for R22 (0x16) */ 64*4882a593Smuzhiyun #define WM8350_RTC_MTH_JAN 1 65*4882a593Smuzhiyun #define WM8350_RTC_MTH_FEB 2 66*4882a593Smuzhiyun #define WM8350_RTC_MTH_MAR 3 67*4882a593Smuzhiyun #define WM8350_RTC_MTH_APR 4 68*4882a593Smuzhiyun #define WM8350_RTC_MTH_MAY 5 69*4882a593Smuzhiyun #define WM8350_RTC_MTH_JUN 6 70*4882a593Smuzhiyun #define WM8350_RTC_MTH_JUL 7 71*4882a593Smuzhiyun #define WM8350_RTC_MTH_AUG 8 72*4882a593Smuzhiyun #define WM8350_RTC_MTH_SEP 9 73*4882a593Smuzhiyun #define WM8350_RTC_MTH_OCT 10 74*4882a593Smuzhiyun #define WM8350_RTC_MTH_NOV 11 75*4882a593Smuzhiyun #define WM8350_RTC_MTH_DEC 12 76*4882a593Smuzhiyun #define WM8350_RTC_MTH_JAN_BCD 0x01 77*4882a593Smuzhiyun #define WM8350_RTC_MTH_FEB_BCD 0x02 78*4882a593Smuzhiyun #define WM8350_RTC_MTH_MAR_BCD 0x03 79*4882a593Smuzhiyun #define WM8350_RTC_MTH_APR_BCD 0x04 80*4882a593Smuzhiyun #define WM8350_RTC_MTH_MAY_BCD 0x05 81*4882a593Smuzhiyun #define WM8350_RTC_MTH_JUN_BCD 0x06 82*4882a593Smuzhiyun #define WM8350_RTC_MTH_JUL_BCD 0x07 83*4882a593Smuzhiyun #define WM8350_RTC_MTH_AUG_BCD 0x08 84*4882a593Smuzhiyun #define WM8350_RTC_MTH_SEP_BCD 0x09 85*4882a593Smuzhiyun #define WM8350_RTC_MTH_OCT_BCD 0x10 86*4882a593Smuzhiyun #define WM8350_RTC_MTH_NOV_BCD 0x11 87*4882a593Smuzhiyun #define WM8350_RTC_MTH_DEC_BCD 0x12 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * R19 (0x13) - RTC Year 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define WM8350_RTC_YHUNDREDS_MASK 0x3F00 93*4882a593Smuzhiyun #define WM8350_RTC_YHUNDREDS_SHIFT 8 94*4882a593Smuzhiyun #define WM8350_RTC_YUNITS_MASK 0x00FF 95*4882a593Smuzhiyun #define WM8350_RTC_YUNITS_SHIFT 0 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * R20 (0x14) - Alarm Seconds/Minutes 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun #define WM8350_RTC_ALMMINS_MASK 0x7F00 101*4882a593Smuzhiyun #define WM8350_RTC_ALMMINS_SHIFT 8 102*4882a593Smuzhiyun #define WM8350_RTC_ALMSECS_MASK 0x007F 103*4882a593Smuzhiyun #define WM8350_RTC_ALMSECS_SHIFT 0 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Bit values for R20 (0x14) */ 106*4882a593Smuzhiyun #define WM8350_RTC_ALMMINS_DONT_CARE -1 107*4882a593Smuzhiyun #define WM8350_RTC_ALMSECS_DONT_CARE -1 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * R21 (0x15) - Alarm Hours/Day 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_MASK 0x0F00 113*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_SHIFT 8 114*4882a593Smuzhiyun #define WM8350_RTC_ALMHPM_MASK 0x0020 115*4882a593Smuzhiyun #define WM8350_RTC_ALMHPM_SHIFT 5 116*4882a593Smuzhiyun #define WM8350_RTC_ALMHRS_MASK 0x001F 117*4882a593Smuzhiyun #define WM8350_RTC_ALMHRS_SHIFT 0 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* Bit values for R21 (0x15) */ 120*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_DONT_CARE -1 121*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_SUN 1 122*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_MON 2 123*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_TUE 3 124*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_WED 4 125*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_THU 5 126*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_FRI 6 127*4882a593Smuzhiyun #define WM8350_RTC_ALMDAY_SAT 7 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define WM8350_RTC_ALMHPM_AM 0 130*4882a593Smuzhiyun #define WM8350_RTC_ALMHPM_PM 1 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define WM8350_RTC_ALMHRS_DONT_CARE -1 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* 135*4882a593Smuzhiyun * R22 (0x16) - Alarm Date/Month 136*4882a593Smuzhiyun */ 137*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_MASK 0x1F00 138*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_SHIFT 8 139*4882a593Smuzhiyun #define WM8350_RTC_ALMDATE_MASK 0x003F 140*4882a593Smuzhiyun #define WM8350_RTC_ALMDATE_SHIFT 0 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Bit values for R22 (0x16) */ 143*4882a593Smuzhiyun #define WM8350_RTC_ALMDATE_DONT_CARE -1 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_DONT_CARE -1 146*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_JAN 1 147*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_FEB 2 148*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_MAR 3 149*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_APR 4 150*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_MAY 5 151*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_JUN 6 152*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_JUL 7 153*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_AUG 8 154*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_SEP 9 155*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_OCT 10 156*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_NOV 11 157*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_DEC 12 158*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_JAN_BCD 0x01 159*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_FEB_BCD 0x02 160*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_MAR_BCD 0x03 161*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_APR_BCD 0x04 162*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_MAY_BCD 0x05 163*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_JUN_BCD 0x06 164*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_JUL_BCD 0x07 165*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_AUG_BCD 0x08 166*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_SEP_BCD 0x09 167*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_OCT_BCD 0x10 168*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_NOV_BCD 0x11 169*4882a593Smuzhiyun #define WM8350_RTC_ALMMTH_DEC_BCD 0x12 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * R23 (0x17) - RTC Time Control 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun #define WM8350_RTC_BCD 0x8000 175*4882a593Smuzhiyun #define WM8350_RTC_BCD_MASK 0x8000 176*4882a593Smuzhiyun #define WM8350_RTC_BCD_SHIFT 15 177*4882a593Smuzhiyun #define WM8350_RTC_12HR 0x4000 178*4882a593Smuzhiyun #define WM8350_RTC_12HR_MASK 0x4000 179*4882a593Smuzhiyun #define WM8350_RTC_12HR_SHIFT 14 180*4882a593Smuzhiyun #define WM8350_RTC_DST 0x2000 181*4882a593Smuzhiyun #define WM8350_RTC_DST_MASK 0x2000 182*4882a593Smuzhiyun #define WM8350_RTC_DST_SHIFT 13 183*4882a593Smuzhiyun #define WM8350_RTC_SET 0x0800 184*4882a593Smuzhiyun #define WM8350_RTC_SET_MASK 0x0800 185*4882a593Smuzhiyun #define WM8350_RTC_SET_SHIFT 11 186*4882a593Smuzhiyun #define WM8350_RTC_STS 0x0400 187*4882a593Smuzhiyun #define WM8350_RTC_STS_MASK 0x0400 188*4882a593Smuzhiyun #define WM8350_RTC_STS_SHIFT 10 189*4882a593Smuzhiyun #define WM8350_RTC_ALMSET 0x0200 190*4882a593Smuzhiyun #define WM8350_RTC_ALMSET_MASK 0x0200 191*4882a593Smuzhiyun #define WM8350_RTC_ALMSET_SHIFT 9 192*4882a593Smuzhiyun #define WM8350_RTC_ALMSTS 0x0100 193*4882a593Smuzhiyun #define WM8350_RTC_ALMSTS_MASK 0x0100 194*4882a593Smuzhiyun #define WM8350_RTC_ALMSTS_SHIFT 8 195*4882a593Smuzhiyun #define WM8350_RTC_PINT 0x0070 196*4882a593Smuzhiyun #define WM8350_RTC_PINT_MASK 0x0070 197*4882a593Smuzhiyun #define WM8350_RTC_PINT_SHIFT 4 198*4882a593Smuzhiyun #define WM8350_RTC_DSW 0x000F 199*4882a593Smuzhiyun #define WM8350_RTC_DSW_MASK 0x000F 200*4882a593Smuzhiyun #define WM8350_RTC_DSW_SHIFT 0 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* Bit values for R23 (0x17) */ 203*4882a593Smuzhiyun #define WM8350_RTC_BCD_BINARY 0 204*4882a593Smuzhiyun #define WM8350_RTC_BCD_BCD 1 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define WM8350_RTC_12HR_24HR 0 207*4882a593Smuzhiyun #define WM8350_RTC_12HR_12HR 1 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define WM8350_RTC_DST_DISABLED 0 210*4882a593Smuzhiyun #define WM8350_RTC_DST_ENABLED 1 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #define WM8350_RTC_SET_RUN 0 213*4882a593Smuzhiyun #define WM8350_RTC_SET_SET 1 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define WM8350_RTC_STS_RUNNING 0 216*4882a593Smuzhiyun #define WM8350_RTC_STS_STOPPED 1 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #define WM8350_RTC_ALMSET_RUN 0 219*4882a593Smuzhiyun #define WM8350_RTC_ALMSET_SET 1 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define WM8350_RTC_ALMSTS_RUNNING 0 222*4882a593Smuzhiyun #define WM8350_RTC_ALMSTS_STOPPED 1 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #define WM8350_RTC_PINT_DISABLED 0 225*4882a593Smuzhiyun #define WM8350_RTC_PINT_SECS 1 226*4882a593Smuzhiyun #define WM8350_RTC_PINT_MINS 2 227*4882a593Smuzhiyun #define WM8350_RTC_PINT_HRS 3 228*4882a593Smuzhiyun #define WM8350_RTC_PINT_DAYS 4 229*4882a593Smuzhiyun #define WM8350_RTC_PINT_MTHS 5 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define WM8350_RTC_DSW_DISABLED 0 232*4882a593Smuzhiyun #define WM8350_RTC_DSW_1HZ 1 233*4882a593Smuzhiyun #define WM8350_RTC_DSW_2HZ 2 234*4882a593Smuzhiyun #define WM8350_RTC_DSW_4HZ 3 235*4882a593Smuzhiyun #define WM8350_RTC_DSW_8HZ 4 236*4882a593Smuzhiyun #define WM8350_RTC_DSW_16HZ 5 237*4882a593Smuzhiyun #define WM8350_RTC_DSW_32HZ 6 238*4882a593Smuzhiyun #define WM8350_RTC_DSW_64HZ 7 239*4882a593Smuzhiyun #define WM8350_RTC_DSW_128HZ 8 240*4882a593Smuzhiyun #define WM8350_RTC_DSW_256HZ 9 241*4882a593Smuzhiyun #define WM8350_RTC_DSW_512HZ 10 242*4882a593Smuzhiyun #define WM8350_RTC_DSW_1024HZ 11 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* 245*4882a593Smuzhiyun * R218 (0xDA) - RTC Tick Control 246*4882a593Smuzhiyun */ 247*4882a593Smuzhiyun #define WM8350_RTC_TICKSTS 0x4000 248*4882a593Smuzhiyun #define WM8350_RTC_CLKSRC 0x2000 249*4882a593Smuzhiyun #define WM8350_RTC_TRIM_MASK 0x03FF 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* 252*4882a593Smuzhiyun * RTC Interrupts. 253*4882a593Smuzhiyun */ 254*4882a593Smuzhiyun #define WM8350_IRQ_RTC_PER 7 255*4882a593Smuzhiyun #define WM8350_IRQ_RTC_SEC 8 256*4882a593Smuzhiyun #define WM8350_IRQ_RTC_ALM 9 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun struct wm8350_rtc { 259*4882a593Smuzhiyun struct platform_device *pdev; 260*4882a593Smuzhiyun struct rtc_device *rtc; 261*4882a593Smuzhiyun int alarm_enabled; /* used over suspend/resume */ 262*4882a593Smuzhiyun int update_enabled; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun #endif 266