xref: /OK3568_Linux_fs/kernel/include/linux/mfd/wm8350/audio.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * audio.h  --  Audio Driver for Wolfson WM8350 PMIC
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2007, 2008 Wolfson Microelectronics PLC
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __LINUX_MFD_WM8350_AUDIO_H_
9*4882a593Smuzhiyun #define __LINUX_MFD_WM8350_AUDIO_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define WM8350_CLOCK_CONTROL_1                  0x28
14*4882a593Smuzhiyun #define WM8350_CLOCK_CONTROL_2                  0x29
15*4882a593Smuzhiyun #define WM8350_FLL_CONTROL_1                    0x2A
16*4882a593Smuzhiyun #define WM8350_FLL_CONTROL_2                    0x2B
17*4882a593Smuzhiyun #define WM8350_FLL_CONTROL_3                    0x2C
18*4882a593Smuzhiyun #define WM8350_FLL_CONTROL_4                    0x2D
19*4882a593Smuzhiyun #define WM8350_DAC_CONTROL                      0x30
20*4882a593Smuzhiyun #define WM8350_DAC_DIGITAL_VOLUME_L             0x32
21*4882a593Smuzhiyun #define WM8350_DAC_DIGITAL_VOLUME_R             0x33
22*4882a593Smuzhiyun #define WM8350_DAC_LR_RATE                      0x35
23*4882a593Smuzhiyun #define WM8350_DAC_CLOCK_CONTROL                0x36
24*4882a593Smuzhiyun #define WM8350_DAC_MUTE                         0x3A
25*4882a593Smuzhiyun #define WM8350_DAC_MUTE_VOLUME                  0x3B
26*4882a593Smuzhiyun #define WM8350_DAC_SIDE                         0x3C
27*4882a593Smuzhiyun #define WM8350_ADC_CONTROL                      0x40
28*4882a593Smuzhiyun #define WM8350_ADC_DIGITAL_VOLUME_L             0x42
29*4882a593Smuzhiyun #define WM8350_ADC_DIGITAL_VOLUME_R             0x43
30*4882a593Smuzhiyun #define WM8350_ADC_DIVIDER                      0x44
31*4882a593Smuzhiyun #define WM8350_ADC_LR_RATE                      0x46
32*4882a593Smuzhiyun #define WM8350_INPUT_CONTROL                    0x48
33*4882a593Smuzhiyun #define WM8350_IN3_INPUT_CONTROL                0x49
34*4882a593Smuzhiyun #define WM8350_MIC_BIAS_CONTROL                 0x4A
35*4882a593Smuzhiyun #define WM8350_OUTPUT_CONTROL                   0x4C
36*4882a593Smuzhiyun #define WM8350_JACK_DETECT                      0x4D
37*4882a593Smuzhiyun #define WM8350_ANTI_POP_CONTROL                 0x4E
38*4882a593Smuzhiyun #define WM8350_LEFT_INPUT_VOLUME                0x50
39*4882a593Smuzhiyun #define WM8350_RIGHT_INPUT_VOLUME               0x51
40*4882a593Smuzhiyun #define WM8350_LEFT_MIXER_CONTROL               0x58
41*4882a593Smuzhiyun #define WM8350_RIGHT_MIXER_CONTROL              0x59
42*4882a593Smuzhiyun #define WM8350_OUT3_MIXER_CONTROL               0x5C
43*4882a593Smuzhiyun #define WM8350_OUT4_MIXER_CONTROL               0x5D
44*4882a593Smuzhiyun #define WM8350_OUTPUT_LEFT_MIXER_VOLUME         0x60
45*4882a593Smuzhiyun #define WM8350_OUTPUT_RIGHT_MIXER_VOLUME        0x61
46*4882a593Smuzhiyun #define WM8350_INPUT_MIXER_VOLUME_L             0x62
47*4882a593Smuzhiyun #define WM8350_INPUT_MIXER_VOLUME_R             0x63
48*4882a593Smuzhiyun #define WM8350_INPUT_MIXER_VOLUME               0x64
49*4882a593Smuzhiyun #define WM8350_LOUT1_VOLUME                     0x68
50*4882a593Smuzhiyun #define WM8350_ROUT1_VOLUME                     0x69
51*4882a593Smuzhiyun #define WM8350_LOUT2_VOLUME                     0x6A
52*4882a593Smuzhiyun #define WM8350_ROUT2_VOLUME                     0x6B
53*4882a593Smuzhiyun #define WM8350_BEEP_VOLUME                      0x6F
54*4882a593Smuzhiyun #define WM8350_AI_FORMATING                     0x70
55*4882a593Smuzhiyun #define WM8350_ADC_DAC_COMP                     0x71
56*4882a593Smuzhiyun #define WM8350_AI_ADC_CONTROL                   0x72
57*4882a593Smuzhiyun #define WM8350_AI_DAC_CONTROL                   0x73
58*4882a593Smuzhiyun #define WM8350_AIF_TEST                         0x74
59*4882a593Smuzhiyun #define WM8350_JACK_PIN_STATUS                  0xE7
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* Bit values for R08 (0x08) */
62*4882a593Smuzhiyun #define WM8350_CODEC_ISEL_1_5                   0	/* x1.5 */
63*4882a593Smuzhiyun #define WM8350_CODEC_ISEL_1_0                   1	/* x1.0 */
64*4882a593Smuzhiyun #define WM8350_CODEC_ISEL_0_75                  2	/* x0.75 */
65*4882a593Smuzhiyun #define WM8350_CODEC_ISEL_0_5                   3	/* x0.5 */
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define WM8350_VMID_OFF                         0
68*4882a593Smuzhiyun #define WM8350_VMID_300K                        1
69*4882a593Smuzhiyun #define WM8350_VMID_50K                         2
70*4882a593Smuzhiyun #define WM8350_VMID_5K                          3
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun  * R40 (0x28) - Clock Control 1
74*4882a593Smuzhiyun  */
75*4882a593Smuzhiyun #define WM8350_TOCLK_RATE                       0x4000
76*4882a593Smuzhiyun #define WM8350_MCLK_SEL                         0x0800
77*4882a593Smuzhiyun #define WM8350_MCLK_DIV_MASK                    0x0100
78*4882a593Smuzhiyun #define WM8350_BCLK_DIV_MASK                    0x00F0
79*4882a593Smuzhiyun #define WM8350_OPCLK_DIV_MASK                   0x0007
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun  * R41 (0x29) - Clock Control 2
83*4882a593Smuzhiyun  */
84*4882a593Smuzhiyun #define WM8350_LRC_ADC_SEL                      0x8000
85*4882a593Smuzhiyun #define WM8350_MCLK_DIR                         0x0001
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun  * R42 (0x2A) - FLL Control 1
89*4882a593Smuzhiyun  */
90*4882a593Smuzhiyun #define WM8350_FLL_DITHER_WIDTH_MASK            0x3000
91*4882a593Smuzhiyun #define WM8350_FLL_DITHER_HP                    0x0800
92*4882a593Smuzhiyun #define WM8350_FLL_OUTDIV_MASK                  0x0700
93*4882a593Smuzhiyun #define WM8350_FLL_RSP_RATE_MASK                0x00F0
94*4882a593Smuzhiyun #define WM8350_FLL_RATE_MASK                    0x0007
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun  * R43 (0x2B) - FLL Control 2
98*4882a593Smuzhiyun  */
99*4882a593Smuzhiyun #define WM8350_FLL_RATIO_MASK                   0xF800
100*4882a593Smuzhiyun #define WM8350_FLL_N_MASK                       0x03FF
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun  * R44 (0x2C) - FLL Control 3
104*4882a593Smuzhiyun  */
105*4882a593Smuzhiyun #define WM8350_FLL_K_MASK                       0xFFFF
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun  * R45 (0x2D) - FLL Control 4
109*4882a593Smuzhiyun  */
110*4882a593Smuzhiyun #define WM8350_FLL_FRAC                         0x0020
111*4882a593Smuzhiyun #define WM8350_FLL_SLOW_LOCK_REF                0x0010
112*4882a593Smuzhiyun #define WM8350_FLL_CLK_SRC_MASK                 0x0003
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun  * R48 (0x30) - DAC Control
116*4882a593Smuzhiyun  */
117*4882a593Smuzhiyun #define WM8350_DAC_MONO                         0x2000
118*4882a593Smuzhiyun #define WM8350_AIF_LRCLKRATE                    0x1000
119*4882a593Smuzhiyun #define WM8350_DEEMP_MASK                       0x0030
120*4882a593Smuzhiyun #define WM8350_DACL_DATINV                      0x0002
121*4882a593Smuzhiyun #define WM8350_DACR_DATINV                      0x0001
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /*
124*4882a593Smuzhiyun  * R50 (0x32) - DAC Digital Volume L
125*4882a593Smuzhiyun  */
126*4882a593Smuzhiyun #define WM8350_DAC_VU                           0x0100
127*4882a593Smuzhiyun #define WM8350_DACL_VOL_MASK                    0x00FF
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun  * R51 (0x33) - DAC Digital Volume R
131*4882a593Smuzhiyun  */
132*4882a593Smuzhiyun #define WM8350_DAC_VU                           0x0100
133*4882a593Smuzhiyun #define WM8350_DACR_VOL_MASK                    0x00FF
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun  * R53 (0x35) - DAC LR Rate
137*4882a593Smuzhiyun  */
138*4882a593Smuzhiyun #define WM8350_DACLRC_ENA                       0x0800
139*4882a593Smuzhiyun #define WM8350_DACLRC_RATE_MASK                 0x07FF
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun /*
142*4882a593Smuzhiyun  * R54 (0x36) - DAC Clock Control
143*4882a593Smuzhiyun  */
144*4882a593Smuzhiyun #define WM8350_DACCLK_POL                       0x0010
145*4882a593Smuzhiyun #define WM8350_DAC_CLKDIV_MASK                  0x0007
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun  * R58 (0x3A) - DAC Mute
149*4882a593Smuzhiyun  */
150*4882a593Smuzhiyun #define WM8350_DAC_MUTE_ENA                     0x4000
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun  * R59 (0x3B) - DAC Mute Volume
154*4882a593Smuzhiyun  */
155*4882a593Smuzhiyun #define WM8350_DAC_MUTEMODE                     0x4000
156*4882a593Smuzhiyun #define WM8350_DAC_MUTERATE                     0x2000
157*4882a593Smuzhiyun #define WM8350_DAC_SB_FILT                      0x1000
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun /*
160*4882a593Smuzhiyun  * R60 (0x3C) - DAC Side
161*4882a593Smuzhiyun  */
162*4882a593Smuzhiyun #define WM8350_ADC_TO_DACL_MASK                 0x3000
163*4882a593Smuzhiyun #define WM8350_ADC_TO_DACR_MASK                 0x0C00
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun  * R64 (0x40) - ADC Control
167*4882a593Smuzhiyun  */
168*4882a593Smuzhiyun #define WM8350_ADC_HPF_CUT_MASK                 0x0300
169*4882a593Smuzhiyun #define WM8350_ADCL_DATINV                      0x0002
170*4882a593Smuzhiyun #define WM8350_ADCR_DATINV                      0x0001
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun /*
173*4882a593Smuzhiyun  * R66 (0x42) - ADC Digital Volume L
174*4882a593Smuzhiyun  */
175*4882a593Smuzhiyun #define WM8350_ADC_VU                           0x0100
176*4882a593Smuzhiyun #define WM8350_ADCL_VOL_MASK                    0x00FF
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /*
179*4882a593Smuzhiyun  * R67 (0x43) - ADC Digital Volume R
180*4882a593Smuzhiyun  */
181*4882a593Smuzhiyun #define WM8350_ADC_VU                           0x0100
182*4882a593Smuzhiyun #define WM8350_ADCR_VOL_MASK                    0x00FF
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /*
185*4882a593Smuzhiyun  * R68 (0x44) - ADC Divider
186*4882a593Smuzhiyun  */
187*4882a593Smuzhiyun #define WM8350_ADCL_DAC_SVOL_MASK               0x0F00
188*4882a593Smuzhiyun #define WM8350_ADCR_DAC_SVOL_MASK               0x00F0
189*4882a593Smuzhiyun #define WM8350_ADCCLK_POL                       0x0008
190*4882a593Smuzhiyun #define WM8350_ADC_CLKDIV_MASK                  0x0007
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun /*
193*4882a593Smuzhiyun  * R70 (0x46) - ADC LR Rate
194*4882a593Smuzhiyun  */
195*4882a593Smuzhiyun #define WM8350_ADCLRC_ENA                       0x0800
196*4882a593Smuzhiyun #define WM8350_ADCLRC_RATE_MASK                 0x07FF
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun /*
199*4882a593Smuzhiyun  * R72 (0x48) - Input Control
200*4882a593Smuzhiyun  */
201*4882a593Smuzhiyun #define WM8350_IN2R_ENA                         0x0400
202*4882a593Smuzhiyun #define WM8350_IN1RN_ENA                        0x0200
203*4882a593Smuzhiyun #define WM8350_IN1RP_ENA                        0x0100
204*4882a593Smuzhiyun #define WM8350_IN2L_ENA                         0x0004
205*4882a593Smuzhiyun #define WM8350_IN1LN_ENA                        0x0002
206*4882a593Smuzhiyun #define WM8350_IN1LP_ENA                        0x0001
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun /*
209*4882a593Smuzhiyun  * R73 (0x49) - IN3 Input Control
210*4882a593Smuzhiyun  */
211*4882a593Smuzhiyun #define WM8350_IN3R_SHORT                       0x4000
212*4882a593Smuzhiyun #define WM8350_IN3L_SHORT                       0x0040
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /*
215*4882a593Smuzhiyun  * R74 (0x4A) - Mic Bias Control
216*4882a593Smuzhiyun  */
217*4882a593Smuzhiyun #define WM8350_MICBSEL                          0x4000
218*4882a593Smuzhiyun #define WM8350_MCDTHR_MASK                      0x001C
219*4882a593Smuzhiyun #define WM8350_MCDSCTHR_MASK                    0x0003
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun /*
222*4882a593Smuzhiyun  * R76 (0x4C) - Output Control
223*4882a593Smuzhiyun  */
224*4882a593Smuzhiyun #define WM8350_OUT4_VROI                        0x0800
225*4882a593Smuzhiyun #define WM8350_OUT3_VROI                        0x0400
226*4882a593Smuzhiyun #define WM8350_OUT2_VROI                        0x0200
227*4882a593Smuzhiyun #define WM8350_OUT1_VROI                        0x0100
228*4882a593Smuzhiyun #define WM8350_OUT2_FB                          0x0004
229*4882a593Smuzhiyun #define WM8350_OUT1_FB                          0x0001
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun /*
232*4882a593Smuzhiyun  * R77 (0x4D) - Jack Detect
233*4882a593Smuzhiyun  */
234*4882a593Smuzhiyun #define WM8350_JDL_ENA                          0x8000
235*4882a593Smuzhiyun #define WM8350_JDR_ENA                          0x4000
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun /*
238*4882a593Smuzhiyun  * R78 (0x4E) - Anti Pop Control
239*4882a593Smuzhiyun  */
240*4882a593Smuzhiyun #define WM8350_ANTI_POP_MASK                    0x0300
241*4882a593Smuzhiyun #define WM8350_DIS_OP_LN4_MASK                  0x00C0
242*4882a593Smuzhiyun #define WM8350_DIS_OP_LN3_MASK                  0x0030
243*4882a593Smuzhiyun #define WM8350_DIS_OP_OUT2_MASK                 0x000C
244*4882a593Smuzhiyun #define WM8350_DIS_OP_OUT1_MASK                 0x0003
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun /*
247*4882a593Smuzhiyun  * R80 (0x50) - Left Input Volume
248*4882a593Smuzhiyun  */
249*4882a593Smuzhiyun #define WM8350_INL_MUTE                         0x4000
250*4882a593Smuzhiyun #define WM8350_INL_ZC                           0x2000
251*4882a593Smuzhiyun #define WM8350_IN_VU                            0x0100
252*4882a593Smuzhiyun #define WM8350_INL_VOL_MASK                     0x00FC
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /*
255*4882a593Smuzhiyun  * R81 (0x51) - Right Input Volume
256*4882a593Smuzhiyun  */
257*4882a593Smuzhiyun #define WM8350_INR_MUTE                         0x4000
258*4882a593Smuzhiyun #define WM8350_INR_ZC                           0x2000
259*4882a593Smuzhiyun #define WM8350_IN_VU                            0x0100
260*4882a593Smuzhiyun #define WM8350_INR_VOL_MASK                     0x00FC
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun /*
263*4882a593Smuzhiyun  * R88 (0x58) - Left Mixer Control
264*4882a593Smuzhiyun  */
265*4882a593Smuzhiyun #define WM8350_DACR_TO_MIXOUTL                  0x1000
266*4882a593Smuzhiyun #define WM8350_DACL_TO_MIXOUTL                  0x0800
267*4882a593Smuzhiyun #define WM8350_IN3L_TO_MIXOUTL                  0x0004
268*4882a593Smuzhiyun #define WM8350_INR_TO_MIXOUTL                   0x0002
269*4882a593Smuzhiyun #define WM8350_INL_TO_MIXOUTL                   0x0001
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /*
272*4882a593Smuzhiyun  * R89 (0x59) - Right Mixer Control
273*4882a593Smuzhiyun  */
274*4882a593Smuzhiyun #define WM8350_DACR_TO_MIXOUTR                  0x1000
275*4882a593Smuzhiyun #define WM8350_DACL_TO_MIXOUTR                  0x0800
276*4882a593Smuzhiyun #define WM8350_IN3R_TO_MIXOUTR                  0x0008
277*4882a593Smuzhiyun #define WM8350_INR_TO_MIXOUTR                   0x0002
278*4882a593Smuzhiyun #define WM8350_INL_TO_MIXOUTR                   0x0001
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun /*
281*4882a593Smuzhiyun  * R92 (0x5C) - OUT3 Mixer Control
282*4882a593Smuzhiyun  */
283*4882a593Smuzhiyun #define WM8350_DACL_TO_OUT3                     0x0800
284*4882a593Smuzhiyun #define WM8350_MIXINL_TO_OUT3                   0x0100
285*4882a593Smuzhiyun #define WM8350_OUT4_TO_OUT3                     0x0008
286*4882a593Smuzhiyun #define WM8350_MIXOUTL_TO_OUT3                  0x0001
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun /*
289*4882a593Smuzhiyun  * R93 (0x5D) - OUT4 Mixer Control
290*4882a593Smuzhiyun  */
291*4882a593Smuzhiyun #define WM8350_DACR_TO_OUT4                     0x1000
292*4882a593Smuzhiyun #define WM8350_DACL_TO_OUT4                     0x0800
293*4882a593Smuzhiyun #define WM8350_OUT4_ATTN                        0x0400
294*4882a593Smuzhiyun #define WM8350_MIXINR_TO_OUT4                   0x0200
295*4882a593Smuzhiyun #define WM8350_OUT3_TO_OUT4                     0x0004
296*4882a593Smuzhiyun #define WM8350_MIXOUTR_TO_OUT4                  0x0002
297*4882a593Smuzhiyun #define WM8350_MIXOUTL_TO_OUT4                  0x0001
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun /*
300*4882a593Smuzhiyun  * R96 (0x60) - Output Left Mixer Volume
301*4882a593Smuzhiyun  */
302*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_MASK            0x0E00
303*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_SHIFT                9
304*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_MASK             0x00E0
305*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_SHIFT                 5
306*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_MASK             0x000E
307*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_SHIFT                 1
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun /* Bit values for R96 (0x60) */
310*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_OFF                  0
311*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_M12DB                1
312*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_M9DB                 2
313*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_M6DB                 3
314*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_M3DB                 4
315*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_0DB                  5
316*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_3DB                  6
317*4882a593Smuzhiyun #define WM8350_IN3L_MIXOUTL_VOL_6DB                  7
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_OFF                   0
320*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_M12DB                 1
321*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_M9DB                  2
322*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_M6DB                  3
323*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_M3DB                  4
324*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_0DB                   5
325*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_3DB                   6
326*4882a593Smuzhiyun #define WM8350_INR_MIXOUTL_VOL_6DB                   7
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_OFF                   0
329*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_M12DB                 1
330*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_M9DB                  2
331*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_M6DB                  3
332*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_M3DB                  4
333*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_0DB                   5
334*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_3DB                   6
335*4882a593Smuzhiyun #define WM8350_INL_MIXOUTL_VOL_6DB                   7
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun /*
338*4882a593Smuzhiyun  * R97 (0x61) - Output Right Mixer Volume
339*4882a593Smuzhiyun  */
340*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_MASK            0xE000
341*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_SHIFT               13
342*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_MASK             0x00E0
343*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_SHIFT                 5
344*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_MASK             0x000E
345*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_SHIFT                 1
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun /* Bit values for R96 (0x60) */
348*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_OFF                  0
349*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_M12DB                1
350*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_M9DB                 2
351*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_M6DB                 3
352*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_M3DB                 4
353*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_0DB                  5
354*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_3DB                  6
355*4882a593Smuzhiyun #define WM8350_IN3R_MIXOUTR_VOL_6DB                  7
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_OFF                   0
358*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_M12DB                 1
359*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_M9DB                  2
360*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_M6DB                  3
361*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_M3DB                  4
362*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_0DB                   5
363*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_3DB                   6
364*4882a593Smuzhiyun #define WM8350_INR_MIXOUTR_VOL_6DB                   7
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_OFF                   0
367*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_M12DB                 1
368*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_M9DB                  2
369*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_M6DB                  3
370*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_M3DB                  4
371*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_0DB                   5
372*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_3DB                   6
373*4882a593Smuzhiyun #define WM8350_INL_MIXOUTR_VOL_6DB                   7
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun /*
376*4882a593Smuzhiyun  * R98 (0x62) - Input Mixer Volume L
377*4882a593Smuzhiyun  */
378*4882a593Smuzhiyun #define WM8350_IN3L_MIXINL_VOL_MASK             0x0E00
379*4882a593Smuzhiyun #define WM8350_IN2L_MIXINL_VOL_MASK             0x000E
380*4882a593Smuzhiyun #define WM8350_INL_MIXINL_VOL                   0x0001
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun /*
383*4882a593Smuzhiyun  * R99 (0x63) - Input Mixer Volume R
384*4882a593Smuzhiyun  */
385*4882a593Smuzhiyun #define WM8350_IN3R_MIXINR_VOL_MASK             0xE000
386*4882a593Smuzhiyun #define WM8350_IN2R_MIXINR_VOL_MASK             0x00E0
387*4882a593Smuzhiyun #define WM8350_INR_MIXINR_VOL                   0x0001
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun /*
390*4882a593Smuzhiyun  * R100 (0x64) - Input Mixer Volume
391*4882a593Smuzhiyun  */
392*4882a593Smuzhiyun #define WM8350_OUT4_MIXIN_DST                   0x8000
393*4882a593Smuzhiyun #define WM8350_OUT4_MIXIN_VOL_MASK              0x000E
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun /*
396*4882a593Smuzhiyun  * R104 (0x68) - LOUT1 Volume
397*4882a593Smuzhiyun  */
398*4882a593Smuzhiyun #define WM8350_OUT1L_MUTE                       0x4000
399*4882a593Smuzhiyun #define WM8350_OUT1L_ZC                         0x2000
400*4882a593Smuzhiyun #define WM8350_OUT1_VU                          0x0100
401*4882a593Smuzhiyun #define WM8350_OUT1L_VOL_MASK                   0x00FC
402*4882a593Smuzhiyun #define WM8350_OUT1L_VOL_SHIFT                       2
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun /*
405*4882a593Smuzhiyun  * R105 (0x69) - ROUT1 Volume
406*4882a593Smuzhiyun  */
407*4882a593Smuzhiyun #define WM8350_OUT1R_MUTE                       0x4000
408*4882a593Smuzhiyun #define WM8350_OUT1R_ZC                         0x2000
409*4882a593Smuzhiyun #define WM8350_OUT1_VU                          0x0100
410*4882a593Smuzhiyun #define WM8350_OUT1R_VOL_MASK                   0x00FC
411*4882a593Smuzhiyun #define WM8350_OUT1R_VOL_SHIFT                       2
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun /*
414*4882a593Smuzhiyun  * R106 (0x6A) - LOUT2 Volume
415*4882a593Smuzhiyun  */
416*4882a593Smuzhiyun #define WM8350_OUT2L_MUTE                       0x4000
417*4882a593Smuzhiyun #define WM8350_OUT2L_ZC                         0x2000
418*4882a593Smuzhiyun #define WM8350_OUT2_VU                          0x0100
419*4882a593Smuzhiyun #define WM8350_OUT2L_VOL_MASK                   0x00FC
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun /*
422*4882a593Smuzhiyun  * R107 (0x6B) - ROUT2 Volume
423*4882a593Smuzhiyun  */
424*4882a593Smuzhiyun #define WM8350_OUT2R_MUTE                       0x4000
425*4882a593Smuzhiyun #define WM8350_OUT2R_ZC                         0x2000
426*4882a593Smuzhiyun #define WM8350_OUT2R_INV                        0x0400
427*4882a593Smuzhiyun #define WM8350_OUT2R_INV_MUTE                   0x0200
428*4882a593Smuzhiyun #define WM8350_OUT2_VU                          0x0100
429*4882a593Smuzhiyun #define WM8350_OUT2R_VOL_MASK                   0x00FC
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun /*
432*4882a593Smuzhiyun  * R111 (0x6F) - BEEP Volume
433*4882a593Smuzhiyun  */
434*4882a593Smuzhiyun #define WM8350_IN3R_OUT2R_VOL_MASK              0x00E0
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun /*
437*4882a593Smuzhiyun  * R112 (0x70) - AI Formating
438*4882a593Smuzhiyun  */
439*4882a593Smuzhiyun #define WM8350_AIF_BCLK_INV                     0x8000
440*4882a593Smuzhiyun #define WM8350_AIF_TRI                          0x2000
441*4882a593Smuzhiyun #define WM8350_AIF_LRCLK_INV                    0x1000
442*4882a593Smuzhiyun #define WM8350_AIF_WL_MASK                      0x0C00
443*4882a593Smuzhiyun #define WM8350_AIF_FMT_MASK                     0x0300
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun /*
446*4882a593Smuzhiyun  * R113 (0x71) - ADC DAC COMP
447*4882a593Smuzhiyun  */
448*4882a593Smuzhiyun #define WM8350_DAC_COMP                         0x0080
449*4882a593Smuzhiyun #define WM8350_DAC_COMPMODE                     0x0040
450*4882a593Smuzhiyun #define WM8350_ADC_COMP                         0x0020
451*4882a593Smuzhiyun #define WM8350_ADC_COMPMODE                     0x0010
452*4882a593Smuzhiyun #define WM8350_LOOPBACK                         0x0001
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun /*
455*4882a593Smuzhiyun  * R114 (0x72) - AI ADC Control
456*4882a593Smuzhiyun  */
457*4882a593Smuzhiyun #define WM8350_AIFADC_PD                        0x0080
458*4882a593Smuzhiyun #define WM8350_AIFADCL_SRC                      0x0040
459*4882a593Smuzhiyun #define WM8350_AIFADCR_SRC                      0x0020
460*4882a593Smuzhiyun #define WM8350_AIFADC_TDM_CHAN                  0x0010
461*4882a593Smuzhiyun #define WM8350_AIFADC_TDM                       0x0008
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun /*
464*4882a593Smuzhiyun  * R115 (0x73) - AI DAC Control
465*4882a593Smuzhiyun  */
466*4882a593Smuzhiyun #define WM8350_BCLK_MSTR                        0x4000
467*4882a593Smuzhiyun #define WM8350_AIFDAC_PD                        0x0080
468*4882a593Smuzhiyun #define WM8350_DACL_SRC                         0x0040
469*4882a593Smuzhiyun #define WM8350_DACR_SRC                         0x0020
470*4882a593Smuzhiyun #define WM8350_AIFDAC_TDM_CHAN                  0x0010
471*4882a593Smuzhiyun #define WM8350_AIFDAC_TDM                       0x0008
472*4882a593Smuzhiyun #define WM8350_DAC_BOOST_MASK                   0x0003
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun /*
475*4882a593Smuzhiyun  * R116 (0x74) - AIF Test
476*4882a593Smuzhiyun  */
477*4882a593Smuzhiyun #define WM8350_CODEC_BYP                        0x4000
478*4882a593Smuzhiyun #define WM8350_AIFADC_WR_TST                    0x2000
479*4882a593Smuzhiyun #define WM8350_AIFADC_RD_TST                    0x1000
480*4882a593Smuzhiyun #define WM8350_AIFDAC_WR_TST                    0x0800
481*4882a593Smuzhiyun #define WM8350_AIFDAC_RD_TST                    0x0400
482*4882a593Smuzhiyun #define WM8350_AIFADC_ASYN                      0x0020
483*4882a593Smuzhiyun #define WM8350_AIFDAC_ASYN                      0x0010
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun /*
486*4882a593Smuzhiyun  * R231 (0xE7) - Jack Status
487*4882a593Smuzhiyun  */
488*4882a593Smuzhiyun #define WM8350_JACK_L_LVL			0x0800
489*4882a593Smuzhiyun #define WM8350_JACK_R_LVL                       0x0400
490*4882a593Smuzhiyun #define WM8350_JACK_MICSCD_LVL			0x0200
491*4882a593Smuzhiyun #define WM8350_JACK_MICSD_LVL			0x0100
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun /*
494*4882a593Smuzhiyun  * WM8350 Platform setup
495*4882a593Smuzhiyun  */
496*4882a593Smuzhiyun #define WM8350_S_CURVE_NONE			0x0
497*4882a593Smuzhiyun #define WM8350_S_CURVE_FAST			0x1
498*4882a593Smuzhiyun #define WM8350_S_CURVE_MEDIUM			0x2
499*4882a593Smuzhiyun #define WM8350_S_CURVE_SLOW			0x3
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun #define WM8350_DISCHARGE_OFF			0x0
502*4882a593Smuzhiyun #define WM8350_DISCHARGE_FAST			0x1
503*4882a593Smuzhiyun #define WM8350_DISCHARGE_MEDIUM			0x2
504*4882a593Smuzhiyun #define WM8350_DISCHARGE_SLOW			0x3
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun #define WM8350_TIE_OFF_500R			0x0
507*4882a593Smuzhiyun #define WM8350_TIE_OFF_30K			0x1
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun /*
510*4882a593Smuzhiyun  * Clock sources & directions
511*4882a593Smuzhiyun  */
512*4882a593Smuzhiyun #define WM8350_SYSCLK				0
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun #define WM8350_MCLK_SEL_PLL_MCLK		0
515*4882a593Smuzhiyun #define WM8350_MCLK_SEL_PLL_DAC			1
516*4882a593Smuzhiyun #define WM8350_MCLK_SEL_PLL_ADC			2
517*4882a593Smuzhiyun #define WM8350_MCLK_SEL_PLL_32K			3
518*4882a593Smuzhiyun #define WM8350_MCLK_SEL_MCLK			5
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun /* clock divider id's */
521*4882a593Smuzhiyun #define WM8350_ADC_CLKDIV			0
522*4882a593Smuzhiyun #define WM8350_DAC_CLKDIV			1
523*4882a593Smuzhiyun #define WM8350_BCLK_CLKDIV			2
524*4882a593Smuzhiyun #define WM8350_OPCLK_CLKDIV			3
525*4882a593Smuzhiyun #define WM8350_TO_CLKDIV			4
526*4882a593Smuzhiyun #define WM8350_SYS_CLKDIV			5
527*4882a593Smuzhiyun #define WM8350_DACLR_CLKDIV			6
528*4882a593Smuzhiyun #define WM8350_ADCLR_CLKDIV			7
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun /* ADC clock dividers */
531*4882a593Smuzhiyun #define WM8350_ADCDIV_1				0x0
532*4882a593Smuzhiyun #define WM8350_ADCDIV_1_5			0x1
533*4882a593Smuzhiyun #define WM8350_ADCDIV_2				0x2
534*4882a593Smuzhiyun #define WM8350_ADCDIV_3				0x3
535*4882a593Smuzhiyun #define WM8350_ADCDIV_4				0x4
536*4882a593Smuzhiyun #define WM8350_ADCDIV_5_5			0x5
537*4882a593Smuzhiyun #define WM8350_ADCDIV_6				0x6
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun /* ADC clock dividers */
540*4882a593Smuzhiyun #define WM8350_DACDIV_1				0x0
541*4882a593Smuzhiyun #define WM8350_DACDIV_1_5			0x1
542*4882a593Smuzhiyun #define WM8350_DACDIV_2				0x2
543*4882a593Smuzhiyun #define WM8350_DACDIV_3				0x3
544*4882a593Smuzhiyun #define WM8350_DACDIV_4				0x4
545*4882a593Smuzhiyun #define WM8350_DACDIV_5_5			0x5
546*4882a593Smuzhiyun #define WM8350_DACDIV_6				0x6
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun /* BCLK clock dividers */
549*4882a593Smuzhiyun #define WM8350_BCLK_DIV_1			(0x0 << 4)
550*4882a593Smuzhiyun #define WM8350_BCLK_DIV_1_5			(0x1 << 4)
551*4882a593Smuzhiyun #define WM8350_BCLK_DIV_2			(0x2 << 4)
552*4882a593Smuzhiyun #define WM8350_BCLK_DIV_3			(0x3 << 4)
553*4882a593Smuzhiyun #define WM8350_BCLK_DIV_4			(0x4 << 4)
554*4882a593Smuzhiyun #define WM8350_BCLK_DIV_5_5			(0x5 << 4)
555*4882a593Smuzhiyun #define WM8350_BCLK_DIV_6			(0x6 << 4)
556*4882a593Smuzhiyun #define WM8350_BCLK_DIV_8			(0x7 << 4)
557*4882a593Smuzhiyun #define WM8350_BCLK_DIV_11			(0x8 << 4)
558*4882a593Smuzhiyun #define WM8350_BCLK_DIV_12			(0x9 << 4)
559*4882a593Smuzhiyun #define WM8350_BCLK_DIV_16			(0xa << 4)
560*4882a593Smuzhiyun #define WM8350_BCLK_DIV_22			(0xb << 4)
561*4882a593Smuzhiyun #define WM8350_BCLK_DIV_24			(0xc << 4)
562*4882a593Smuzhiyun #define WM8350_BCLK_DIV_32			(0xd << 4)
563*4882a593Smuzhiyun #define WM8350_BCLK_DIV_44			(0xe << 4)
564*4882a593Smuzhiyun #define WM8350_BCLK_DIV_48			(0xf << 4)
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun /* Sys (MCLK) clock dividers */
567*4882a593Smuzhiyun #define WM8350_MCLK_DIV_1			(0x0 << 8)
568*4882a593Smuzhiyun #define WM8350_MCLK_DIV_2			(0x1 << 8)
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun /* OP clock dividers */
571*4882a593Smuzhiyun #define WM8350_OPCLK_DIV_1			0x0
572*4882a593Smuzhiyun #define WM8350_OPCLK_DIV_2			0x1
573*4882a593Smuzhiyun #define WM8350_OPCLK_DIV_3			0x2
574*4882a593Smuzhiyun #define WM8350_OPCLK_DIV_4			0x3
575*4882a593Smuzhiyun #define WM8350_OPCLK_DIV_5_5			0x4
576*4882a593Smuzhiyun #define WM8350_OPCLK_DIV_6			0x5
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun /* DAI ID */
579*4882a593Smuzhiyun #define WM8350_HIFI_DAI				0
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun /*
582*4882a593Smuzhiyun  * Audio interrupts.
583*4882a593Smuzhiyun  */
584*4882a593Smuzhiyun #define WM8350_IRQ_CODEC_JCK_DET_L		39
585*4882a593Smuzhiyun #define WM8350_IRQ_CODEC_JCK_DET_R		40
586*4882a593Smuzhiyun #define WM8350_IRQ_CODEC_MICSCD			41
587*4882a593Smuzhiyun #define WM8350_IRQ_CODEC_MICD			42
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun /*
590*4882a593Smuzhiyun  * WM8350 Platform data.
591*4882a593Smuzhiyun  *
592*4882a593Smuzhiyun  * This must be initialised per platform for best audio performance.
593*4882a593Smuzhiyun  * Please see WM8350 datasheet for information.
594*4882a593Smuzhiyun  */
595*4882a593Smuzhiyun struct wm8350_audio_platform_data {
596*4882a593Smuzhiyun 	int vmid_discharge_msecs;	/* VMID --> OFF discharge time */
597*4882a593Smuzhiyun 	int drain_msecs;	/* OFF drain time */
598*4882a593Smuzhiyun 	int cap_discharge_msecs;	/* Cap ON (from OFF) discharge time */
599*4882a593Smuzhiyun 	int vmid_charge_msecs;	/* vmid power up time */
600*4882a593Smuzhiyun 	u32 vmid_s_curve:2;	/* vmid enable s curve speed */
601*4882a593Smuzhiyun 	u32 dis_out4:2;		/* out4 discharge speed */
602*4882a593Smuzhiyun 	u32 dis_out3:2;		/* out3 discharge speed */
603*4882a593Smuzhiyun 	u32 dis_out2:2;		/* out2 discharge speed */
604*4882a593Smuzhiyun 	u32 dis_out1:2;		/* out1 discharge speed */
605*4882a593Smuzhiyun 	u32 vroi_out4:1;	/* out4 tie off */
606*4882a593Smuzhiyun 	u32 vroi_out3:1;	/* out3 tie off */
607*4882a593Smuzhiyun 	u32 vroi_out2:1;	/* out2 tie off */
608*4882a593Smuzhiyun 	u32 vroi_out1:1;	/* out1 tie off */
609*4882a593Smuzhiyun 	u32 vroi_enable:1;	/* enable tie off */
610*4882a593Smuzhiyun 	u32 codec_current_on:2;	/* current level ON */
611*4882a593Smuzhiyun 	u32 codec_current_standby:2;	/* current level STANDBY */
612*4882a593Smuzhiyun 	u32 codec_current_charge:2;	/* codec current @ vmid charge */
613*4882a593Smuzhiyun };
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun struct wm8350_codec {
616*4882a593Smuzhiyun 	struct platform_device *pdev;
617*4882a593Smuzhiyun 	struct wm8350_audio_platform_data *platform_data;
618*4882a593Smuzhiyun };
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun #endif
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