1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/linux/mfd/wm831x/pmu.h -- PMU for WM831x 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MFD_WM831X_PMU_H__ 11*4882a593Smuzhiyun #define __MFD_WM831X_PMU_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * R16387 (0x4003) - Power State 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define WM831X_CHIP_ON 0x8000 /* CHIP_ON */ 17*4882a593Smuzhiyun #define WM831X_CHIP_ON_MASK 0x8000 /* CHIP_ON */ 18*4882a593Smuzhiyun #define WM831X_CHIP_ON_SHIFT 15 /* CHIP_ON */ 19*4882a593Smuzhiyun #define WM831X_CHIP_ON_WIDTH 1 /* CHIP_ON */ 20*4882a593Smuzhiyun #define WM831X_CHIP_SLP 0x4000 /* CHIP_SLP */ 21*4882a593Smuzhiyun #define WM831X_CHIP_SLP_MASK 0x4000 /* CHIP_SLP */ 22*4882a593Smuzhiyun #define WM831X_CHIP_SLP_SHIFT 14 /* CHIP_SLP */ 23*4882a593Smuzhiyun #define WM831X_CHIP_SLP_WIDTH 1 /* CHIP_SLP */ 24*4882a593Smuzhiyun #define WM831X_REF_LP 0x1000 /* REF_LP */ 25*4882a593Smuzhiyun #define WM831X_REF_LP_MASK 0x1000 /* REF_LP */ 26*4882a593Smuzhiyun #define WM831X_REF_LP_SHIFT 12 /* REF_LP */ 27*4882a593Smuzhiyun #define WM831X_REF_LP_WIDTH 1 /* REF_LP */ 28*4882a593Smuzhiyun #define WM831X_PWRSTATE_DLY_MASK 0x0C00 /* PWRSTATE_DLY - [11:10] */ 29*4882a593Smuzhiyun #define WM831X_PWRSTATE_DLY_SHIFT 10 /* PWRSTATE_DLY - [11:10] */ 30*4882a593Smuzhiyun #define WM831X_PWRSTATE_DLY_WIDTH 2 /* PWRSTATE_DLY - [11:10] */ 31*4882a593Smuzhiyun #define WM831X_SWRST_DLY 0x0200 /* SWRST_DLY */ 32*4882a593Smuzhiyun #define WM831X_SWRST_DLY_MASK 0x0200 /* SWRST_DLY */ 33*4882a593Smuzhiyun #define WM831X_SWRST_DLY_SHIFT 9 /* SWRST_DLY */ 34*4882a593Smuzhiyun #define WM831X_SWRST_DLY_WIDTH 1 /* SWRST_DLY */ 35*4882a593Smuzhiyun #define WM831X_USB100MA_STARTUP_MASK 0x0030 /* USB100MA_STARTUP - [5:4] */ 36*4882a593Smuzhiyun #define WM831X_USB100MA_STARTUP_SHIFT 4 /* USB100MA_STARTUP - [5:4] */ 37*4882a593Smuzhiyun #define WM831X_USB100MA_STARTUP_WIDTH 2 /* USB100MA_STARTUP - [5:4] */ 38*4882a593Smuzhiyun #define WM831X_USB_CURR_STS 0x0008 /* USB_CURR_STS */ 39*4882a593Smuzhiyun #define WM831X_USB_CURR_STS_MASK 0x0008 /* USB_CURR_STS */ 40*4882a593Smuzhiyun #define WM831X_USB_CURR_STS_SHIFT 3 /* USB_CURR_STS */ 41*4882a593Smuzhiyun #define WM831X_USB_CURR_STS_WIDTH 1 /* USB_CURR_STS */ 42*4882a593Smuzhiyun #define WM831X_USB_ILIM_MASK 0x0007 /* USB_ILIM - [2:0] */ 43*4882a593Smuzhiyun #define WM831X_USB_ILIM_SHIFT 0 /* USB_ILIM - [2:0] */ 44*4882a593Smuzhiyun #define WM831X_USB_ILIM_WIDTH 3 /* USB_ILIM - [2:0] */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * R16397 (0x400D) - System Status 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define WM831X_THW_STS 0x8000 /* THW_STS */ 50*4882a593Smuzhiyun #define WM831X_THW_STS_MASK 0x8000 /* THW_STS */ 51*4882a593Smuzhiyun #define WM831X_THW_STS_SHIFT 15 /* THW_STS */ 52*4882a593Smuzhiyun #define WM831X_THW_STS_WIDTH 1 /* THW_STS */ 53*4882a593Smuzhiyun #define WM831X_PWR_SRC_BATT 0x0400 /* PWR_SRC_BATT */ 54*4882a593Smuzhiyun #define WM831X_PWR_SRC_BATT_MASK 0x0400 /* PWR_SRC_BATT */ 55*4882a593Smuzhiyun #define WM831X_PWR_SRC_BATT_SHIFT 10 /* PWR_SRC_BATT */ 56*4882a593Smuzhiyun #define WM831X_PWR_SRC_BATT_WIDTH 1 /* PWR_SRC_BATT */ 57*4882a593Smuzhiyun #define WM831X_PWR_WALL 0x0200 /* PWR_WALL */ 58*4882a593Smuzhiyun #define WM831X_PWR_WALL_MASK 0x0200 /* PWR_WALL */ 59*4882a593Smuzhiyun #define WM831X_PWR_WALL_SHIFT 9 /* PWR_WALL */ 60*4882a593Smuzhiyun #define WM831X_PWR_WALL_WIDTH 1 /* PWR_WALL */ 61*4882a593Smuzhiyun #define WM831X_PWR_USB 0x0100 /* PWR_USB */ 62*4882a593Smuzhiyun #define WM831X_PWR_USB_MASK 0x0100 /* PWR_USB */ 63*4882a593Smuzhiyun #define WM831X_PWR_USB_SHIFT 8 /* PWR_USB */ 64*4882a593Smuzhiyun #define WM831X_PWR_USB_WIDTH 1 /* PWR_USB */ 65*4882a593Smuzhiyun #define WM831X_MAIN_STATE_MASK 0x001F /* MAIN_STATE - [4:0] */ 66*4882a593Smuzhiyun #define WM831X_MAIN_STATE_SHIFT 0 /* MAIN_STATE - [4:0] */ 67*4882a593Smuzhiyun #define WM831X_MAIN_STATE_WIDTH 5 /* MAIN_STATE - [4:0] */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * R16456 (0x4048) - Charger Control 1 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun #define WM831X_CHG_ENA 0x8000 /* CHG_ENA */ 73*4882a593Smuzhiyun #define WM831X_CHG_ENA_MASK 0x8000 /* CHG_ENA */ 74*4882a593Smuzhiyun #define WM831X_CHG_ENA_SHIFT 15 /* CHG_ENA */ 75*4882a593Smuzhiyun #define WM831X_CHG_ENA_WIDTH 1 /* CHG_ENA */ 76*4882a593Smuzhiyun #define WM831X_CHG_FRC 0x4000 /* CHG_FRC */ 77*4882a593Smuzhiyun #define WM831X_CHG_FRC_MASK 0x4000 /* CHG_FRC */ 78*4882a593Smuzhiyun #define WM831X_CHG_FRC_SHIFT 14 /* CHG_FRC */ 79*4882a593Smuzhiyun #define WM831X_CHG_FRC_WIDTH 1 /* CHG_FRC */ 80*4882a593Smuzhiyun #define WM831X_CHG_ITERM_MASK 0x1C00 /* CHG_ITERM - [12:10] */ 81*4882a593Smuzhiyun #define WM831X_CHG_ITERM_SHIFT 10 /* CHG_ITERM - [12:10] */ 82*4882a593Smuzhiyun #define WM831X_CHG_ITERM_WIDTH 3 /* CHG_ITERM - [12:10] */ 83*4882a593Smuzhiyun #define WM831X_CHG_FAST 0x0020 /* CHG_FAST */ 84*4882a593Smuzhiyun #define WM831X_CHG_FAST_MASK 0x0020 /* CHG_FAST */ 85*4882a593Smuzhiyun #define WM831X_CHG_FAST_SHIFT 5 /* CHG_FAST */ 86*4882a593Smuzhiyun #define WM831X_CHG_FAST_WIDTH 1 /* CHG_FAST */ 87*4882a593Smuzhiyun #define WM831X_CHG_IMON_ENA 0x0002 /* CHG_IMON_ENA */ 88*4882a593Smuzhiyun #define WM831X_CHG_IMON_ENA_MASK 0x0002 /* CHG_IMON_ENA */ 89*4882a593Smuzhiyun #define WM831X_CHG_IMON_ENA_SHIFT 1 /* CHG_IMON_ENA */ 90*4882a593Smuzhiyun #define WM831X_CHG_IMON_ENA_WIDTH 1 /* CHG_IMON_ENA */ 91*4882a593Smuzhiyun #define WM831X_CHG_CHIP_TEMP_MON 0x0001 /* CHG_CHIP_TEMP_MON */ 92*4882a593Smuzhiyun #define WM831X_CHG_CHIP_TEMP_MON_MASK 0x0001 /* CHG_CHIP_TEMP_MON */ 93*4882a593Smuzhiyun #define WM831X_CHG_CHIP_TEMP_MON_SHIFT 0 /* CHG_CHIP_TEMP_MON */ 94*4882a593Smuzhiyun #define WM831X_CHG_CHIP_TEMP_MON_WIDTH 1 /* CHG_CHIP_TEMP_MON */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * R16457 (0x4049) - Charger Control 2 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun #define WM831X_CHG_OFF_MSK 0x4000 /* CHG_OFF_MSK */ 100*4882a593Smuzhiyun #define WM831X_CHG_OFF_MSK_MASK 0x4000 /* CHG_OFF_MSK */ 101*4882a593Smuzhiyun #define WM831X_CHG_OFF_MSK_SHIFT 14 /* CHG_OFF_MSK */ 102*4882a593Smuzhiyun #define WM831X_CHG_OFF_MSK_WIDTH 1 /* CHG_OFF_MSK */ 103*4882a593Smuzhiyun #define WM831X_CHG_TIME_MASK 0x0F00 /* CHG_TIME - [11:8] */ 104*4882a593Smuzhiyun #define WM831X_CHG_TIME_SHIFT 8 /* CHG_TIME - [11:8] */ 105*4882a593Smuzhiyun #define WM831X_CHG_TIME_WIDTH 4 /* CHG_TIME - [11:8] */ 106*4882a593Smuzhiyun #define WM831X_CHG_TRKL_ILIM_MASK 0x00C0 /* CHG_TRKL_ILIM - [7:6] */ 107*4882a593Smuzhiyun #define WM831X_CHG_TRKL_ILIM_SHIFT 6 /* CHG_TRKL_ILIM - [7:6] */ 108*4882a593Smuzhiyun #define WM831X_CHG_TRKL_ILIM_WIDTH 2 /* CHG_TRKL_ILIM - [7:6] */ 109*4882a593Smuzhiyun #define WM831X_CHG_VSEL_MASK 0x0030 /* CHG_VSEL - [5:4] */ 110*4882a593Smuzhiyun #define WM831X_CHG_VSEL_SHIFT 4 /* CHG_VSEL - [5:4] */ 111*4882a593Smuzhiyun #define WM831X_CHG_VSEL_WIDTH 2 /* CHG_VSEL - [5:4] */ 112*4882a593Smuzhiyun #define WM831X_CHG_FAST_ILIM_MASK 0x000F /* CHG_FAST_ILIM - [3:0] */ 113*4882a593Smuzhiyun #define WM831X_CHG_FAST_ILIM_SHIFT 0 /* CHG_FAST_ILIM - [3:0] */ 114*4882a593Smuzhiyun #define WM831X_CHG_FAST_ILIM_WIDTH 4 /* CHG_FAST_ILIM - [3:0] */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 117*4882a593Smuzhiyun * R16458 (0x404A) - Charger Status 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun #define WM831X_BATT_OV_STS 0x8000 /* BATT_OV_STS */ 120*4882a593Smuzhiyun #define WM831X_BATT_OV_STS_MASK 0x8000 /* BATT_OV_STS */ 121*4882a593Smuzhiyun #define WM831X_BATT_OV_STS_SHIFT 15 /* BATT_OV_STS */ 122*4882a593Smuzhiyun #define WM831X_BATT_OV_STS_WIDTH 1 /* BATT_OV_STS */ 123*4882a593Smuzhiyun #define WM831X_CHG_STATE_MASK 0x7000 /* CHG_STATE - [14:12] */ 124*4882a593Smuzhiyun #define WM831X_CHG_STATE_SHIFT 12 /* CHG_STATE - [14:12] */ 125*4882a593Smuzhiyun #define WM831X_CHG_STATE_WIDTH 3 /* CHG_STATE - [14:12] */ 126*4882a593Smuzhiyun #define WM831X_BATT_HOT_STS 0x0800 /* BATT_HOT_STS */ 127*4882a593Smuzhiyun #define WM831X_BATT_HOT_STS_MASK 0x0800 /* BATT_HOT_STS */ 128*4882a593Smuzhiyun #define WM831X_BATT_HOT_STS_SHIFT 11 /* BATT_HOT_STS */ 129*4882a593Smuzhiyun #define WM831X_BATT_HOT_STS_WIDTH 1 /* BATT_HOT_STS */ 130*4882a593Smuzhiyun #define WM831X_BATT_COLD_STS 0x0400 /* BATT_COLD_STS */ 131*4882a593Smuzhiyun #define WM831X_BATT_COLD_STS_MASK 0x0400 /* BATT_COLD_STS */ 132*4882a593Smuzhiyun #define WM831X_BATT_COLD_STS_SHIFT 10 /* BATT_COLD_STS */ 133*4882a593Smuzhiyun #define WM831X_BATT_COLD_STS_WIDTH 1 /* BATT_COLD_STS */ 134*4882a593Smuzhiyun #define WM831X_CHG_TOPOFF 0x0200 /* CHG_TOPOFF */ 135*4882a593Smuzhiyun #define WM831X_CHG_TOPOFF_MASK 0x0200 /* CHG_TOPOFF */ 136*4882a593Smuzhiyun #define WM831X_CHG_TOPOFF_SHIFT 9 /* CHG_TOPOFF */ 137*4882a593Smuzhiyun #define WM831X_CHG_TOPOFF_WIDTH 1 /* CHG_TOPOFF */ 138*4882a593Smuzhiyun #define WM831X_CHG_ACTIVE 0x0100 /* CHG_ACTIVE */ 139*4882a593Smuzhiyun #define WM831X_CHG_ACTIVE_MASK 0x0100 /* CHG_ACTIVE */ 140*4882a593Smuzhiyun #define WM831X_CHG_ACTIVE_SHIFT 8 /* CHG_ACTIVE */ 141*4882a593Smuzhiyun #define WM831X_CHG_ACTIVE_WIDTH 1 /* CHG_ACTIVE */ 142*4882a593Smuzhiyun #define WM831X_CHG_TIME_ELAPSED_MASK 0x00FF /* CHG_TIME_ELAPSED - [7:0] */ 143*4882a593Smuzhiyun #define WM831X_CHG_TIME_ELAPSED_SHIFT 0 /* CHG_TIME_ELAPSED - [7:0] */ 144*4882a593Smuzhiyun #define WM831X_CHG_TIME_ELAPSED_WIDTH 8 /* CHG_TIME_ELAPSED - [7:0] */ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define WM831X_CHG_STATE_OFF (0 << WM831X_CHG_STATE_SHIFT) 147*4882a593Smuzhiyun #define WM831X_CHG_STATE_TRICKLE (1 << WM831X_CHG_STATE_SHIFT) 148*4882a593Smuzhiyun #define WM831X_CHG_STATE_FAST (2 << WM831X_CHG_STATE_SHIFT) 149*4882a593Smuzhiyun #define WM831X_CHG_STATE_TRICKLE_OT (3 << WM831X_CHG_STATE_SHIFT) 150*4882a593Smuzhiyun #define WM831X_CHG_STATE_FAST_OT (4 << WM831X_CHG_STATE_SHIFT) 151*4882a593Smuzhiyun #define WM831X_CHG_STATE_DEFECTIVE (5 << WM831X_CHG_STATE_SHIFT) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* 154*4882a593Smuzhiyun * R16459 (0x404B) - Backup Charger Control 155*4882a593Smuzhiyun */ 156*4882a593Smuzhiyun #define WM831X_BKUP_CHG_ENA 0x8000 /* BKUP_CHG_ENA */ 157*4882a593Smuzhiyun #define WM831X_BKUP_CHG_ENA_MASK 0x8000 /* BKUP_CHG_ENA */ 158*4882a593Smuzhiyun #define WM831X_BKUP_CHG_ENA_SHIFT 15 /* BKUP_CHG_ENA */ 159*4882a593Smuzhiyun #define WM831X_BKUP_CHG_ENA_WIDTH 1 /* BKUP_CHG_ENA */ 160*4882a593Smuzhiyun #define WM831X_BKUP_CHG_STS 0x4000 /* BKUP_CHG_STS */ 161*4882a593Smuzhiyun #define WM831X_BKUP_CHG_STS_MASK 0x4000 /* BKUP_CHG_STS */ 162*4882a593Smuzhiyun #define WM831X_BKUP_CHG_STS_SHIFT 14 /* BKUP_CHG_STS */ 163*4882a593Smuzhiyun #define WM831X_BKUP_CHG_STS_WIDTH 1 /* BKUP_CHG_STS */ 164*4882a593Smuzhiyun #define WM831X_BKUP_CHG_MODE 0x1000 /* BKUP_CHG_MODE */ 165*4882a593Smuzhiyun #define WM831X_BKUP_CHG_MODE_MASK 0x1000 /* BKUP_CHG_MODE */ 166*4882a593Smuzhiyun #define WM831X_BKUP_CHG_MODE_SHIFT 12 /* BKUP_CHG_MODE */ 167*4882a593Smuzhiyun #define WM831X_BKUP_CHG_MODE_WIDTH 1 /* BKUP_CHG_MODE */ 168*4882a593Smuzhiyun #define WM831X_BKUP_BATT_DET_ENA 0x0800 /* BKUP_BATT_DET_ENA */ 169*4882a593Smuzhiyun #define WM831X_BKUP_BATT_DET_ENA_MASK 0x0800 /* BKUP_BATT_DET_ENA */ 170*4882a593Smuzhiyun #define WM831X_BKUP_BATT_DET_ENA_SHIFT 11 /* BKUP_BATT_DET_ENA */ 171*4882a593Smuzhiyun #define WM831X_BKUP_BATT_DET_ENA_WIDTH 1 /* BKUP_BATT_DET_ENA */ 172*4882a593Smuzhiyun #define WM831X_BKUP_BATT_STS 0x0400 /* BKUP_BATT_STS */ 173*4882a593Smuzhiyun #define WM831X_BKUP_BATT_STS_MASK 0x0400 /* BKUP_BATT_STS */ 174*4882a593Smuzhiyun #define WM831X_BKUP_BATT_STS_SHIFT 10 /* BKUP_BATT_STS */ 175*4882a593Smuzhiyun #define WM831X_BKUP_BATT_STS_WIDTH 1 /* BKUP_BATT_STS */ 176*4882a593Smuzhiyun #define WM831X_BKUP_CHG_VLIM 0x0010 /* BKUP_CHG_VLIM */ 177*4882a593Smuzhiyun #define WM831X_BKUP_CHG_VLIM_MASK 0x0010 /* BKUP_CHG_VLIM */ 178*4882a593Smuzhiyun #define WM831X_BKUP_CHG_VLIM_SHIFT 4 /* BKUP_CHG_VLIM */ 179*4882a593Smuzhiyun #define WM831X_BKUP_CHG_VLIM_WIDTH 1 /* BKUP_CHG_VLIM */ 180*4882a593Smuzhiyun #define WM831X_BKUP_CHG_ILIM_MASK 0x0003 /* BKUP_CHG_ILIM - [1:0] */ 181*4882a593Smuzhiyun #define WM831X_BKUP_CHG_ILIM_SHIFT 0 /* BKUP_CHG_ILIM - [1:0] */ 182*4882a593Smuzhiyun #define WM831X_BKUP_CHG_ILIM_WIDTH 2 /* BKUP_CHG_ILIM - [1:0] */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #endif 185