1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/linux/mfd/wm831x/auxadc.h -- Auxiliary ADC interface for WM831x 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MFD_WM831X_AUXADC_H__ 11*4882a593Smuzhiyun #define __MFD_WM831X_AUXADC_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct wm831x; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * R16429 (0x402D) - AuxADC Data 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */ 19*4882a593Smuzhiyun #define WM831X_AUX_DATA_SRC_SHIFT 12 /* AUX_DATA_SRC - [15:12] */ 20*4882a593Smuzhiyun #define WM831X_AUX_DATA_SRC_WIDTH 4 /* AUX_DATA_SRC - [15:12] */ 21*4882a593Smuzhiyun #define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */ 22*4882a593Smuzhiyun #define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */ 23*4882a593Smuzhiyun #define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * R16430 (0x402E) - AuxADC Control 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define WM831X_AUX_ENA 0x8000 /* AUX_ENA */ 29*4882a593Smuzhiyun #define WM831X_AUX_ENA_MASK 0x8000 /* AUX_ENA */ 30*4882a593Smuzhiyun #define WM831X_AUX_ENA_SHIFT 15 /* AUX_ENA */ 31*4882a593Smuzhiyun #define WM831X_AUX_ENA_WIDTH 1 /* AUX_ENA */ 32*4882a593Smuzhiyun #define WM831X_AUX_CVT_ENA 0x4000 /* AUX_CVT_ENA */ 33*4882a593Smuzhiyun #define WM831X_AUX_CVT_ENA_MASK 0x4000 /* AUX_CVT_ENA */ 34*4882a593Smuzhiyun #define WM831X_AUX_CVT_ENA_SHIFT 14 /* AUX_CVT_ENA */ 35*4882a593Smuzhiyun #define WM831X_AUX_CVT_ENA_WIDTH 1 /* AUX_CVT_ENA */ 36*4882a593Smuzhiyun #define WM831X_AUX_SLPENA 0x1000 /* AUX_SLPENA */ 37*4882a593Smuzhiyun #define WM831X_AUX_SLPENA_MASK 0x1000 /* AUX_SLPENA */ 38*4882a593Smuzhiyun #define WM831X_AUX_SLPENA_SHIFT 12 /* AUX_SLPENA */ 39*4882a593Smuzhiyun #define WM831X_AUX_SLPENA_WIDTH 1 /* AUX_SLPENA */ 40*4882a593Smuzhiyun #define WM831X_AUX_FRC_ENA 0x0800 /* AUX_FRC_ENA */ 41*4882a593Smuzhiyun #define WM831X_AUX_FRC_ENA_MASK 0x0800 /* AUX_FRC_ENA */ 42*4882a593Smuzhiyun #define WM831X_AUX_FRC_ENA_SHIFT 11 /* AUX_FRC_ENA */ 43*4882a593Smuzhiyun #define WM831X_AUX_FRC_ENA_WIDTH 1 /* AUX_FRC_ENA */ 44*4882a593Smuzhiyun #define WM831X_AUX_RATE_MASK 0x003F /* AUX_RATE - [5:0] */ 45*4882a593Smuzhiyun #define WM831X_AUX_RATE_SHIFT 0 /* AUX_RATE - [5:0] */ 46*4882a593Smuzhiyun #define WM831X_AUX_RATE_WIDTH 6 /* AUX_RATE - [5:0] */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * R16431 (0x402F) - AuxADC Source 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define WM831X_AUX_CAL_SEL 0x8000 /* AUX_CAL_SEL */ 52*4882a593Smuzhiyun #define WM831X_AUX_CAL_SEL_MASK 0x8000 /* AUX_CAL_SEL */ 53*4882a593Smuzhiyun #define WM831X_AUX_CAL_SEL_SHIFT 15 /* AUX_CAL_SEL */ 54*4882a593Smuzhiyun #define WM831X_AUX_CAL_SEL_WIDTH 1 /* AUX_CAL_SEL */ 55*4882a593Smuzhiyun #define WM831X_AUX_BKUP_BATT_SEL 0x0400 /* AUX_BKUP_BATT_SEL */ 56*4882a593Smuzhiyun #define WM831X_AUX_BKUP_BATT_SEL_MASK 0x0400 /* AUX_BKUP_BATT_SEL */ 57*4882a593Smuzhiyun #define WM831X_AUX_BKUP_BATT_SEL_SHIFT 10 /* AUX_BKUP_BATT_SEL */ 58*4882a593Smuzhiyun #define WM831X_AUX_BKUP_BATT_SEL_WIDTH 1 /* AUX_BKUP_BATT_SEL */ 59*4882a593Smuzhiyun #define WM831X_AUX_WALL_SEL 0x0200 /* AUX_WALL_SEL */ 60*4882a593Smuzhiyun #define WM831X_AUX_WALL_SEL_MASK 0x0200 /* AUX_WALL_SEL */ 61*4882a593Smuzhiyun #define WM831X_AUX_WALL_SEL_SHIFT 9 /* AUX_WALL_SEL */ 62*4882a593Smuzhiyun #define WM831X_AUX_WALL_SEL_WIDTH 1 /* AUX_WALL_SEL */ 63*4882a593Smuzhiyun #define WM831X_AUX_BATT_SEL 0x0100 /* AUX_BATT_SEL */ 64*4882a593Smuzhiyun #define WM831X_AUX_BATT_SEL_MASK 0x0100 /* AUX_BATT_SEL */ 65*4882a593Smuzhiyun #define WM831X_AUX_BATT_SEL_SHIFT 8 /* AUX_BATT_SEL */ 66*4882a593Smuzhiyun #define WM831X_AUX_BATT_SEL_WIDTH 1 /* AUX_BATT_SEL */ 67*4882a593Smuzhiyun #define WM831X_AUX_USB_SEL 0x0080 /* AUX_USB_SEL */ 68*4882a593Smuzhiyun #define WM831X_AUX_USB_SEL_MASK 0x0080 /* AUX_USB_SEL */ 69*4882a593Smuzhiyun #define WM831X_AUX_USB_SEL_SHIFT 7 /* AUX_USB_SEL */ 70*4882a593Smuzhiyun #define WM831X_AUX_USB_SEL_WIDTH 1 /* AUX_USB_SEL */ 71*4882a593Smuzhiyun #define WM831X_AUX_SYSVDD_SEL 0x0040 /* AUX_SYSVDD_SEL */ 72*4882a593Smuzhiyun #define WM831X_AUX_SYSVDD_SEL_MASK 0x0040 /* AUX_SYSVDD_SEL */ 73*4882a593Smuzhiyun #define WM831X_AUX_SYSVDD_SEL_SHIFT 6 /* AUX_SYSVDD_SEL */ 74*4882a593Smuzhiyun #define WM831X_AUX_SYSVDD_SEL_WIDTH 1 /* AUX_SYSVDD_SEL */ 75*4882a593Smuzhiyun #define WM831X_AUX_BATT_TEMP_SEL 0x0020 /* AUX_BATT_TEMP_SEL */ 76*4882a593Smuzhiyun #define WM831X_AUX_BATT_TEMP_SEL_MASK 0x0020 /* AUX_BATT_TEMP_SEL */ 77*4882a593Smuzhiyun #define WM831X_AUX_BATT_TEMP_SEL_SHIFT 5 /* AUX_BATT_TEMP_SEL */ 78*4882a593Smuzhiyun #define WM831X_AUX_BATT_TEMP_SEL_WIDTH 1 /* AUX_BATT_TEMP_SEL */ 79*4882a593Smuzhiyun #define WM831X_AUX_CHIP_TEMP_SEL 0x0010 /* AUX_CHIP_TEMP_SEL */ 80*4882a593Smuzhiyun #define WM831X_AUX_CHIP_TEMP_SEL_MASK 0x0010 /* AUX_CHIP_TEMP_SEL */ 81*4882a593Smuzhiyun #define WM831X_AUX_CHIP_TEMP_SEL_SHIFT 4 /* AUX_CHIP_TEMP_SEL */ 82*4882a593Smuzhiyun #define WM831X_AUX_CHIP_TEMP_SEL_WIDTH 1 /* AUX_CHIP_TEMP_SEL */ 83*4882a593Smuzhiyun #define WM831X_AUX_AUX4_SEL 0x0008 /* AUX_AUX4_SEL */ 84*4882a593Smuzhiyun #define WM831X_AUX_AUX4_SEL_MASK 0x0008 /* AUX_AUX4_SEL */ 85*4882a593Smuzhiyun #define WM831X_AUX_AUX4_SEL_SHIFT 3 /* AUX_AUX4_SEL */ 86*4882a593Smuzhiyun #define WM831X_AUX_AUX4_SEL_WIDTH 1 /* AUX_AUX4_SEL */ 87*4882a593Smuzhiyun #define WM831X_AUX_AUX3_SEL 0x0004 /* AUX_AUX3_SEL */ 88*4882a593Smuzhiyun #define WM831X_AUX_AUX3_SEL_MASK 0x0004 /* AUX_AUX3_SEL */ 89*4882a593Smuzhiyun #define WM831X_AUX_AUX3_SEL_SHIFT 2 /* AUX_AUX3_SEL */ 90*4882a593Smuzhiyun #define WM831X_AUX_AUX3_SEL_WIDTH 1 /* AUX_AUX3_SEL */ 91*4882a593Smuzhiyun #define WM831X_AUX_AUX2_SEL 0x0002 /* AUX_AUX2_SEL */ 92*4882a593Smuzhiyun #define WM831X_AUX_AUX2_SEL_MASK 0x0002 /* AUX_AUX2_SEL */ 93*4882a593Smuzhiyun #define WM831X_AUX_AUX2_SEL_SHIFT 1 /* AUX_AUX2_SEL */ 94*4882a593Smuzhiyun #define WM831X_AUX_AUX2_SEL_WIDTH 1 /* AUX_AUX2_SEL */ 95*4882a593Smuzhiyun #define WM831X_AUX_AUX1_SEL 0x0001 /* AUX_AUX1_SEL */ 96*4882a593Smuzhiyun #define WM831X_AUX_AUX1_SEL_MASK 0x0001 /* AUX_AUX1_SEL */ 97*4882a593Smuzhiyun #define WM831X_AUX_AUX1_SEL_SHIFT 0 /* AUX_AUX1_SEL */ 98*4882a593Smuzhiyun #define WM831X_AUX_AUX1_SEL_WIDTH 1 /* AUX_AUX1_SEL */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * R16432 (0x4030) - Comparator Control 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun #define WM831X_DCOMP4_STS 0x0800 /* DCOMP4_STS */ 104*4882a593Smuzhiyun #define WM831X_DCOMP4_STS_MASK 0x0800 /* DCOMP4_STS */ 105*4882a593Smuzhiyun #define WM831X_DCOMP4_STS_SHIFT 11 /* DCOMP4_STS */ 106*4882a593Smuzhiyun #define WM831X_DCOMP4_STS_WIDTH 1 /* DCOMP4_STS */ 107*4882a593Smuzhiyun #define WM831X_DCOMP3_STS 0x0400 /* DCOMP3_STS */ 108*4882a593Smuzhiyun #define WM831X_DCOMP3_STS_MASK 0x0400 /* DCOMP3_STS */ 109*4882a593Smuzhiyun #define WM831X_DCOMP3_STS_SHIFT 10 /* DCOMP3_STS */ 110*4882a593Smuzhiyun #define WM831X_DCOMP3_STS_WIDTH 1 /* DCOMP3_STS */ 111*4882a593Smuzhiyun #define WM831X_DCOMP2_STS 0x0200 /* DCOMP2_STS */ 112*4882a593Smuzhiyun #define WM831X_DCOMP2_STS_MASK 0x0200 /* DCOMP2_STS */ 113*4882a593Smuzhiyun #define WM831X_DCOMP2_STS_SHIFT 9 /* DCOMP2_STS */ 114*4882a593Smuzhiyun #define WM831X_DCOMP2_STS_WIDTH 1 /* DCOMP2_STS */ 115*4882a593Smuzhiyun #define WM831X_DCOMP1_STS 0x0100 /* DCOMP1_STS */ 116*4882a593Smuzhiyun #define WM831X_DCOMP1_STS_MASK 0x0100 /* DCOMP1_STS */ 117*4882a593Smuzhiyun #define WM831X_DCOMP1_STS_SHIFT 8 /* DCOMP1_STS */ 118*4882a593Smuzhiyun #define WM831X_DCOMP1_STS_WIDTH 1 /* DCOMP1_STS */ 119*4882a593Smuzhiyun #define WM831X_DCMP4_ENA 0x0008 /* DCMP4_ENA */ 120*4882a593Smuzhiyun #define WM831X_DCMP4_ENA_MASK 0x0008 /* DCMP4_ENA */ 121*4882a593Smuzhiyun #define WM831X_DCMP4_ENA_SHIFT 3 /* DCMP4_ENA */ 122*4882a593Smuzhiyun #define WM831X_DCMP4_ENA_WIDTH 1 /* DCMP4_ENA */ 123*4882a593Smuzhiyun #define WM831X_DCMP3_ENA 0x0004 /* DCMP3_ENA */ 124*4882a593Smuzhiyun #define WM831X_DCMP3_ENA_MASK 0x0004 /* DCMP3_ENA */ 125*4882a593Smuzhiyun #define WM831X_DCMP3_ENA_SHIFT 2 /* DCMP3_ENA */ 126*4882a593Smuzhiyun #define WM831X_DCMP3_ENA_WIDTH 1 /* DCMP3_ENA */ 127*4882a593Smuzhiyun #define WM831X_DCMP2_ENA 0x0002 /* DCMP2_ENA */ 128*4882a593Smuzhiyun #define WM831X_DCMP2_ENA_MASK 0x0002 /* DCMP2_ENA */ 129*4882a593Smuzhiyun #define WM831X_DCMP2_ENA_SHIFT 1 /* DCMP2_ENA */ 130*4882a593Smuzhiyun #define WM831X_DCMP2_ENA_WIDTH 1 /* DCMP2_ENA */ 131*4882a593Smuzhiyun #define WM831X_DCMP1_ENA 0x0001 /* DCMP1_ENA */ 132*4882a593Smuzhiyun #define WM831X_DCMP1_ENA_MASK 0x0001 /* DCMP1_ENA */ 133*4882a593Smuzhiyun #define WM831X_DCMP1_ENA_SHIFT 0 /* DCMP1_ENA */ 134*4882a593Smuzhiyun #define WM831X_DCMP1_ENA_WIDTH 1 /* DCMP1_ENA */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * R16433 (0x4031) - Comparator 1 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define WM831X_DCMP1_SRC_MASK 0xE000 /* DCMP1_SRC - [15:13] */ 140*4882a593Smuzhiyun #define WM831X_DCMP1_SRC_SHIFT 13 /* DCMP1_SRC - [15:13] */ 141*4882a593Smuzhiyun #define WM831X_DCMP1_SRC_WIDTH 3 /* DCMP1_SRC - [15:13] */ 142*4882a593Smuzhiyun #define WM831X_DCMP1_GT 0x1000 /* DCMP1_GT */ 143*4882a593Smuzhiyun #define WM831X_DCMP1_GT_MASK 0x1000 /* DCMP1_GT */ 144*4882a593Smuzhiyun #define WM831X_DCMP1_GT_SHIFT 12 /* DCMP1_GT */ 145*4882a593Smuzhiyun #define WM831X_DCMP1_GT_WIDTH 1 /* DCMP1_GT */ 146*4882a593Smuzhiyun #define WM831X_DCMP1_THR_MASK 0x0FFF /* DCMP1_THR - [11:0] */ 147*4882a593Smuzhiyun #define WM831X_DCMP1_THR_SHIFT 0 /* DCMP1_THR - [11:0] */ 148*4882a593Smuzhiyun #define WM831X_DCMP1_THR_WIDTH 12 /* DCMP1_THR - [11:0] */ 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* 151*4882a593Smuzhiyun * R16434 (0x4032) - Comparator 2 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun #define WM831X_DCMP2_SRC_MASK 0xE000 /* DCMP2_SRC - [15:13] */ 154*4882a593Smuzhiyun #define WM831X_DCMP2_SRC_SHIFT 13 /* DCMP2_SRC - [15:13] */ 155*4882a593Smuzhiyun #define WM831X_DCMP2_SRC_WIDTH 3 /* DCMP2_SRC - [15:13] */ 156*4882a593Smuzhiyun #define WM831X_DCMP2_GT 0x1000 /* DCMP2_GT */ 157*4882a593Smuzhiyun #define WM831X_DCMP2_GT_MASK 0x1000 /* DCMP2_GT */ 158*4882a593Smuzhiyun #define WM831X_DCMP2_GT_SHIFT 12 /* DCMP2_GT */ 159*4882a593Smuzhiyun #define WM831X_DCMP2_GT_WIDTH 1 /* DCMP2_GT */ 160*4882a593Smuzhiyun #define WM831X_DCMP2_THR_MASK 0x0FFF /* DCMP2_THR - [11:0] */ 161*4882a593Smuzhiyun #define WM831X_DCMP2_THR_SHIFT 0 /* DCMP2_THR - [11:0] */ 162*4882a593Smuzhiyun #define WM831X_DCMP2_THR_WIDTH 12 /* DCMP2_THR - [11:0] */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* 165*4882a593Smuzhiyun * R16435 (0x4033) - Comparator 3 166*4882a593Smuzhiyun */ 167*4882a593Smuzhiyun #define WM831X_DCMP3_SRC_MASK 0xE000 /* DCMP3_SRC - [15:13] */ 168*4882a593Smuzhiyun #define WM831X_DCMP3_SRC_SHIFT 13 /* DCMP3_SRC - [15:13] */ 169*4882a593Smuzhiyun #define WM831X_DCMP3_SRC_WIDTH 3 /* DCMP3_SRC - [15:13] */ 170*4882a593Smuzhiyun #define WM831X_DCMP3_GT 0x1000 /* DCMP3_GT */ 171*4882a593Smuzhiyun #define WM831X_DCMP3_GT_MASK 0x1000 /* DCMP3_GT */ 172*4882a593Smuzhiyun #define WM831X_DCMP3_GT_SHIFT 12 /* DCMP3_GT */ 173*4882a593Smuzhiyun #define WM831X_DCMP3_GT_WIDTH 1 /* DCMP3_GT */ 174*4882a593Smuzhiyun #define WM831X_DCMP3_THR_MASK 0x0FFF /* DCMP3_THR - [11:0] */ 175*4882a593Smuzhiyun #define WM831X_DCMP3_THR_SHIFT 0 /* DCMP3_THR - [11:0] */ 176*4882a593Smuzhiyun #define WM831X_DCMP3_THR_WIDTH 12 /* DCMP3_THR - [11:0] */ 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* 179*4882a593Smuzhiyun * R16436 (0x4034) - Comparator 4 180*4882a593Smuzhiyun */ 181*4882a593Smuzhiyun #define WM831X_DCMP4_SRC_MASK 0xE000 /* DCMP4_SRC - [15:13] */ 182*4882a593Smuzhiyun #define WM831X_DCMP4_SRC_SHIFT 13 /* DCMP4_SRC - [15:13] */ 183*4882a593Smuzhiyun #define WM831X_DCMP4_SRC_WIDTH 3 /* DCMP4_SRC - [15:13] */ 184*4882a593Smuzhiyun #define WM831X_DCMP4_GT 0x1000 /* DCMP4_GT */ 185*4882a593Smuzhiyun #define WM831X_DCMP4_GT_MASK 0x1000 /* DCMP4_GT */ 186*4882a593Smuzhiyun #define WM831X_DCMP4_GT_SHIFT 12 /* DCMP4_GT */ 187*4882a593Smuzhiyun #define WM831X_DCMP4_GT_WIDTH 1 /* DCMP4_GT */ 188*4882a593Smuzhiyun #define WM831X_DCMP4_THR_MASK 0x0FFF /* DCMP4_THR - [11:0] */ 189*4882a593Smuzhiyun #define WM831X_DCMP4_THR_SHIFT 0 /* DCMP4_THR - [11:0] */ 190*4882a593Smuzhiyun #define WM831X_DCMP4_THR_WIDTH 12 /* DCMP4_THR - [11:0] */ 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define WM831X_AUX_CAL_FACTOR 0xfff 193*4882a593Smuzhiyun #define WM831X_AUX_CAL_NOMINAL 0x222 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun enum wm831x_auxadc { 196*4882a593Smuzhiyun WM831X_AUX_CAL = 15, 197*4882a593Smuzhiyun WM831X_AUX_BKUP_BATT = 10, 198*4882a593Smuzhiyun WM831X_AUX_WALL = 9, 199*4882a593Smuzhiyun WM831X_AUX_BATT = 8, 200*4882a593Smuzhiyun WM831X_AUX_USB = 7, 201*4882a593Smuzhiyun WM831X_AUX_SYSVDD = 6, 202*4882a593Smuzhiyun WM831X_AUX_BATT_TEMP = 5, 203*4882a593Smuzhiyun WM831X_AUX_CHIP_TEMP = 4, 204*4882a593Smuzhiyun WM831X_AUX_AUX4 = 3, 205*4882a593Smuzhiyun WM831X_AUX_AUX3 = 2, 206*4882a593Smuzhiyun WM831X_AUX_AUX2 = 1, 207*4882a593Smuzhiyun WM831X_AUX_AUX1 = 0, 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input); 211*4882a593Smuzhiyun int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input); 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #endif 214