1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef _WCD934X_REGISTERS_H 4*4882a593Smuzhiyun #define _WCD934X_REGISTERS_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_CLK_GATE 0x0002 7*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_CLK_GATE_MASK GENMASK(1, 0) 8*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_CLK_MCLK_CFG 0x0003 9*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0) 10*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(1) 11*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0) 12*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_RST_CTL 0x0009 13*4882a593Smuzhiyun #define WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL 0x0011 14*4882a593Smuzhiyun #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0 0x0021 15*4882a593Smuzhiyun #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2 0x0023 16*4882a593Smuzhiyun #define WCD934X_CHIP_TIER_CTRL_EFUSE_CTL 0x0025 17*4882a593Smuzhiyun #define WCD934X_EFUSE_SENSE_STATE_MASK GENMASK(4, 1) 18*4882a593Smuzhiyun #define WCD934X_EFUSE_SENSE_STATE_DEF 0x10 19*4882a593Smuzhiyun #define WCD934X_EFUSE_SENSE_EN_MASK BIT(0) 20*4882a593Smuzhiyun #define WCD934X_EFUSE_SENSE_ENABLE BIT(0) 21*4882a593Smuzhiyun #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14 0x0037 22*4882a593Smuzhiyun #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15 0x0038 23*4882a593Smuzhiyun #define WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS 0x0039 24*4882a593Smuzhiyun #define WCD934X_DATA_HUB_SB_TX10_INP_CFG 0x006b 25*4882a593Smuzhiyun #define WCD934X_DATA_HUB_SB_TX11_INP_CFG 0x006c 26*4882a593Smuzhiyun #define WCD934X_DATA_HUB_SB_TX13_INP_CFG 0x006e 27*4882a593Smuzhiyun #define WCD934X_CPE_FLL_CONFIG_CTL_2 0x0111 28*4882a593Smuzhiyun #define WCD934X_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD 0x0213 29*4882a593Smuzhiyun #define WCD934X_CPE_SS_SVA_CFG 0x0214 30*4882a593Smuzhiyun #define WCD934X_CPE_SS_DMIC0_CTL 0x0218 31*4882a593Smuzhiyun #define WCD934X_CPE_SS_DMIC1_CTL 0x0219 32*4882a593Smuzhiyun #define WCD934X_DMIC_RATE_MASK GENMASK(3, 1) 33*4882a593Smuzhiyun #define WCD934X_CPE_SS_DMIC2_CTL 0x021a 34*4882a593Smuzhiyun #define WCD934X_CPE_SS_DMIC_CFG 0x021b 35*4882a593Smuzhiyun #define WCD934X_CPE_SS_DMIC_CFG 0x021b 36*4882a593Smuzhiyun #define WCD934X_CPE_SS_CPAR_CFG 0x021c 37*4882a593Smuzhiyun #define WCD934X_INTR_PIN1_MASK0 0x0409 38*4882a593Smuzhiyun #define WCD934X_INTR_PIN1_STATUS0 0x0411 39*4882a593Smuzhiyun #define WCD934X_INTR_PIN1_CLEAR0 0x0419 40*4882a593Smuzhiyun #define WCD934X_INTR_PIN2_CLEAR3 0x0434 41*4882a593Smuzhiyun #define WCD934X_INTR_LEVEL0 0x0461 42*4882a593Smuzhiyun /* INTR_REG 0 */ 43*4882a593Smuzhiyun #define WCD934X_IRQ_SLIMBUS 0 44*4882a593Smuzhiyun #define WCD934X_IRQ_MISC 1 45*4882a593Smuzhiyun #define WCD934X_IRQ_HPH_PA_OCPL_FAULT 2 46*4882a593Smuzhiyun #define WCD934X_IRQ_HPH_PA_OCPR_FAULT 3 47*4882a593Smuzhiyun #define WCD934X_IRQ_EAR_PA_OCP_FAULT 4 48*4882a593Smuzhiyun #define WCD934X_IRQ_HPH_PA_CNPL_COMPLETE 5 49*4882a593Smuzhiyun #define WCD934X_IRQ_HPH_PA_CNPR_COMPLETE 6 50*4882a593Smuzhiyun #define WCD934X_IRQ_EAR_PA_CNP_COMPLETE 7 51*4882a593Smuzhiyun /* INTR_REG 1 */ 52*4882a593Smuzhiyun #define WCD934X_IRQ_MBHC_SW_DET 8 53*4882a593Smuzhiyun #define WCD934X_IRQ_MBHC_ELECT_INS_REM_DET 9 54*4882a593Smuzhiyun #define WCD934X_IRQ_MBHC_BUTTON_PRESS_DET 10 55*4882a593Smuzhiyun #define WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET 11 56*4882a593Smuzhiyun #define WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET 12 57*4882a593Smuzhiyun #define WCD934X_IRQ_RESERVED_0 13 58*4882a593Smuzhiyun #define WCD934X_IRQ_RESERVED_1 14 59*4882a593Smuzhiyun #define WCD934X_IRQ_RESERVED_2 15 60*4882a593Smuzhiyun /* INTR_REG 2 */ 61*4882a593Smuzhiyun #define WCD934X_IRQ_LINE_PA1_CNP_COMPLETE 16 62*4882a593Smuzhiyun #define WCD934X_IRQ_LINE_PA2_CNP_COMPLETE 17 63*4882a593Smuzhiyun #define WCD934X_IRQ_SLNQ_ANALOG_ERROR 18 64*4882a593Smuzhiyun #define WCD934X_IRQ_RESERVED_3 19 65*4882a593Smuzhiyun #define WCD934X_IRQ_SOUNDWIRE 20 66*4882a593Smuzhiyun #define WCD934X_IRQ_VDD_DIG_RAMP_COMPLETE 21 67*4882a593Smuzhiyun #define WCD934X_IRQ_RCO_ERROR 22 68*4882a593Smuzhiyun #define WCD934X_IRQ_CPE_ERROR 23 69*4882a593Smuzhiyun /* INTR_REG 3 */ 70*4882a593Smuzhiyun #define WCD934X_IRQ_MAD_AUDIO 24 71*4882a593Smuzhiyun #define WCD934X_IRQ_MAD_BEACON 25 72*4882a593Smuzhiyun #define WCD934X_IRQ_MAD_ULTRASOUND 26 73*4882a593Smuzhiyun #define WCD934X_IRQ_VBAT_ATTACK 27 74*4882a593Smuzhiyun #define WCD934X_IRQ_VBAT_RESTORE 28 75*4882a593Smuzhiyun #define WCD934X_IRQ_CPE1_INTR 29 76*4882a593Smuzhiyun #define WCD934X_IRQ_RESERVED_4 30 77*4882a593Smuzhiyun #define WCD934X_IRQ_SLNQ_DIGITAL 31 78*4882a593Smuzhiyun #define WCD934X_NUM_IRQS 32 79*4882a593Smuzhiyun #define WCD934X_ANA_BIAS 0x0601 80*4882a593Smuzhiyun #define WCD934X_ANA_BIAS_EN_MASK BIT(7) 81*4882a593Smuzhiyun #define WCD934X_ANA_BIAS_EN BIT(7) 82*4882a593Smuzhiyun #define WCD934X_ANA_PRECHRG_EN_MASK BIT(6) 83*4882a593Smuzhiyun #define WCD934X_ANA_PRECHRG_EN BIT(6) 84*4882a593Smuzhiyun #define WCD934X_ANA_PRECHRG_MODE_MASK BIT(5) 85*4882a593Smuzhiyun #define WCD934X_ANA_PRECHRG_MODE_AUTO BIT(5) 86*4882a593Smuzhiyun #define WCD934X_ANA_RCO 0x0603 87*4882a593Smuzhiyun #define WCD934X_ANA_RCO_BG_EN_MASK BIT(7) 88*4882a593Smuzhiyun #define WCD934X_ANA_RCO_BG_ENABLE BIT(7) 89*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_CTL 0x0606 90*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK GENMASK(1, 0) 91*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_PRE_EN2_MASK BIT(0) 92*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_PRE_EN2_ENABLE BIT(0) 93*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_PRE_EN1_MASK BIT(1) 94*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_PRE_EN1_ENABLE BIT(1) 95*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_HI_ACCU_EN_MASK BIT(2) 96*4882a593Smuzhiyun #define WCD934X_ANA_BUCK_HI_ACCU_ENABLE BIT(2) 97*4882a593Smuzhiyun #define WCD934X_ANA_RX_SUPPLIES 0x0608 98*4882a593Smuzhiyun #define WCD934X_ANA_HPH 0x0609 99*4882a593Smuzhiyun #define WCD934X_ANA_EAR 0x060a 100*4882a593Smuzhiyun #define WCD934X_ANA_LO_1_2 0x060b 101*4882a593Smuzhiyun #define WCD934X_ANA_AMIC1 0x060e 102*4882a593Smuzhiyun #define WCD934X_ANA_AMIC2 0x060f 103*4882a593Smuzhiyun #define WCD934X_ANA_AMIC3 0x0610 104*4882a593Smuzhiyun #define WCD934X_ANA_AMIC4 0x0611 105*4882a593Smuzhiyun #define WCD934X_ANA_MBHC_MECH 0x0614 106*4882a593Smuzhiyun #define WCD934X_ANA_MBHC_ELECT 0x0615 107*4882a593Smuzhiyun #define WCD934X_ANA_MBHC_ZDET 0x0616 108*4882a593Smuzhiyun #define WCD934X_ANA_MBHC_RESULT_1 0x0617 109*4882a593Smuzhiyun #define WCD934X_ANA_MBHC_RESULT_2 0x0618 110*4882a593Smuzhiyun #define WCD934X_ANA_MBHC_RESULT_3 0x0619 111*4882a593Smuzhiyun #define WCD934X_ANA_MICB1 0x0622 112*4882a593Smuzhiyun #define WCD934X_MICB_VAL_MASK GENMASK(5, 0) 113*4882a593Smuzhiyun #define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6) 114*4882a593Smuzhiyun #define WCD934X_ANA_MICB_PULL_UP 0x80 115*4882a593Smuzhiyun #define WCD934X_ANA_MICB_ENABLE 0x40 116*4882a593Smuzhiyun #define WCD934X_ANA_MICB_DISABLE 0x0 117*4882a593Smuzhiyun #define WCD934X_ANA_MICB2 0x0623 118*4882a593Smuzhiyun #define WCD934X_ANA_MICB3 0x0625 119*4882a593Smuzhiyun #define WCD934X_ANA_MICB4 0x0626 120*4882a593Smuzhiyun #define WCD934X_BIAS_VBG_FINE_ADJ 0x0629 121*4882a593Smuzhiyun #define WCD934X_MICB1_TEST_CTL_1 0x066b 122*4882a593Smuzhiyun #define WCD934X_MICB1_TEST_CTL_2 0x066c 123*4882a593Smuzhiyun #define WCD934X_MICB2_TEST_CTL_1 0x066e 124*4882a593Smuzhiyun #define WCD934X_MICB3_TEST_CTL_1 0x0671 125*4882a593Smuzhiyun #define WCD934X_MICB4_TEST_CTL_1 0x0674 126*4882a593Smuzhiyun #define WCD934X_CLASSH_MODE_1 0x0697 127*4882a593Smuzhiyun #define WCD934X_CLASSH_MODE_2 0x0698 128*4882a593Smuzhiyun #define WCD934X_CLASSH_MODE_3 0x0699 129*4882a593Smuzhiyun #define WCD934X_CLASSH_CTRL_VCL_1 0x069a 130*4882a593Smuzhiyun #define WCD934X_CLASSH_CTRL_VCL_2 0x069b 131*4882a593Smuzhiyun #define WCD934X_CLASSH_CTRL_CCL_1 0x069c 132*4882a593Smuzhiyun #define WCD934X_CLASSH_CTRL_CCL_2 0x069d 133*4882a593Smuzhiyun #define WCD934X_CLASSH_CTRL_CCL_3 0x069e 134*4882a593Smuzhiyun #define WCD934X_CLASSH_CTRL_CCL_4 0x069f 135*4882a593Smuzhiyun #define WCD934X_CLASSH_CTRL_CCL_5 0x06a0 136*4882a593Smuzhiyun #define WCD934X_CLASSH_BUCK_TMUX_A_D 0x06a1 137*4882a593Smuzhiyun #define WCD934X_CLASSH_BUCK_SW_DRV_CNTL 0x06a2 138*4882a593Smuzhiyun #define WCD934X_RX_OCP_CTL 0x06b6 139*4882a593Smuzhiyun #define WCD934X_RX_OCP_COUNT 0x06b7 140*4882a593Smuzhiyun #define WCD934X_HPH_CNP_EN 0x06cb 141*4882a593Smuzhiyun #define WCD934X_HPH_CNP_WG_CTL 0x06cc 142*4882a593Smuzhiyun #define WCD934X_HPH_GM3_BOOST_EN_MASK BIT(7) 143*4882a593Smuzhiyun #define WCD934X_HPH_GM3_BOOST_ENABLE BIT(7) 144*4882a593Smuzhiyun #define WCD934X_HPH_OCP_CTL 0x06ce 145*4882a593Smuzhiyun #define WCD934X_HPH_L_EN 0x06d3 146*4882a593Smuzhiyun #define WCD934X_HPH_GAIN_SRC_SEL_MASK BIT(5) 147*4882a593Smuzhiyun #define WCD934X_HPH_GAIN_SRC_SEL_COMPANDER 0 148*4882a593Smuzhiyun #define WCD934X_HPH_GAIN_SRC_SEL_REGISTER BIT(5) 149*4882a593Smuzhiyun #define WCD934X_HPH_L_TEST 0x06d4 150*4882a593Smuzhiyun #define WCD934X_HPH_R_EN 0x06d6 151*4882a593Smuzhiyun #define WCD934X_HPH_R_TEST 0x06d7 152*4882a593Smuzhiyun #define WCD934X_HPH_OCP_DET_MASK BIT(0) 153*4882a593Smuzhiyun #define WCD934X_HPH_OCP_DET_ENABLE BIT(0) 154*4882a593Smuzhiyun #define WCD934X_HPH_OCP_DET_DISABLE 0 155*4882a593Smuzhiyun #define WCD934X_DIFF_LO_LO2_COMPANDER 0x06ea 156*4882a593Smuzhiyun #define WCD934X_DIFF_LO_LO1_COMPANDER 0x06eb 157*4882a593Smuzhiyun #define WCD934X_CLK_SYS_MCLK_PRG 0x0711 158*4882a593Smuzhiyun #define WCD934X_EXT_CLK_BUF_EN_MASK BIT(7) 159*4882a593Smuzhiyun #define WCD934X_EXT_CLK_BUF_EN BIT(7) 160*4882a593Smuzhiyun #define WCD934X_EXT_CLK_DIV_RATIO_MASK GENMASK(5, 4) 161*4882a593Smuzhiyun #define WCD934X_EXT_CLK_DIV_BY_2 0x10 162*4882a593Smuzhiyun #define WCD934X_MCLK_SRC_MASK BIT(1) 163*4882a593Smuzhiyun #define WCD934X_MCLK_SRC_EXT_CLK 0 164*4882a593Smuzhiyun #define WCD934X_MCLK_SRC_MASK BIT(1) 165*4882a593Smuzhiyun #define WCD934X_MCLK_EN_MASK BIT(0) 166*4882a593Smuzhiyun #define WCD934X_MCLK_EN BIT(0) 167*4882a593Smuzhiyun #define WCD934X_CLK_SYS_MCLK2_PRG1 0x0712 168*4882a593Smuzhiyun #define WCD934X_CLK_SYS_MCLK2_PRG2 0x0713 169*4882a593Smuzhiyun #define WCD934X_SIDO_NEW_VOUT_A_STARTUP 0x071b 170*4882a593Smuzhiyun #define WCD934X_SIDO_NEW_VOUT_D_STARTUP 0x071c 171*4882a593Smuzhiyun #define WCD934X_SIDO_NEW_VOUT_D_FREQ1 0x071d 172*4882a593Smuzhiyun #define WCD934X_SIDO_NEW_VOUT_D_FREQ2 0x071e 173*4882a593Smuzhiyun #define WCD934X_SIDO_RIPPLE_FREQ_EN_MASK BIT(0) 174*4882a593Smuzhiyun #define WCD934X_SIDO_RIPPLE_FREQ_ENABLE BIT(0) 175*4882a593Smuzhiyun #define WCD934X_MBHC_NEW_CTL_2 0x0721 176*4882a593Smuzhiyun #define WCD934X_TX_NEW_AMIC_4_5_SEL 0x0727 177*4882a593Smuzhiyun #define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L 0x0733 178*4882a593Smuzhiyun #define WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL 0x0735 179*4882a593Smuzhiyun #define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_R 0x0736 180*4882a593Smuzhiyun #define WCD934X_HPH_NEW_INT_HPH_TIMER1 0x073a 181*4882a593Smuzhiyun #define WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK BIT(1) 182*4882a593Smuzhiyun #define WCD934X_HPH_AUTOCHOP_TIMER_ENABLE BIT(1) 183*4882a593Smuzhiyun #define WCD934X_CDC_TX0_TX_PATH_CTL 0x0a31 184*4882a593Smuzhiyun #define WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0) 185*4882a593Smuzhiyun #define WCD934X_CDC_TX_PATH_CTL(dec) (0xa31 + dec * 0x10) 186*4882a593Smuzhiyun #define WCD934X_CDC_TX0_TX_PATH_CFG0 0x0a32 187*4882a593Smuzhiyun #define WCD934X_CDC_TX0_TX_PATH_CFG1 0x0a33 188*4882a593Smuzhiyun #define WCD934X_CDC_TX0_TX_VOL_CTL 0x0a34 189*4882a593Smuzhiyun #define WCD934X_CDC_TX0_TX_PATH_192_CTL 0x0a35 190*4882a593Smuzhiyun #define WCD934X_CDC_TX0_TX_PATH_192_CFG 0x0a36 191*4882a593Smuzhiyun #define WCD934X_CDC_TX0_TX_PATH_SEC2 0x0a39 192*4882a593Smuzhiyun #define WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK BIT(1) 193*4882a593Smuzhiyun #define WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ BIT(1) 194*4882a593Smuzhiyun #define WCD934X_CDC_TX1_TX_PATH_CTL 0x0a41 195*4882a593Smuzhiyun #define WCD934X_CDC_TX1_TX_PATH_CFG0 0x0a42 196*4882a593Smuzhiyun #define WCD934X_CDC_TX1_TX_PATH_CFG1 0x0a43 197*4882a593Smuzhiyun #define WCD934X_CDC_TX1_TX_VOL_CTL 0x0a44 198*4882a593Smuzhiyun #define WCD934X_CDC_TX2_TX_PATH_CTL 0x0a51 199*4882a593Smuzhiyun #define WCD934X_CDC_TX2_TX_PATH_CFG0 0x0a52 200*4882a593Smuzhiyun #define WCD934X_CDC_TX2_TX_PATH_CFG1 0x0a53 201*4882a593Smuzhiyun #define WCD934X_CDC_TX2_TX_VOL_CTL 0x0a54 202*4882a593Smuzhiyun #define WCD934X_CDC_TX3_TX_PATH_CTL 0x0a61 203*4882a593Smuzhiyun #define WCD934X_CDC_TX3_TX_PATH_CFG0 0x0a62 204*4882a593Smuzhiyun #define WCD934X_CDC_TX3_TX_PATH_CFG1 0x0a63 205*4882a593Smuzhiyun #define WCD934X_CDC_TX3_TX_VOL_CTL 0x0a64 206*4882a593Smuzhiyun #define WCD934X_CDC_TX3_TX_PATH_192_CTL 0x0a65 207*4882a593Smuzhiyun #define WCD934X_CDC_TX3_TX_PATH_192_CFG 0x0a66 208*4882a593Smuzhiyun #define WCD934X_CDC_TX4_TX_PATH_CTL 0x0a71 209*4882a593Smuzhiyun #define WCD934X_CDC_TX4_TX_PATH_CFG0 0x0a72 210*4882a593Smuzhiyun #define WCD934X_CDC_TX4_TX_PATH_CFG1 0x0a73 211*4882a593Smuzhiyun #define WCD934X_CDC_TX4_TX_VOL_CTL 0x0a74 212*4882a593Smuzhiyun #define WCD934X_CDC_TX4_TX_PATH_192_CTL 0x0a75 213*4882a593Smuzhiyun #define WCD934X_CDC_TX4_TX_PATH_192_CFG 0x0a76 214*4882a593Smuzhiyun #define WCD934X_CDC_TX5_TX_PATH_CTL 0x0a81 215*4882a593Smuzhiyun #define WCD934X_CDC_TX5_TX_PATH_CFG0 0x0a82 216*4882a593Smuzhiyun #define WCD934X_CDC_TX5_TX_PATH_CFG1 0x0a83 217*4882a593Smuzhiyun #define WCD934X_CDC_TX5_TX_VOL_CTL 0x0a84 218*4882a593Smuzhiyun #define WCD934X_CDC_TX5_TX_PATH_192_CTL 0x0a85 219*4882a593Smuzhiyun #define WCD934X_CDC_TX5_TX_PATH_192_CFG 0x0a86 220*4882a593Smuzhiyun #define WCD934X_CDC_TX6_TX_PATH_CTL 0x0a91 221*4882a593Smuzhiyun #define WCD934X_CDC_TX6_TX_PATH_CFG0 0x0a92 222*4882a593Smuzhiyun #define WCD934X_CDC_TX6_TX_PATH_CFG1 0x0a93 223*4882a593Smuzhiyun #define WCD934X_CDC_TX6_TX_VOL_CTL 0x0a94 224*4882a593Smuzhiyun #define WCD934X_CDC_TX6_TX_PATH_192_CTL 0x0a95 225*4882a593Smuzhiyun #define WCD934X_CDC_TX6_TX_PATH_192_CFG 0x0a96 226*4882a593Smuzhiyun #define WCD934X_CDC_TX7_TX_PATH_CTL 0x0aa1 227*4882a593Smuzhiyun #define WCD934X_CDC_TX7_TX_PATH_CFG0 0x0aa2 228*4882a593Smuzhiyun #define WCD934X_CDC_TX7_TX_PATH_CFG1 0x0aa3 229*4882a593Smuzhiyun #define WCD934X_CDC_TX7_TX_VOL_CTL 0x0aa4 230*4882a593Smuzhiyun #define WCD934X_CDC_TX7_TX_PATH_192_CTL 0x0aa5 231*4882a593Smuzhiyun #define WCD934X_CDC_TX7_TX_PATH_192_CFG 0x0aa6 232*4882a593Smuzhiyun #define WCD934X_CDC_TX8_TX_PATH_CTL 0x0ab1 233*4882a593Smuzhiyun #define WCD934X_CDC_TX8_TX_PATH_CFG0 0x0ab2 234*4882a593Smuzhiyun #define WCD934X_CDC_TX8_TX_PATH_CFG1 0x0ab3 235*4882a593Smuzhiyun #define WCD934X_CDC_TX8_TX_VOL_CTL 0x0ab4 236*4882a593Smuzhiyun #define WCD934X_CDC_TX8_TX_PATH_192_CTL 0x0ab5 237*4882a593Smuzhiyun #define WCD934X_CDC_TX8_TX_PATH_192_CFG 0x0ab6 238*4882a593Smuzhiyun #define WCD934X_CDC_TX9_SPKR_PROT_PATH_CFG0 0x0ac3 239*4882a593Smuzhiyun #define WCD934X_CDC_TX10_SPKR_PROT_PATH_CFG0 0x0ac7 240*4882a593Smuzhiyun #define WCD934X_CDC_TX11_SPKR_PROT_PATH_CFG0 0x0acb 241*4882a593Smuzhiyun #define WCD934X_CDC_TX12_SPKR_PROT_PATH_CFG0 0x0acf 242*4882a593Smuzhiyun #define WCD934X_CDC_COMPANDER1_CTL0 0x0b01 243*4882a593Smuzhiyun #define WCD934X_COMP_CLK_EN_MASK BIT(0) 244*4882a593Smuzhiyun #define WCD934X_COMP_CLK_ENABLE BIT(0) 245*4882a593Smuzhiyun #define WCD934X_COMP_SOFT_RST_MASK BIT(1) 246*4882a593Smuzhiyun #define WCD934X_COMP_SOFT_RST_ENABLE BIT(1) 247*4882a593Smuzhiyun #define WCD934X_COMP_HALT_MASK BIT(2) 248*4882a593Smuzhiyun #define WCD934X_COMP_HALT BIT(2) 249*4882a593Smuzhiyun #define WCD934X_COMP_SOFT_RST_DISABLE 0 250*4882a593Smuzhiyun #define WCD934X_CDC_COMPANDER1_CTL7 0x0b08 251*4882a593Smuzhiyun #define WCD934X_HPH_LOW_PWR_MODE_EN_MASK BIT(5) 252*4882a593Smuzhiyun #define WCD934X_CDC_COMPANDER2_CTL7 0x0b10 253*4882a593Smuzhiyun #define WCD934X_CDC_COMPANDER7_CTL3 0x0b34 254*4882a593Smuzhiyun #define WCD934X_CDC_COMPANDER7_CTL7 0x0b38 255*4882a593Smuzhiyun #define WCD934X_CDC_COMPANDER8_CTL3 0x0b3c 256*4882a593Smuzhiyun #define WCD934X_CDC_COMPANDER8_CTL7 0x0b40 257*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_CTL 0x0b41 258*4882a593Smuzhiyun #define WCD934X_CDC_RX_PGA_MUTE_EN_MASK BIT(4) 259*4882a593Smuzhiyun #define WCD934X_CDC_RX_PGA_MUTE_ENABLE BIT(4) 260*4882a593Smuzhiyun #define WCD934X_CDC_RX_PGA_MUTE_DISABLE 0 261*4882a593Smuzhiyun #define WCD934X_RX_CLK_EN_MASK BIT(5) 262*4882a593Smuzhiyun #define WCD934X_RX_CLK_ENABLE BIT(5) 263*4882a593Smuzhiyun #define WCD934X_RX_RESET_MASK BIT(6) 264*4882a593Smuzhiyun #define WCD934X_RX_RESET_ENABLE BIT(6) 265*4882a593Smuzhiyun #define WCD934X_RX_RESET_DISABLE 0 266*4882a593Smuzhiyun #define WCD934X_RX_PCM_RATE_MASK GENMASK(3, 0) 267*4882a593Smuzhiyun #define WCD934X_RX_PCM_RATE_F_48K 0x04 268*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_CTL(rx) (0xb41 + rx * 0x14) 269*4882a593Smuzhiyun #define WCD934X_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0) 270*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_CFG0 0x0b42 271*4882a593Smuzhiyun #define WCD934X_RX_DLY_ZN_EN_MASK BIT(3) 272*4882a593Smuzhiyun #define WCD934X_RX_DLY_ZN_ENABLE BIT(3) 273*4882a593Smuzhiyun #define WCD934X_RX_DLY_ZN_DISABLE 0 274*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_CFG1 0x0b43 275*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_CFG2 0x0b44 276*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_VOL_CTL 0x0b45 277*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_MIX_CTL 0x0b46 278*4882a593Smuzhiyun #define WCD934X_CDC_RX_MIX_CLK_EN_MASK BIT(5) 279*4882a593Smuzhiyun #define WCD934X_CDC_RX_MIX_CLK_ENABLE BIT(5) 280*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_MIX_CTL(rx) (0xb46 + rx * 0x14) 281*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_MIX_CFG 0x0b47 282*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_VOL_MIX_CTL 0x0b48 283*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_SEC0 0x0b49 284*4882a593Smuzhiyun #define WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL 0x0b53 285*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_CTL 0x0b55 286*4882a593Smuzhiyun #define WCD934X_RX_PATH_PGA_MUTE_EN_MASK BIT(4) 287*4882a593Smuzhiyun #define WCD934X_RX_PATH_PGA_MUTE_ENABLE BIT(4) 288*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_PGA_MUTE_DISABLE 0 289*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_CLK_EN_MASK BIT(5) 290*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_CLK_ENABLE BIT(5) 291*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_CLK_DISABLE 0 292*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_CFG0 0x0b56 293*4882a593Smuzhiyun #define WCD934X_HPH_CMP_EN_MASK BIT(1) 294*4882a593Smuzhiyun #define WCD934X_HPH_CMP_ENABLE BIT(1) 295*4882a593Smuzhiyun #define WCD934X_HPH_CMP_DISABLE 0 296*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_CFG2 0x0b58 297*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_VOL_CTL 0x0b59 298*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_MIX_CTL 0x0b5a 299*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_MIX_CFG 0x0b5b 300*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_VOL_MIX_CTL 0x0b5c 301*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_SEC0 0x0b5d 302*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_SEC3 0x0b60 303*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2) 304*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125 0x14 305*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000 0 306*4882a593Smuzhiyun #define WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL 0x0b67 307*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_CTL 0x0b69 308*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_CFG0 0x0b6a 309*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2) 310*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE BIT(2) 311*4882a593Smuzhiyun #define WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE 0 312*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_CFG2 0x0b6c 313*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_VOL_CTL 0x0b6d 314*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_MIX_CTL 0x0b6e 315*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_MIX_CFG 0x0b6f 316*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_VOL_MIX_CTL 0x0b70 317*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_SEC0 0x0b71 318*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_SEC3 0x0b74 319*4882a593Smuzhiyun #define WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL 0x0b7b 320*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_PATH_CTL 0x0b7d 321*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_PATH_CFG0 0x0b6e 322*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_PATH_CFG2 0x0b80 323*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_VOL_CTL 0x0b81 324*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_PATH_MIX_CTL 0x0b82 325*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_PATH_MIX_CFG 0x0b83 326*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_VOL_MIX_CTL 0x0b84 327*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_PATH_SEC0 0x0b85 328*4882a593Smuzhiyun #define WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL 0x0b8f 329*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_PATH_CTL 0x0b91 330*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_PATH_CFG0 0x0b92 331*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_PATH_CFG2 0x0b94 332*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_VOL_CTL 0x0b95 333*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_PATH_MIX_CTL 0x0b96 334*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_PATH_MIX_CFG 0x0b97 335*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_VOL_MIX_CTL 0x0b98 336*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_PATH_SEC0 0x0b99 337*4882a593Smuzhiyun #define WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL 0x0ba3 338*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_CTL 0x0bcd 339*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_CFG0 0x0bce 340*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_CFG1 0x0bcf 341*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_CFG2 0x0bd0 342*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_VOL_CTL 0x0bd1 343*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_MIX_CTL 0x0bd2 344*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_MIX_CFG 0x0bd3 345*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_VOL_MIX_CTL 0x0bd4 346*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_SEC1 0x0bd6 347*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_MIX_SEC0 0x0bdd 348*4882a593Smuzhiyun #define WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL 0x0bdf 349*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_CTL 0x0be1 350*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_CFG0 0x0be2 351*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_CFG1 0x0be3 352*4882a593Smuzhiyun #define WCD934X_RX_SMART_BOOST_EN_MASK BIT(0) 353*4882a593Smuzhiyun #define WCD934X_RX_SMART_BOOST_ENABLE BIT(0) 354*4882a593Smuzhiyun #define WCD934X_RX_SMART_BOOST_DISABLE 0 355*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_CFG2 0x0be4 356*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_VOL_CTL 0x0be5 357*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_MIX_CTL 0x0be6 358*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_MIX_CFG 0x0be7 359*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_VOL_MIX_CTL 0x0be8 360*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_SEC1 0x0bea 361*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_MIX_SEC0 0x0bf1 362*4882a593Smuzhiyun #define WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL 0x0bf3 363*4882a593Smuzhiyun #define WCD934X_CDC_CLSH_DECAY_CTRL 0x0c03 364*4882a593Smuzhiyun #define WCD934X_CDC_CLSH_K2_MSB 0x0c0a 365*4882a593Smuzhiyun #define WCD934X_CDC_CLSH_K2_LSB 0x0c0b 366*4882a593Smuzhiyun #define WCD934X_CDC_CLSH_TEST0 0x0c0f 367*4882a593Smuzhiyun #define WCD934X_CDC_BOOST0_BOOST_PATH_CTL 0x0c19 368*4882a593Smuzhiyun #define WCD934X_BOOST_PATH_CLK_EN_MASK BIT(4) 369*4882a593Smuzhiyun #define WCD934X_BOOST_PATH_CLK_ENABLE BIT(4) 370*4882a593Smuzhiyun #define WCD934X_BOOST_PATH_CLK_DISABLE 0 371*4882a593Smuzhiyun #define WCD934X_CDC_BOOST0_BOOST_CTL 0x0c1a 372*4882a593Smuzhiyun #define WCD934X_CDC_BOOST0_BOOST_CFG1 0x0c1b 373*4882a593Smuzhiyun #define WCD934X_CDC_BOOST0_BOOST_CFG2 0x0c1c 374*4882a593Smuzhiyun #define WCD934X_CDC_BOOST1_BOOST_PATH_CTL 0x0c21 375*4882a593Smuzhiyun #define WCD934X_CDC_BOOST1_BOOST_CTL 0x0c22 376*4882a593Smuzhiyun #define WCD934X_CDC_BOOST1_BOOST_CFG1 0x0c23 377*4882a593Smuzhiyun #define WCD934X_CDC_BOOST1_BOOST_CFG2 0x0c24 378*4882a593Smuzhiyun #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_0 0x0c91 379*4882a593Smuzhiyun #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_1 0x0c92 380*4882a593Smuzhiyun #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_2 0x0c93 381*4882a593Smuzhiyun #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_3 0x0c94 382*4882a593Smuzhiyun #define WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS 0x0c96 383*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL 0x0cb5 384*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL 0x0cb9 385*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0 0x0d01 386*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(i) (0xd01 + i * 0x2) 387*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0) 388*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1 0x0d02 389*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(i) (0xd02 + i * 0x2) 390*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0 0x0d03 391*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1 0x0d04 392*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0 0x0d05 393*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1 0x0d06 394*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0 0x0d07 395*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1 0x0d08 396*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0 0x0d09 397*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1 0x0d0a 398*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0 0x0d0f 399*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1 0x0d10 400*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0 0x0d11 401*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1 0x0d12 402*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG0 0x0d13 403*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG1 0x0d14 404*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG2 0x0d15 405*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG3 0x0d16 406*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG4 0x0d17 407*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 0x0d18 408*4882a593Smuzhiyun #define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1 0x0d19 409*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 0x0d1d 410*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 0x0d1e 411*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0 0x0d1f 412*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1 0x0d20 413*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0 0x0d21 414*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1 0x0d22 415*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0 0x0d23 416*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1 0x0d25 417*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 0x0d26 418*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0 0x0d27 419*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0 0x0d28 420*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0 0x0d29 421*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0 0x0d2a 422*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX10_CFG0 0x0d2b 423*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX11_CFG0 0x0d2c 424*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX12_CFG0 0x0d2d 425*4882a593Smuzhiyun #define WCD934X_CDC_TX_INP_MUX_ADC_MUX13_CFG0 0x0d2e 426*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0 0x0d31 427*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1 0x0d32 428*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2 0x0d33 429*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3 0x0d34 430*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0 0x0d35 431*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1 0x0d36 432*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2 0x0d37 433*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3 0x0d38 434*4882a593Smuzhiyun #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0 0x0d3a 435*4882a593Smuzhiyun #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1 0x0d3b 436*4882a593Smuzhiyun #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2 0x0d3c 437*4882a593Smuzhiyun #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3 0x0d3d 438*4882a593Smuzhiyun #define WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL 0x0d41 439*4882a593Smuzhiyun #define WCD934X_CDC_MCLK_EN_MASK BIT(0) 440*4882a593Smuzhiyun #define WCD934X_CDC_MCLK_EN_ENABLE BIT(0) 441*4882a593Smuzhiyun #define WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL 0x0d42 442*4882a593Smuzhiyun #define WCD934X_CDC_FS_MCLK_CNT_EN_MASK BIT(0) 443*4882a593Smuzhiyun #define WCD934X_CDC_FS_MCLK_CNT_ENABLE BIT(0) 444*4882a593Smuzhiyun #define WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL 0x0d43 445*4882a593Smuzhiyun #define WCD934X_CDC_SWR_CLK_EN_MASK BIT(0) 446*4882a593Smuzhiyun #define WCD934X_CDC_SWR_CLK_ENABLE BIT(0) 447*4882a593Smuzhiyun #define WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL 0x0d44 448*4882a593Smuzhiyun #define WCD934X_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL 0x0d45 449*4882a593Smuzhiyun #define WCD934X_CDC_CLK_RST_CTRL_GFM_CONTROL 0x0d46 450*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_PATH_CTL 0x0d55 451*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL 0x0d56 452*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL 0x0d57 453*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL 0x0d58 454*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL 0x0d59 455*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL 0x0d5a 456*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL 0x0d5b 457*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL 0x0d5c 458*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL 0x0d5d 459*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_CTL 0x0d5e 460*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL 0x0d5f 461*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL 0x0d60 462*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL 0x0d61 463*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_PATH_CTL 0x0d65 464*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL 0x0d66 465*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL 0x0d67 466*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL 0x0d68 467*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL 0x0d69 468*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL 0x0d6a 469*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL 0x0d6b 470*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL 0x0d6c 471*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL 0x0d6d 472*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_CTL 0x0d6e 473*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL 0x0d6f 474*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL 0x0d70 475*4882a593Smuzhiyun #define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL 0x0d71 476*4882a593Smuzhiyun #define WCD934X_CDC_TOP_TOP_CFG1 0x0d82 477*4882a593Smuzhiyun #define WCD934X_CDC_TOP_TOP_CFG7 0x0d88 478*4882a593Smuzhiyun #define WCD934X_CDC_TOP_HPHL_COMP_LUT 0x0d8b 479*4882a593Smuzhiyun #define WCD934X_CDC_TOP_HPHR_COMP_LUT 0x0d90 480*4882a593Smuzhiyun #define WCD934X_HPH_LUT_BYPASS_MASK BIT(7) 481*4882a593Smuzhiyun #define WCD934X_HPH_LUT_BYPASS_ENABLE BIT(7) 482*4882a593Smuzhiyun #define WCD934X_HPH_LUT_BYPASS_DISABLE 0 483*4882a593Smuzhiyun #define WCD934X_CODEC_CPR_WR_DATA_0 0x5001 484*4882a593Smuzhiyun #define WCD934X_CODEC_CPR_WR_ADDR_0 0x5005 485*4882a593Smuzhiyun #define WCD934X_CODEC_CPR_SVS_CX_VDD 0x5022 486*4882a593Smuzhiyun #define WCD934X_CODEC_CPR_SVS2_CX_VDD 0x5023 487*4882a593Smuzhiyun #define WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD 0x5027 488*4882a593Smuzhiyun #define WCD934X_TLMM_DMIC1_CLK_PINCFG 0x8015 489*4882a593Smuzhiyun #define WCD934X_TLMM_DMIC1_DATA_PINCFG 0x8016 490*4882a593Smuzhiyun #define WCD934X_TLMM_DMIC2_CLK_PINCFG 0x8017 491*4882a593Smuzhiyun #define WCD934X_TLMM_DMIC2_DATA_PINCFG 0x8018 492*4882a593Smuzhiyun #define WCD934X_TLMM_DMIC3_CLK_PINCFG 0x8019 493*4882a593Smuzhiyun #define WCD934X_TLMM_DMIC3_DATA_PINCFG 0x801a 494*4882a593Smuzhiyun #define WCD934X_TEST_DEBUG_PAD_DRVCTL_0 0x803b 495*4882a593Smuzhiyun #define WCD934X_TEST_DEBUG_NPL_DLY_TEST_1 0x803e 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun #define WCD934X_MAX_REGISTER 0xffff 498*4882a593Smuzhiyun #define WCD934X_SEL_REGISTER 0x800 499*4882a593Smuzhiyun #define WCD934X_SEL_MASK 0xff 500*4882a593Smuzhiyun #define WCD934X_SEL_SHIFT 0x0 501*4882a593Smuzhiyun #define WCD934X_WINDOW_START 0x800 502*4882a593Smuzhiyun #define WCD934X_WINDOW_LENGTH 0x100 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun /* SLIMBUS Slave Registers */ 505*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_EN0 0x30 506*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0 0x34 507*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_1 0x35 508*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_0 0x36 509*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1 0x37 510*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 0x38 511*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_1 0x39 512*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_0 0x3A 513*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_1 0x3B 514*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 0x60 515*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_TX_SOURCE0 0x70 516*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_RX_PORT_CFG(p) (0x30 + p) 517*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_CFG(p) (0x40 + p) 518*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_TX_PORT_CFG(p) (0x50 + p) 519*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_SRC(p) (0x60 + p) 520*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_PORT_INT_STATUS(p) (0x80 + p) 521*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(p) (0x100 + 4 * p) 522*4882a593Smuzhiyun /* ports range from 10-16 */ 523*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(p) (0x101 + 4 * p) 524*4882a593Smuzhiyun #define WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(p) (0x140 + 4 * p) 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun #define SLIM_MANF_ID_QCOM 0x217 527*4882a593Smuzhiyun #define SLIM_PROD_CODE_WCD9340 0x250 528*4882a593Smuzhiyun #define SLIM_DEV_IDX_WCD9340 0x1 529*4882a593Smuzhiyun #define SLIM_DEV_INSTANCE_ID_WCD9340 0 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun #endif 532