1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/include/mfd/ucb1x00.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2001 Russell King, All Rights Reserved.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef UCB1200_H
8*4882a593Smuzhiyun #define UCB1200_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/mfd/mcp.h>
12*4882a593Smuzhiyun #include <linux/gpio.h>
13*4882a593Smuzhiyun #include <linux/mutex.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define UCB_IO_DATA 0x00
16*4882a593Smuzhiyun #define UCB_IO_DIR 0x01
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define UCB_IO_0 (1 << 0)
19*4882a593Smuzhiyun #define UCB_IO_1 (1 << 1)
20*4882a593Smuzhiyun #define UCB_IO_2 (1 << 2)
21*4882a593Smuzhiyun #define UCB_IO_3 (1 << 3)
22*4882a593Smuzhiyun #define UCB_IO_4 (1 << 4)
23*4882a593Smuzhiyun #define UCB_IO_5 (1 << 5)
24*4882a593Smuzhiyun #define UCB_IO_6 (1 << 6)
25*4882a593Smuzhiyun #define UCB_IO_7 (1 << 7)
26*4882a593Smuzhiyun #define UCB_IO_8 (1 << 8)
27*4882a593Smuzhiyun #define UCB_IO_9 (1 << 9)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define UCB_IE_RIS 0x02
30*4882a593Smuzhiyun #define UCB_IE_FAL 0x03
31*4882a593Smuzhiyun #define UCB_IE_STATUS 0x04
32*4882a593Smuzhiyun #define UCB_IE_CLEAR 0x04
33*4882a593Smuzhiyun #define UCB_IE_ADC (1 << 11)
34*4882a593Smuzhiyun #define UCB_IE_TSPX (1 << 12)
35*4882a593Smuzhiyun #define UCB_IE_TSMX (1 << 13)
36*4882a593Smuzhiyun #define UCB_IE_TCLIP (1 << 14)
37*4882a593Smuzhiyun #define UCB_IE_ACLIP (1 << 15)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define UCB_IRQ_TSPX 12
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define UCB_TC_A 0x05
42*4882a593Smuzhiyun #define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
43*4882a593Smuzhiyun #define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define UCB_TC_B 0x06
46*4882a593Smuzhiyun #define UCB_TC_B_VOICE_ENA (1 << 3)
47*4882a593Smuzhiyun #define UCB_TC_B_CLIP (1 << 4)
48*4882a593Smuzhiyun #define UCB_TC_B_ATT (1 << 6)
49*4882a593Smuzhiyun #define UCB_TC_B_SIDE_ENA (1 << 11)
50*4882a593Smuzhiyun #define UCB_TC_B_MUTE (1 << 13)
51*4882a593Smuzhiyun #define UCB_TC_B_IN_ENA (1 << 14)
52*4882a593Smuzhiyun #define UCB_TC_B_OUT_ENA (1 << 15)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define UCB_AC_A 0x07
55*4882a593Smuzhiyun #define UCB_AC_B 0x08
56*4882a593Smuzhiyun #define UCB_AC_B_LOOP (1 << 8)
57*4882a593Smuzhiyun #define UCB_AC_B_MUTE (1 << 13)
58*4882a593Smuzhiyun #define UCB_AC_B_IN_ENA (1 << 14)
59*4882a593Smuzhiyun #define UCB_AC_B_OUT_ENA (1 << 15)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define UCB_TS_CR 0x09
62*4882a593Smuzhiyun #define UCB_TS_CR_TSMX_POW (1 << 0)
63*4882a593Smuzhiyun #define UCB_TS_CR_TSPX_POW (1 << 1)
64*4882a593Smuzhiyun #define UCB_TS_CR_TSMY_POW (1 << 2)
65*4882a593Smuzhiyun #define UCB_TS_CR_TSPY_POW (1 << 3)
66*4882a593Smuzhiyun #define UCB_TS_CR_TSMX_GND (1 << 4)
67*4882a593Smuzhiyun #define UCB_TS_CR_TSPX_GND (1 << 5)
68*4882a593Smuzhiyun #define UCB_TS_CR_TSMY_GND (1 << 6)
69*4882a593Smuzhiyun #define UCB_TS_CR_TSPY_GND (1 << 7)
70*4882a593Smuzhiyun #define UCB_TS_CR_MODE_INT (0 << 8)
71*4882a593Smuzhiyun #define UCB_TS_CR_MODE_PRES (1 << 8)
72*4882a593Smuzhiyun #define UCB_TS_CR_MODE_POS (2 << 8)
73*4882a593Smuzhiyun #define UCB_TS_CR_BIAS_ENA (1 << 11)
74*4882a593Smuzhiyun #define UCB_TS_CR_TSPX_LOW (1 << 12)
75*4882a593Smuzhiyun #define UCB_TS_CR_TSMX_LOW (1 << 13)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define UCB_ADC_CR 0x0a
78*4882a593Smuzhiyun #define UCB_ADC_SYNC_ENA (1 << 0)
79*4882a593Smuzhiyun #define UCB_ADC_VREFBYP_CON (1 << 1)
80*4882a593Smuzhiyun #define UCB_ADC_INP_TSPX (0 << 2)
81*4882a593Smuzhiyun #define UCB_ADC_INP_TSMX (1 << 2)
82*4882a593Smuzhiyun #define UCB_ADC_INP_TSPY (2 << 2)
83*4882a593Smuzhiyun #define UCB_ADC_INP_TSMY (3 << 2)
84*4882a593Smuzhiyun #define UCB_ADC_INP_AD0 (4 << 2)
85*4882a593Smuzhiyun #define UCB_ADC_INP_AD1 (5 << 2)
86*4882a593Smuzhiyun #define UCB_ADC_INP_AD2 (6 << 2)
87*4882a593Smuzhiyun #define UCB_ADC_INP_AD3 (7 << 2)
88*4882a593Smuzhiyun #define UCB_ADC_EXT_REF (1 << 5)
89*4882a593Smuzhiyun #define UCB_ADC_START (1 << 7)
90*4882a593Smuzhiyun #define UCB_ADC_ENA (1 << 15)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define UCB_ADC_DATA 0x0b
93*4882a593Smuzhiyun #define UCB_ADC_DAT_VAL (1 << 15)
94*4882a593Smuzhiyun #define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define UCB_ID 0x0c
97*4882a593Smuzhiyun #define UCB_ID_1200 0x1004
98*4882a593Smuzhiyun #define UCB_ID_1300 0x1005
99*4882a593Smuzhiyun #define UCB_ID_TC35143 0x9712
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define UCB_MODE 0x0d
102*4882a593Smuzhiyun #define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
103*4882a593Smuzhiyun #define UCB_MODE_AUD_OFF_CAN (1 << 13)
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun enum ucb1x00_reset {
106*4882a593Smuzhiyun UCB_RST_PROBE,
107*4882a593Smuzhiyun UCB_RST_RESUME,
108*4882a593Smuzhiyun UCB_RST_SUSPEND,
109*4882a593Smuzhiyun UCB_RST_REMOVE,
110*4882a593Smuzhiyun UCB_RST_PROBE_FAIL,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun struct ucb1x00_plat_data {
114*4882a593Smuzhiyun void (*reset)(enum ucb1x00_reset);
115*4882a593Smuzhiyun unsigned irq_base;
116*4882a593Smuzhiyun int gpio_base;
117*4882a593Smuzhiyun unsigned can_wakeup;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun struct ucb1x00 {
121*4882a593Smuzhiyun raw_spinlock_t irq_lock;
122*4882a593Smuzhiyun struct mcp *mcp;
123*4882a593Smuzhiyun unsigned int irq;
124*4882a593Smuzhiyun int irq_base;
125*4882a593Smuzhiyun struct mutex adc_mutex;
126*4882a593Smuzhiyun spinlock_t io_lock;
127*4882a593Smuzhiyun u16 id;
128*4882a593Smuzhiyun u16 io_dir;
129*4882a593Smuzhiyun u16 io_out;
130*4882a593Smuzhiyun u16 adc_cr;
131*4882a593Smuzhiyun u16 irq_fal_enbl;
132*4882a593Smuzhiyun u16 irq_ris_enbl;
133*4882a593Smuzhiyun u16 irq_mask;
134*4882a593Smuzhiyun u16 irq_wake;
135*4882a593Smuzhiyun struct device dev;
136*4882a593Smuzhiyun struct list_head node;
137*4882a593Smuzhiyun struct list_head devs;
138*4882a593Smuzhiyun struct gpio_chip gpio;
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun struct ucb1x00_driver;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun struct ucb1x00_dev {
144*4882a593Smuzhiyun struct list_head dev_node;
145*4882a593Smuzhiyun struct list_head drv_node;
146*4882a593Smuzhiyun struct ucb1x00 *ucb;
147*4882a593Smuzhiyun struct ucb1x00_driver *drv;
148*4882a593Smuzhiyun void *priv;
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun struct ucb1x00_driver {
152*4882a593Smuzhiyun struct list_head node;
153*4882a593Smuzhiyun struct list_head devs;
154*4882a593Smuzhiyun int (*add)(struct ucb1x00_dev *dev);
155*4882a593Smuzhiyun void (*remove)(struct ucb1x00_dev *dev);
156*4882a593Smuzhiyun int (*suspend)(struct ucb1x00_dev *dev);
157*4882a593Smuzhiyun int (*resume)(struct ucb1x00_dev *dev);
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun int ucb1x00_register_driver(struct ucb1x00_driver *);
163*4882a593Smuzhiyun void ucb1x00_unregister_driver(struct ucb1x00_driver *);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /**
166*4882a593Smuzhiyun * ucb1x00_clkrate - return the UCB1x00 SIB clock rate
167*4882a593Smuzhiyun * @ucb: UCB1x00 structure describing chip
168*4882a593Smuzhiyun *
169*4882a593Smuzhiyun * Return the SIB clock rate in Hz.
170*4882a593Smuzhiyun */
ucb1x00_clkrate(struct ucb1x00 * ucb)171*4882a593Smuzhiyun static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun return mcp_get_sclk_rate(ucb->mcp);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /**
177*4882a593Smuzhiyun * ucb1x00_enable - enable the UCB1x00 SIB clock
178*4882a593Smuzhiyun * @ucb: UCB1x00 structure describing chip
179*4882a593Smuzhiyun *
180*4882a593Smuzhiyun * Enable the SIB clock. This can be called multiple times.
181*4882a593Smuzhiyun */
ucb1x00_enable(struct ucb1x00 * ucb)182*4882a593Smuzhiyun static inline void ucb1x00_enable(struct ucb1x00 *ucb)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun mcp_enable(ucb->mcp);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /**
188*4882a593Smuzhiyun * ucb1x00_disable - disable the UCB1x00 SIB clock
189*4882a593Smuzhiyun * @ucb: UCB1x00 structure describing chip
190*4882a593Smuzhiyun *
191*4882a593Smuzhiyun * Disable the SIB clock. The SIB clock will only be disabled
192*4882a593Smuzhiyun * when the number of ucb1x00_enable calls match the number of
193*4882a593Smuzhiyun * ucb1x00_disable calls.
194*4882a593Smuzhiyun */
ucb1x00_disable(struct ucb1x00 * ucb)195*4882a593Smuzhiyun static inline void ucb1x00_disable(struct ucb1x00 *ucb)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun mcp_disable(ucb->mcp);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun /**
201*4882a593Smuzhiyun * ucb1x00_reg_write - write a UCB1x00 register
202*4882a593Smuzhiyun * @ucb: UCB1x00 structure describing chip
203*4882a593Smuzhiyun * @reg: UCB1x00 4-bit register index to write
204*4882a593Smuzhiyun * @val: UCB1x00 16-bit value to write
205*4882a593Smuzhiyun *
206*4882a593Smuzhiyun * Write the UCB1x00 register @reg with value @val. The SIB
207*4882a593Smuzhiyun * clock must be running for this function to return.
208*4882a593Smuzhiyun */
ucb1x00_reg_write(struct ucb1x00 * ucb,unsigned int reg,unsigned int val)209*4882a593Smuzhiyun static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun mcp_reg_write(ucb->mcp, reg, val);
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /**
215*4882a593Smuzhiyun * ucb1x00_reg_read - read a UCB1x00 register
216*4882a593Smuzhiyun * @ucb: UCB1x00 structure describing chip
217*4882a593Smuzhiyun * @reg: UCB1x00 4-bit register index to write
218*4882a593Smuzhiyun *
219*4882a593Smuzhiyun * Read the UCB1x00 register @reg and return its value. The SIB
220*4882a593Smuzhiyun * clock must be running for this function to return.
221*4882a593Smuzhiyun */
ucb1x00_reg_read(struct ucb1x00 * ucb,unsigned int reg)222*4882a593Smuzhiyun static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun return mcp_reg_read(ucb->mcp, reg);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun /**
227*4882a593Smuzhiyun * ucb1x00_set_audio_divisor -
228*4882a593Smuzhiyun * @ucb: UCB1x00 structure describing chip
229*4882a593Smuzhiyun * @div: SIB clock divisor
230*4882a593Smuzhiyun */
ucb1x00_set_audio_divisor(struct ucb1x00 * ucb,unsigned int div)231*4882a593Smuzhiyun static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun mcp_set_audio_divisor(ucb->mcp, div);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /**
237*4882a593Smuzhiyun * ucb1x00_set_telecom_divisor -
238*4882a593Smuzhiyun * @ucb: UCB1x00 structure describing chip
239*4882a593Smuzhiyun * @div: SIB clock divisor
240*4882a593Smuzhiyun */
ucb1x00_set_telecom_divisor(struct ucb1x00 * ucb,unsigned int div)241*4882a593Smuzhiyun static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun mcp_set_telecom_divisor(ucb->mcp, div);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
247*4882a593Smuzhiyun void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
248*4882a593Smuzhiyun unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun #define UCB_NOSYNC (0)
251*4882a593Smuzhiyun #define UCB_SYNC (1)
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
254*4882a593Smuzhiyun void ucb1x00_adc_enable(struct ucb1x00 *ucb);
255*4882a593Smuzhiyun void ucb1x00_adc_disable(struct ucb1x00 *ucb);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun #endif
258