1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * MFD driver for twl4030 audio submodule 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright: (C) 2009 Nokia Corporation 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __TWL4030_CODEC_H__ 11*4882a593Smuzhiyun #define __TWL4030_CODEC_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Codec registers */ 14*4882a593Smuzhiyun #define TWL4030_REG_CODEC_MODE 0x01 15*4882a593Smuzhiyun #define TWL4030_REG_OPTION 0x02 16*4882a593Smuzhiyun #define TWL4030_REG_UNKNOWN 0x03 17*4882a593Smuzhiyun #define TWL4030_REG_MICBIAS_CTL 0x04 18*4882a593Smuzhiyun #define TWL4030_REG_ANAMICL 0x05 19*4882a593Smuzhiyun #define TWL4030_REG_ANAMICR 0x06 20*4882a593Smuzhiyun #define TWL4030_REG_AVADC_CTL 0x07 21*4882a593Smuzhiyun #define TWL4030_REG_ADCMICSEL 0x08 22*4882a593Smuzhiyun #define TWL4030_REG_DIGMIXING 0x09 23*4882a593Smuzhiyun #define TWL4030_REG_ATXL1PGA 0x0A 24*4882a593Smuzhiyun #define TWL4030_REG_ATXR1PGA 0x0B 25*4882a593Smuzhiyun #define TWL4030_REG_AVTXL2PGA 0x0C 26*4882a593Smuzhiyun #define TWL4030_REG_AVTXR2PGA 0x0D 27*4882a593Smuzhiyun #define TWL4030_REG_AUDIO_IF 0x0E 28*4882a593Smuzhiyun #define TWL4030_REG_VOICE_IF 0x0F 29*4882a593Smuzhiyun #define TWL4030_REG_ARXR1PGA 0x10 30*4882a593Smuzhiyun #define TWL4030_REG_ARXL1PGA 0x11 31*4882a593Smuzhiyun #define TWL4030_REG_ARXR2PGA 0x12 32*4882a593Smuzhiyun #define TWL4030_REG_ARXL2PGA 0x13 33*4882a593Smuzhiyun #define TWL4030_REG_VRXPGA 0x14 34*4882a593Smuzhiyun #define TWL4030_REG_VSTPGA 0x15 35*4882a593Smuzhiyun #define TWL4030_REG_VRX2ARXPGA 0x16 36*4882a593Smuzhiyun #define TWL4030_REG_AVDAC_CTL 0x17 37*4882a593Smuzhiyun #define TWL4030_REG_ARX2VTXPGA 0x18 38*4882a593Smuzhiyun #define TWL4030_REG_ARXL1_APGA_CTL 0x19 39*4882a593Smuzhiyun #define TWL4030_REG_ARXR1_APGA_CTL 0x1A 40*4882a593Smuzhiyun #define TWL4030_REG_ARXL2_APGA_CTL 0x1B 41*4882a593Smuzhiyun #define TWL4030_REG_ARXR2_APGA_CTL 0x1C 42*4882a593Smuzhiyun #define TWL4030_REG_ATX2ARXPGA 0x1D 43*4882a593Smuzhiyun #define TWL4030_REG_BT_IF 0x1E 44*4882a593Smuzhiyun #define TWL4030_REG_BTPGA 0x1F 45*4882a593Smuzhiyun #define TWL4030_REG_BTSTPGA 0x20 46*4882a593Smuzhiyun #define TWL4030_REG_EAR_CTL 0x21 47*4882a593Smuzhiyun #define TWL4030_REG_HS_SEL 0x22 48*4882a593Smuzhiyun #define TWL4030_REG_HS_GAIN_SET 0x23 49*4882a593Smuzhiyun #define TWL4030_REG_HS_POPN_SET 0x24 50*4882a593Smuzhiyun #define TWL4030_REG_PREDL_CTL 0x25 51*4882a593Smuzhiyun #define TWL4030_REG_PREDR_CTL 0x26 52*4882a593Smuzhiyun #define TWL4030_REG_PRECKL_CTL 0x27 53*4882a593Smuzhiyun #define TWL4030_REG_PRECKR_CTL 0x28 54*4882a593Smuzhiyun #define TWL4030_REG_HFL_CTL 0x29 55*4882a593Smuzhiyun #define TWL4030_REG_HFR_CTL 0x2A 56*4882a593Smuzhiyun #define TWL4030_REG_ALC_CTL 0x2B 57*4882a593Smuzhiyun #define TWL4030_REG_ALC_SET1 0x2C 58*4882a593Smuzhiyun #define TWL4030_REG_ALC_SET2 0x2D 59*4882a593Smuzhiyun #define TWL4030_REG_BOOST_CTL 0x2E 60*4882a593Smuzhiyun #define TWL4030_REG_SOFTVOL_CTL 0x2F 61*4882a593Smuzhiyun #define TWL4030_REG_DTMF_FREQSEL 0x30 62*4882a593Smuzhiyun #define TWL4030_REG_DTMF_TONEXT1H 0x31 63*4882a593Smuzhiyun #define TWL4030_REG_DTMF_TONEXT1L 0x32 64*4882a593Smuzhiyun #define TWL4030_REG_DTMF_TONEXT2H 0x33 65*4882a593Smuzhiyun #define TWL4030_REG_DTMF_TONEXT2L 0x34 66*4882a593Smuzhiyun #define TWL4030_REG_DTMF_TONOFF 0x35 67*4882a593Smuzhiyun #define TWL4030_REG_DTMF_WANONOFF 0x36 68*4882a593Smuzhiyun #define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37 69*4882a593Smuzhiyun #define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38 70*4882a593Smuzhiyun #define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39 71*4882a593Smuzhiyun #define TWL4030_REG_APLL_CTL 0x3A 72*4882a593Smuzhiyun #define TWL4030_REG_DTMF_CTL 0x3B 73*4882a593Smuzhiyun #define TWL4030_REG_DTMF_PGA_CTL2 0x3C 74*4882a593Smuzhiyun #define TWL4030_REG_DTMF_PGA_CTL1 0x3D 75*4882a593Smuzhiyun #define TWL4030_REG_MISC_SET_1 0x3E 76*4882a593Smuzhiyun #define TWL4030_REG_PCMBTMUX 0x3F 77*4882a593Smuzhiyun #define TWL4030_REG_RX_PATH_SEL 0x43 78*4882a593Smuzhiyun #define TWL4030_REG_VDL_APGA_CTL 0x44 79*4882a593Smuzhiyun #define TWL4030_REG_VIBRA_CTL 0x45 80*4882a593Smuzhiyun #define TWL4030_REG_VIBRA_SET 0x46 81*4882a593Smuzhiyun #define TWL4030_REG_VIBRA_PWM_SET 0x47 82*4882a593Smuzhiyun #define TWL4030_REG_ANAMIC_GAIN 0x48 83*4882a593Smuzhiyun #define TWL4030_REG_MISC_SET_2 0x49 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Bitfield Definitions */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* TWL4030_CODEC_MODE (0x01) Fields */ 88*4882a593Smuzhiyun #define TWL4030_APLL_RATE 0xF0 89*4882a593Smuzhiyun #define TWL4030_APLL_RATE_8000 0x00 90*4882a593Smuzhiyun #define TWL4030_APLL_RATE_11025 0x10 91*4882a593Smuzhiyun #define TWL4030_APLL_RATE_12000 0x20 92*4882a593Smuzhiyun #define TWL4030_APLL_RATE_16000 0x40 93*4882a593Smuzhiyun #define TWL4030_APLL_RATE_22050 0x50 94*4882a593Smuzhiyun #define TWL4030_APLL_RATE_24000 0x60 95*4882a593Smuzhiyun #define TWL4030_APLL_RATE_32000 0x80 96*4882a593Smuzhiyun #define TWL4030_APLL_RATE_44100 0x90 97*4882a593Smuzhiyun #define TWL4030_APLL_RATE_48000 0xA0 98*4882a593Smuzhiyun #define TWL4030_APLL_RATE_96000 0xE0 99*4882a593Smuzhiyun #define TWL4030_SEL_16K 0x08 100*4882a593Smuzhiyun #define TWL4030_CODECPDZ 0x02 101*4882a593Smuzhiyun #define TWL4030_OPT_MODE 0x01 102*4882a593Smuzhiyun #define TWL4030_OPTION_1 (1 << 0) 103*4882a593Smuzhiyun #define TWL4030_OPTION_2 (0 << 0) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* TWL4030_OPTION (0x02) Fields */ 106*4882a593Smuzhiyun #define TWL4030_ATXL1_EN (1 << 0) 107*4882a593Smuzhiyun #define TWL4030_ATXR1_EN (1 << 1) 108*4882a593Smuzhiyun #define TWL4030_ATXL2_VTXL_EN (1 << 2) 109*4882a593Smuzhiyun #define TWL4030_ATXR2_VTXR_EN (1 << 3) 110*4882a593Smuzhiyun #define TWL4030_ARXL1_VRX_EN (1 << 4) 111*4882a593Smuzhiyun #define TWL4030_ARXR1_EN (1 << 5) 112*4882a593Smuzhiyun #define TWL4030_ARXL2_EN (1 << 6) 113*4882a593Smuzhiyun #define TWL4030_ARXR2_EN (1 << 7) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* TWL4030_REG_MICBIAS_CTL (0x04) Fields */ 116*4882a593Smuzhiyun #define TWL4030_MICBIAS2_CTL 0x40 117*4882a593Smuzhiyun #define TWL4030_MICBIAS1_CTL 0x20 118*4882a593Smuzhiyun #define TWL4030_HSMICBIAS_EN 0x04 119*4882a593Smuzhiyun #define TWL4030_MICBIAS2_EN 0x02 120*4882a593Smuzhiyun #define TWL4030_MICBIAS1_EN 0x01 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* ANAMICL (0x05) Fields */ 123*4882a593Smuzhiyun #define TWL4030_CNCL_OFFSET_START 0x80 124*4882a593Smuzhiyun #define TWL4030_OFFSET_CNCL_SEL 0x60 125*4882a593Smuzhiyun #define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00 126*4882a593Smuzhiyun #define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20 127*4882a593Smuzhiyun #define TWL4030_OFFSET_CNCL_SEL_VRX 0x40 128*4882a593Smuzhiyun #define TWL4030_OFFSET_CNCL_SEL_ALL 0x60 129*4882a593Smuzhiyun #define TWL4030_MICAMPL_EN 0x10 130*4882a593Smuzhiyun #define TWL4030_CKMIC_EN 0x08 131*4882a593Smuzhiyun #define TWL4030_AUXL_EN 0x04 132*4882a593Smuzhiyun #define TWL4030_HSMIC_EN 0x02 133*4882a593Smuzhiyun #define TWL4030_MAINMIC_EN 0x01 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* ANAMICR (0x06) Fields */ 136*4882a593Smuzhiyun #define TWL4030_MICAMPR_EN 0x10 137*4882a593Smuzhiyun #define TWL4030_AUXR_EN 0x04 138*4882a593Smuzhiyun #define TWL4030_SUBMIC_EN 0x01 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* AVADC_CTL (0x07) Fields */ 141*4882a593Smuzhiyun #define TWL4030_ADCL_EN 0x08 142*4882a593Smuzhiyun #define TWL4030_AVADC_CLK_PRIORITY 0x04 143*4882a593Smuzhiyun #define TWL4030_ADCR_EN 0x02 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* TWL4030_REG_ADCMICSEL (0x08) Fields */ 146*4882a593Smuzhiyun #define TWL4030_DIGMIC1_EN 0x08 147*4882a593Smuzhiyun #define TWL4030_TX2IN_SEL 0x04 148*4882a593Smuzhiyun #define TWL4030_DIGMIC0_EN 0x02 149*4882a593Smuzhiyun #define TWL4030_TX1IN_SEL 0x01 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* AUDIO_IF (0x0E) Fields */ 152*4882a593Smuzhiyun #define TWL4030_AIF_SLAVE_EN 0x80 153*4882a593Smuzhiyun #define TWL4030_DATA_WIDTH 0x60 154*4882a593Smuzhiyun #define TWL4030_DATA_WIDTH_16S_16W 0x00 155*4882a593Smuzhiyun #define TWL4030_DATA_WIDTH_32S_16W 0x40 156*4882a593Smuzhiyun #define TWL4030_DATA_WIDTH_32S_24W 0x60 157*4882a593Smuzhiyun #define TWL4030_AIF_FORMAT 0x18 158*4882a593Smuzhiyun #define TWL4030_AIF_FORMAT_CODEC 0x00 159*4882a593Smuzhiyun #define TWL4030_AIF_FORMAT_LEFT 0x08 160*4882a593Smuzhiyun #define TWL4030_AIF_FORMAT_RIGHT 0x10 161*4882a593Smuzhiyun #define TWL4030_AIF_FORMAT_TDM 0x18 162*4882a593Smuzhiyun #define TWL4030_AIF_TRI_EN 0x04 163*4882a593Smuzhiyun #define TWL4030_CLK256FS_EN 0x02 164*4882a593Smuzhiyun #define TWL4030_AIF_EN 0x01 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* VOICE_IF (0x0F) Fields */ 167*4882a593Smuzhiyun #define TWL4030_VIF_SLAVE_EN 0x80 168*4882a593Smuzhiyun #define TWL4030_VIF_DIN_EN 0x40 169*4882a593Smuzhiyun #define TWL4030_VIF_DOUT_EN 0x20 170*4882a593Smuzhiyun #define TWL4030_VIF_SWAP 0x10 171*4882a593Smuzhiyun #define TWL4030_VIF_FORMAT 0x08 172*4882a593Smuzhiyun #define TWL4030_VIF_TRI_EN 0x04 173*4882a593Smuzhiyun #define TWL4030_VIF_SUB_EN 0x02 174*4882a593Smuzhiyun #define TWL4030_VIF_EN 0x01 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* EAR_CTL (0x21) */ 177*4882a593Smuzhiyun #define TWL4030_EAR_GAIN 0x30 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* HS_GAIN_SET (0x23) Fields */ 180*4882a593Smuzhiyun #define TWL4030_HSR_GAIN 0x0C 181*4882a593Smuzhiyun #define TWL4030_HSR_GAIN_PWR_DOWN 0x00 182*4882a593Smuzhiyun #define TWL4030_HSR_GAIN_PLUS_6DB 0x04 183*4882a593Smuzhiyun #define TWL4030_HSR_GAIN_0DB 0x08 184*4882a593Smuzhiyun #define TWL4030_HSR_GAIN_MINUS_6DB 0x0C 185*4882a593Smuzhiyun #define TWL4030_HSL_GAIN 0x03 186*4882a593Smuzhiyun #define TWL4030_HSL_GAIN_PWR_DOWN 0x00 187*4882a593Smuzhiyun #define TWL4030_HSL_GAIN_PLUS_6DB 0x01 188*4882a593Smuzhiyun #define TWL4030_HSL_GAIN_0DB 0x02 189*4882a593Smuzhiyun #define TWL4030_HSL_GAIN_MINUS_6DB 0x03 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* HS_POPN_SET (0x24) Fields */ 192*4882a593Smuzhiyun #define TWL4030_VMID_EN 0x40 193*4882a593Smuzhiyun #define TWL4030_EXTMUTE 0x20 194*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY 0x1C 195*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_20MS 0x00 196*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_40MS 0x04 197*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_81MS 0x08 198*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_161MS 0x0C 199*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_323MS 0x10 200*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_645MS 0x14 201*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_1291MS 0x18 202*4882a593Smuzhiyun #define TWL4030_RAMP_DELAY_2581MS 0x1C 203*4882a593Smuzhiyun #define TWL4030_RAMP_EN 0x02 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* PREDL_CTL (0x25) */ 206*4882a593Smuzhiyun #define TWL4030_PREDL_GAIN 0x30 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* PREDR_CTL (0x26) */ 209*4882a593Smuzhiyun #define TWL4030_PREDR_GAIN 0x30 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* PRECKL_CTL (0x27) */ 212*4882a593Smuzhiyun #define TWL4030_PRECKL_GAIN 0x30 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* PRECKR_CTL (0x28) */ 215*4882a593Smuzhiyun #define TWL4030_PRECKR_GAIN 0x30 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* HFL_CTL (0x29, 0x2A) Fields */ 218*4882a593Smuzhiyun #define TWL4030_HF_CTL_HB_EN 0x04 219*4882a593Smuzhiyun #define TWL4030_HF_CTL_LOOP_EN 0x08 220*4882a593Smuzhiyun #define TWL4030_HF_CTL_RAMP_EN 0x10 221*4882a593Smuzhiyun #define TWL4030_HF_CTL_REF_EN 0x20 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* APLL_CTL (0x3A) Fields */ 224*4882a593Smuzhiyun #define TWL4030_APLL_EN 0x10 225*4882a593Smuzhiyun #define TWL4030_APLL_INFREQ 0x0F 226*4882a593Smuzhiyun #define TWL4030_APLL_INFREQ_19200KHZ 0x05 227*4882a593Smuzhiyun #define TWL4030_APLL_INFREQ_26000KHZ 0x06 228*4882a593Smuzhiyun #define TWL4030_APLL_INFREQ_38400KHZ 0x0F 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /* REG_MISC_SET_1 (0x3E) Fields */ 231*4882a593Smuzhiyun #define TWL4030_CLK64_EN 0x80 232*4882a593Smuzhiyun #define TWL4030_SCRAMBLE_EN 0x40 233*4882a593Smuzhiyun #define TWL4030_FMLOOP_EN 0x20 234*4882a593Smuzhiyun #define TWL4030_SMOOTH_ANAVOL_EN 0x02 235*4882a593Smuzhiyun #define TWL4030_DIGMIC_LR_SWAP_EN 0x01 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* VIBRA_CTL (0x45) */ 238*4882a593Smuzhiyun #define TWL4030_VIBRA_EN 0x01 239*4882a593Smuzhiyun #define TWL4030_VIBRA_DIR 0x02 240*4882a593Smuzhiyun #define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2) 241*4882a593Smuzhiyun #define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2) 242*4882a593Smuzhiyun #define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2) 243*4882a593Smuzhiyun #define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2) 244*4882a593Smuzhiyun #define TWL4030_VIBRA_SEL 0x10 245*4882a593Smuzhiyun #define TWL4030_VIBRA_DIR_SEL 0x20 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* TWL4030 codec resource IDs */ 248*4882a593Smuzhiyun enum twl4030_audio_res { 249*4882a593Smuzhiyun TWL4030_AUDIO_RES_POWER = 0, 250*4882a593Smuzhiyun TWL4030_AUDIO_RES_APLL, 251*4882a593Smuzhiyun TWL4030_AUDIO_RES_MAX, 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun int twl4030_audio_disable_resource(enum twl4030_audio_res id); 255*4882a593Smuzhiyun int twl4030_audio_enable_resource(enum twl4030_audio_res id); 256*4882a593Smuzhiyun unsigned int twl4030_audio_get_mclk(void); 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun #endif /* End of __TWL4030_CODEC_H__ */ 259