1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2017 Intel Corporation */ 3*4882a593Smuzhiyun /* Functions to access TPS68470 power management chip. */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __LINUX_MFD_TPS68470_H 6*4882a593Smuzhiyun #define __LINUX_MFD_TPS68470_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* Register addresses */ 9*4882a593Smuzhiyun #define TPS68470_REG_POSTDIV2 0x06 10*4882a593Smuzhiyun #define TPS68470_REG_BOOSTDIV 0x07 11*4882a593Smuzhiyun #define TPS68470_REG_BUCKDIV 0x08 12*4882a593Smuzhiyun #define TPS68470_REG_PLLSWR 0x09 13*4882a593Smuzhiyun #define TPS68470_REG_XTALDIV 0x0A 14*4882a593Smuzhiyun #define TPS68470_REG_PLLDIV 0x0B 15*4882a593Smuzhiyun #define TPS68470_REG_POSTDIV 0x0C 16*4882a593Smuzhiyun #define TPS68470_REG_PLLCTL 0x0D 17*4882a593Smuzhiyun #define TPS68470_REG_PLLCTL2 0x0E 18*4882a593Smuzhiyun #define TPS68470_REG_CLKCFG1 0x0F 19*4882a593Smuzhiyun #define TPS68470_REG_CLKCFG2 0x10 20*4882a593Smuzhiyun #define TPS68470_REG_GPCTL0A 0x14 21*4882a593Smuzhiyun #define TPS68470_REG_GPCTL0B 0x15 22*4882a593Smuzhiyun #define TPS68470_REG_GPCTL1A 0x16 23*4882a593Smuzhiyun #define TPS68470_REG_GPCTL1B 0x17 24*4882a593Smuzhiyun #define TPS68470_REG_GPCTL2A 0x18 25*4882a593Smuzhiyun #define TPS68470_REG_GPCTL2B 0x19 26*4882a593Smuzhiyun #define TPS68470_REG_GPCTL3A 0x1A 27*4882a593Smuzhiyun #define TPS68470_REG_GPCTL3B 0x1B 28*4882a593Smuzhiyun #define TPS68470_REG_GPCTL4A 0x1C 29*4882a593Smuzhiyun #define TPS68470_REG_GPCTL4B 0x1D 30*4882a593Smuzhiyun #define TPS68470_REG_GPCTL5A 0x1E 31*4882a593Smuzhiyun #define TPS68470_REG_GPCTL5B 0x1F 32*4882a593Smuzhiyun #define TPS68470_REG_GPCTL6A 0x20 33*4882a593Smuzhiyun #define TPS68470_REG_GPCTL6B 0x21 34*4882a593Smuzhiyun #define TPS68470_REG_SGPO 0x22 35*4882a593Smuzhiyun #define TPS68470_REG_GPDI 0x26 36*4882a593Smuzhiyun #define TPS68470_REG_GPDO 0x27 37*4882a593Smuzhiyun #define TPS68470_REG_VCMVAL 0x3C 38*4882a593Smuzhiyun #define TPS68470_REG_VAUX1VAL 0x3D 39*4882a593Smuzhiyun #define TPS68470_REG_VAUX2VAL 0x3E 40*4882a593Smuzhiyun #define TPS68470_REG_VIOVAL 0x3F 41*4882a593Smuzhiyun #define TPS68470_REG_VSIOVAL 0x40 42*4882a593Smuzhiyun #define TPS68470_REG_VAVAL 0x41 43*4882a593Smuzhiyun #define TPS68470_REG_VDVAL 0x42 44*4882a593Smuzhiyun #define TPS68470_REG_S_I2C_CTL 0x43 45*4882a593Smuzhiyun #define TPS68470_REG_VCMCTL 0x44 46*4882a593Smuzhiyun #define TPS68470_REG_VAUX1CTL 0x45 47*4882a593Smuzhiyun #define TPS68470_REG_VAUX2CTL 0x46 48*4882a593Smuzhiyun #define TPS68470_REG_VACTL 0x47 49*4882a593Smuzhiyun #define TPS68470_REG_VDCTL 0x48 50*4882a593Smuzhiyun #define TPS68470_REG_RESET 0x50 51*4882a593Smuzhiyun #define TPS68470_REG_REVID 0xFF 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define TPS68470_REG_MAX TPS68470_REG_REVID 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Register field definitions */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define TPS68470_REG_RESET_MASK GENMASK(7, 0) 58*4882a593Smuzhiyun #define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0) 61*4882a593Smuzhiyun #define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0) 62*4882a593Smuzhiyun #define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0) 63*4882a593Smuzhiyun #define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0) 64*4882a593Smuzhiyun #define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0) 65*4882a593Smuzhiyun #define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define TPS68470_VACTL_EN_MASK GENMASK(0, 0) 68*4882a593Smuzhiyun #define TPS68470_VDCTL_EN_MASK GENMASK(0, 0) 69*4882a593Smuzhiyun #define TPS68470_VCMCTL_EN_MASK GENMASK(0, 0) 70*4882a593Smuzhiyun #define TPS68470_S_I2C_CTL_EN_MASK GENMASK(1, 0) 71*4882a593Smuzhiyun #define TPS68470_VAUX1CTL_EN_MASK GENMASK(0, 0) 72*4882a593Smuzhiyun #define TPS68470_VAUX2CTL_EN_MASK GENMASK(0, 0) 73*4882a593Smuzhiyun #define TPS68470_PLL_EN_MASK GENMASK(0, 0) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define TPS68470_CLKCFG1_MODE_A_MASK GENMASK(1, 0) 76*4882a593Smuzhiyun #define TPS68470_CLKCFG1_MODE_B_MASK GENMASK(3, 2) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define TPS68470_GPIO_CTL_REG_A(x) (TPS68470_REG_GPCTL0A + (x) * 2) 79*4882a593Smuzhiyun #define TPS68470_GPIO_CTL_REG_B(x) (TPS68470_REG_GPCTL0B + (x) * 2) 80*4882a593Smuzhiyun #define TPS68470_GPIO_MODE_MASK GENMASK(1, 0) 81*4882a593Smuzhiyun #define TPS68470_GPIO_MODE_IN 0 82*4882a593Smuzhiyun #define TPS68470_GPIO_MODE_IN_PULLUP 1 83*4882a593Smuzhiyun #define TPS68470_GPIO_MODE_OUT_CMOS 2 84*4882a593Smuzhiyun #define TPS68470_GPIO_MODE_OUT_ODRAIN 3 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* __LINUX_MFD_TPS68470_H */ 87