1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * linux/mfd/tps65217.h
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Functions to access TPS65217 power management chip.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
9*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
10*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
14*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15*4882a593Smuzhiyun * GNU General Public License for more details.
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifndef __LINUX_MFD_TPS65217_H
19*4882a593Smuzhiyun #define __LINUX_MFD_TPS65217_H
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/i2c.h>
22*4882a593Smuzhiyun #include <linux/regulator/driver.h>
23*4882a593Smuzhiyun #include <linux/regulator/machine.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* TPS chip id list */
26*4882a593Smuzhiyun #define TPS65217 0xF0
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* I2C ID for TPS65217 part */
29*4882a593Smuzhiyun #define TPS65217_I2C_ID 0x24
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* All register addresses */
32*4882a593Smuzhiyun #define TPS65217_REG_CHIPID 0X00
33*4882a593Smuzhiyun #define TPS65217_REG_PPATH 0X01
34*4882a593Smuzhiyun #define TPS65217_REG_INT 0X02
35*4882a593Smuzhiyun #define TPS65217_REG_CHGCONFIG0 0X03
36*4882a593Smuzhiyun #define TPS65217_REG_CHGCONFIG1 0X04
37*4882a593Smuzhiyun #define TPS65217_REG_CHGCONFIG2 0X05
38*4882a593Smuzhiyun #define TPS65217_REG_CHGCONFIG3 0X06
39*4882a593Smuzhiyun #define TPS65217_REG_WLEDCTRL1 0X07
40*4882a593Smuzhiyun #define TPS65217_REG_WLEDCTRL2 0X08
41*4882a593Smuzhiyun #define TPS65217_REG_MUXCTRL 0X09
42*4882a593Smuzhiyun #define TPS65217_REG_STATUS 0X0A
43*4882a593Smuzhiyun #define TPS65217_REG_PASSWORD 0X0B
44*4882a593Smuzhiyun #define TPS65217_REG_PGOOD 0X0C
45*4882a593Smuzhiyun #define TPS65217_REG_DEFPG 0X0D
46*4882a593Smuzhiyun #define TPS65217_REG_DEFDCDC1 0X0E
47*4882a593Smuzhiyun #define TPS65217_REG_DEFDCDC2 0X0F
48*4882a593Smuzhiyun #define TPS65217_REG_DEFDCDC3 0X10
49*4882a593Smuzhiyun #define TPS65217_REG_DEFSLEW 0X11
50*4882a593Smuzhiyun #define TPS65217_REG_DEFLDO1 0X12
51*4882a593Smuzhiyun #define TPS65217_REG_DEFLDO2 0X13
52*4882a593Smuzhiyun #define TPS65217_REG_DEFLS1 0X14
53*4882a593Smuzhiyun #define TPS65217_REG_DEFLS2 0X15
54*4882a593Smuzhiyun #define TPS65217_REG_ENABLE 0X16
55*4882a593Smuzhiyun #define TPS65217_REG_DEFUVLO 0X18
56*4882a593Smuzhiyun #define TPS65217_REG_SEQ1 0X19
57*4882a593Smuzhiyun #define TPS65217_REG_SEQ2 0X1A
58*4882a593Smuzhiyun #define TPS65217_REG_SEQ3 0X1B
59*4882a593Smuzhiyun #define TPS65217_REG_SEQ4 0X1C
60*4882a593Smuzhiyun #define TPS65217_REG_SEQ5 0X1D
61*4882a593Smuzhiyun #define TPS65217_REG_SEQ6 0X1E
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define TPS65217_REG_MAX TPS65217_REG_SEQ6
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Register field definitions */
66*4882a593Smuzhiyun #define TPS65217_CHIPID_CHIP_MASK 0xF0
67*4882a593Smuzhiyun #define TPS65217_CHIPID_REV_MASK 0x0F
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
70*4882a593Smuzhiyun #define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
71*4882a593Smuzhiyun #define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
72*4882a593Smuzhiyun #define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
73*4882a593Smuzhiyun #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
74*4882a593Smuzhiyun #define TPS65217_PPATH_USB_CURRENT_MASK 0x03
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define TPS65217_INT_PBM BIT(6)
77*4882a593Smuzhiyun #define TPS65217_INT_ACM BIT(5)
78*4882a593Smuzhiyun #define TPS65217_INT_USBM BIT(4)
79*4882a593Smuzhiyun #define TPS65217_INT_PBI BIT(2)
80*4882a593Smuzhiyun #define TPS65217_INT_ACI BIT(1)
81*4882a593Smuzhiyun #define TPS65217_INT_USBI BIT(0)
82*4882a593Smuzhiyun #define TPS65217_INT_SHIFT 4
83*4882a593Smuzhiyun #define TPS65217_INT_MASK (TPS65217_INT_PBM | TPS65217_INT_ACM | \
84*4882a593Smuzhiyun TPS65217_INT_USBM)
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_TREG BIT(7)
87*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_DPPM BIT(6)
88*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_TSUSP BIT(5)
89*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_TERMI BIT(4)
90*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
91*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
92*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
93*4882a593Smuzhiyun #define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
96*4882a593Smuzhiyun #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
97*4882a593Smuzhiyun #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
98*4882a593Smuzhiyun #define TPS65217_CHGCONFIG1_RESET BIT(3)
99*4882a593Smuzhiyun #define TPS65217_CHGCONFIG1_TERM BIT(2)
100*4882a593Smuzhiyun #define TPS65217_CHGCONFIG1_SUSP BIT(1)
101*4882a593Smuzhiyun #define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
104*4882a593Smuzhiyun #define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
105*4882a593Smuzhiyun #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
108*4882a593Smuzhiyun #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
109*4882a593Smuzhiyun #define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
110*4882a593Smuzhiyun #define TPS65217_CHGCONFIG2_TERMIF 0x06
111*4882a593Smuzhiyun #define TPS65217_CHGCONFIG2_TRANGE BIT(0)
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
114*4882a593Smuzhiyun #define TPS65217_WLEDCTRL1_ISEL BIT(2)
115*4882a593Smuzhiyun #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define TPS65217_MUXCTRL_MUX_MASK 0x07
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define TPS65217_STATUS_OFF BIT(7)
122*4882a593Smuzhiyun #define TPS65217_STATUS_ACPWR BIT(3)
123*4882a593Smuzhiyun #define TPS65217_STATUS_USBPWR BIT(2)
124*4882a593Smuzhiyun #define TPS65217_STATUS_PB BIT(0)
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #define TPS65217_PGOOD_LDO3_PG BIT(6)
129*4882a593Smuzhiyun #define TPS65217_PGOOD_LDO4_PG BIT(5)
130*4882a593Smuzhiyun #define TPS65217_PGOOD_DC1_PG BIT(4)
131*4882a593Smuzhiyun #define TPS65217_PGOOD_DC2_PG BIT(3)
132*4882a593Smuzhiyun #define TPS65217_PGOOD_DC3_PG BIT(2)
133*4882a593Smuzhiyun #define TPS65217_PGOOD_LDO1_PG BIT(1)
134*4882a593Smuzhiyun #define TPS65217_PGOOD_LDO2_PG BIT(0)
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define TPS65217_DEFPG_LDO1PGM BIT(3)
137*4882a593Smuzhiyun #define TPS65217_DEFPG_LDO2PGM BIT(2)
138*4882a593Smuzhiyun #define TPS65217_DEFPG_PGDLY_MASK 0x03
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #define TPS65217_DEFDCDCX_XADJX BIT(7)
141*4882a593Smuzhiyun #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define TPS65217_DEFSLEW_GO BIT(7)
144*4882a593Smuzhiyun #define TPS65217_DEFSLEW_GODSBL BIT(6)
145*4882a593Smuzhiyun #define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
146*4882a593Smuzhiyun #define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
147*4882a593Smuzhiyun #define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
148*4882a593Smuzhiyun #define TPS65217_DEFSLEW_SLEW_MASK 0x07
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun #define TPS65217_DEFLDO1_LDO1_MASK 0x0F
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun #define TPS65217_DEFLDO2_TRACK BIT(6)
153*4882a593Smuzhiyun #define TPS65217_DEFLDO2_LDO2_MASK 0x3F
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #define TPS65217_DEFLDO3_LDO3_EN BIT(5)
156*4882a593Smuzhiyun #define TPS65217_DEFLDO3_LDO3_MASK 0x1F
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define TPS65217_DEFLDO4_LDO4_EN BIT(5)
159*4882a593Smuzhiyun #define TPS65217_DEFLDO4_LDO4_MASK 0x1F
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun #define TPS65217_ENABLE_LS1_EN BIT(6)
162*4882a593Smuzhiyun #define TPS65217_ENABLE_LS2_EN BIT(5)
163*4882a593Smuzhiyun #define TPS65217_ENABLE_DC1_EN BIT(4)
164*4882a593Smuzhiyun #define TPS65217_ENABLE_DC2_EN BIT(3)
165*4882a593Smuzhiyun #define TPS65217_ENABLE_DC3_EN BIT(2)
166*4882a593Smuzhiyun #define TPS65217_ENABLE_LDO1_EN BIT(1)
167*4882a593Smuzhiyun #define TPS65217_ENABLE_LDO2_EN BIT(0)
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun #define TPS65217_DEFUVLO_UVLOHYS BIT(2)
170*4882a593Smuzhiyun #define TPS65217_DEFUVLO_UVLO_MASK 0x03
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
173*4882a593Smuzhiyun #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
176*4882a593Smuzhiyun #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
179*4882a593Smuzhiyun #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #define TPS65217_SEQ5_DLY1_MASK 0xC0
184*4882a593Smuzhiyun #define TPS65217_SEQ5_DLY2_MASK 0x30
185*4882a593Smuzhiyun #define TPS65217_SEQ5_DLY3_MASK 0x0C
186*4882a593Smuzhiyun #define TPS65217_SEQ5_DLY4_MASK 0x03
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun #define TPS65217_SEQ6_DLY5_MASK 0xC0
189*4882a593Smuzhiyun #define TPS65217_SEQ6_DLY6_MASK 0x30
190*4882a593Smuzhiyun #define TPS65217_SEQ6_SEQUP BIT(2)
191*4882a593Smuzhiyun #define TPS65217_SEQ6_SEQDWN BIT(1)
192*4882a593Smuzhiyun #define TPS65217_SEQ6_INSTDWN BIT(0)
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun #define TPS65217_MAX_REGISTER 0x1E
195*4882a593Smuzhiyun #define TPS65217_PROTECT_NONE 0
196*4882a593Smuzhiyun #define TPS65217_PROTECT_L1 1
197*4882a593Smuzhiyun #define TPS65217_PROTECT_L2 2
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun enum tps65217_regulator_id {
201*4882a593Smuzhiyun /* DCDC's */
202*4882a593Smuzhiyun TPS65217_DCDC_1,
203*4882a593Smuzhiyun TPS65217_DCDC_2,
204*4882a593Smuzhiyun TPS65217_DCDC_3,
205*4882a593Smuzhiyun /* LDOs */
206*4882a593Smuzhiyun TPS65217_LDO_1,
207*4882a593Smuzhiyun TPS65217_LDO_2,
208*4882a593Smuzhiyun TPS65217_LDO_3,
209*4882a593Smuzhiyun TPS65217_LDO_4,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun #define TPS65217_MAX_REG_ID TPS65217_LDO_4
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* Number of step-down converters available */
215*4882a593Smuzhiyun #define TPS65217_NUM_DCDC 3
216*4882a593Smuzhiyun /* Number of LDO voltage regulators available */
217*4882a593Smuzhiyun #define TPS65217_NUM_LDO 4
218*4882a593Smuzhiyun /* Number of total regulators available */
219*4882a593Smuzhiyun #define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun enum tps65217_bl_isel {
222*4882a593Smuzhiyun TPS65217_BL_ISET1 = 1,
223*4882a593Smuzhiyun TPS65217_BL_ISET2,
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun enum tps65217_bl_fdim {
227*4882a593Smuzhiyun TPS65217_BL_FDIM_100HZ,
228*4882a593Smuzhiyun TPS65217_BL_FDIM_200HZ,
229*4882a593Smuzhiyun TPS65217_BL_FDIM_500HZ,
230*4882a593Smuzhiyun TPS65217_BL_FDIM_1000HZ,
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun struct tps65217_bl_pdata {
234*4882a593Smuzhiyun enum tps65217_bl_isel isel;
235*4882a593Smuzhiyun enum tps65217_bl_fdim fdim;
236*4882a593Smuzhiyun int dft_brightness;
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* Interrupt numbers */
240*4882a593Smuzhiyun #define TPS65217_IRQ_USB 0
241*4882a593Smuzhiyun #define TPS65217_IRQ_AC 1
242*4882a593Smuzhiyun #define TPS65217_IRQ_PB 2
243*4882a593Smuzhiyun #define TPS65217_NUM_IRQ 3
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /**
246*4882a593Smuzhiyun * struct tps65217_board - packages regulator init data
247*4882a593Smuzhiyun * @tps65217_regulator_data: regulator initialization values
248*4882a593Smuzhiyun *
249*4882a593Smuzhiyun * Board data may be used to initialize regulator.
250*4882a593Smuzhiyun */
251*4882a593Smuzhiyun struct tps65217_board {
252*4882a593Smuzhiyun struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
253*4882a593Smuzhiyun struct device_node *of_node[TPS65217_NUM_REGULATOR];
254*4882a593Smuzhiyun struct tps65217_bl_pdata *bl_pdata;
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /**
258*4882a593Smuzhiyun * struct tps65217 - tps65217 sub-driver chip access routines
259*4882a593Smuzhiyun *
260*4882a593Smuzhiyun * Device data may be used to access the TPS65217 chip
261*4882a593Smuzhiyun */
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun struct tps65217 {
264*4882a593Smuzhiyun struct device *dev;
265*4882a593Smuzhiyun struct tps65217_board *pdata;
266*4882a593Smuzhiyun struct regulator_desc desc[TPS65217_NUM_REGULATOR];
267*4882a593Smuzhiyun struct regmap *regmap;
268*4882a593Smuzhiyun u8 *strobes;
269*4882a593Smuzhiyun struct irq_domain *irq_domain;
270*4882a593Smuzhiyun struct mutex irq_lock;
271*4882a593Smuzhiyun u8 irq_mask;
272*4882a593Smuzhiyun int irq;
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
dev_to_tps65217(struct device * dev)275*4882a593Smuzhiyun static inline struct tps65217 *dev_to_tps65217(struct device *dev)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun return dev_get_drvdata(dev);
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
281*4882a593Smuzhiyun unsigned int *val);
282*4882a593Smuzhiyun int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
283*4882a593Smuzhiyun unsigned int val, unsigned int level);
284*4882a593Smuzhiyun int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
285*4882a593Smuzhiyun unsigned int mask, unsigned int val, unsigned int level);
286*4882a593Smuzhiyun int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
287*4882a593Smuzhiyun unsigned int mask, unsigned int level);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun #endif /* __LINUX_MFD_TPS65217_H */
290