1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Core driver interface for TI TPS65090 PMIC family
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012 NVIDIA Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef __LINUX_MFD_TPS65090_H
9*4882a593Smuzhiyun #define __LINUX_MFD_TPS65090_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* TPS65090 IRQs */
15*4882a593Smuzhiyun enum {
16*4882a593Smuzhiyun TPS65090_IRQ_INTERRUPT,
17*4882a593Smuzhiyun TPS65090_IRQ_VAC_STATUS_CHANGE,
18*4882a593Smuzhiyun TPS65090_IRQ_VSYS_STATUS_CHANGE,
19*4882a593Smuzhiyun TPS65090_IRQ_BAT_STATUS_CHANGE,
20*4882a593Smuzhiyun TPS65090_IRQ_CHARGING_STATUS_CHANGE,
21*4882a593Smuzhiyun TPS65090_IRQ_CHARGING_COMPLETE,
22*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_DCDC1,
23*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_DCDC2,
24*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_DCDC3,
25*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_FET1,
26*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_FET2,
27*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_FET3,
28*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_FET4,
29*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_FET5,
30*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_FET6,
31*4882a593Smuzhiyun TPS65090_IRQ_OVERLOAD_FET7,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* TPS65090 Regulator ID */
35*4882a593Smuzhiyun enum {
36*4882a593Smuzhiyun TPS65090_REGULATOR_DCDC1,
37*4882a593Smuzhiyun TPS65090_REGULATOR_DCDC2,
38*4882a593Smuzhiyun TPS65090_REGULATOR_DCDC3,
39*4882a593Smuzhiyun TPS65090_REGULATOR_FET1,
40*4882a593Smuzhiyun TPS65090_REGULATOR_FET2,
41*4882a593Smuzhiyun TPS65090_REGULATOR_FET3,
42*4882a593Smuzhiyun TPS65090_REGULATOR_FET4,
43*4882a593Smuzhiyun TPS65090_REGULATOR_FET5,
44*4882a593Smuzhiyun TPS65090_REGULATOR_FET6,
45*4882a593Smuzhiyun TPS65090_REGULATOR_FET7,
46*4882a593Smuzhiyun TPS65090_REGULATOR_LDO1,
47*4882a593Smuzhiyun TPS65090_REGULATOR_LDO2,
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Last entry for maximum ID */
50*4882a593Smuzhiyun TPS65090_REGULATOR_MAX,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Register addresses */
54*4882a593Smuzhiyun #define TPS65090_REG_INTR_STS 0x00
55*4882a593Smuzhiyun #define TPS65090_REG_INTR_STS2 0x01
56*4882a593Smuzhiyun #define TPS65090_REG_INTR_MASK 0x02
57*4882a593Smuzhiyun #define TPS65090_REG_INTR_MASK2 0x03
58*4882a593Smuzhiyun #define TPS65090_REG_CG_CTRL0 0x04
59*4882a593Smuzhiyun #define TPS65090_REG_CG_CTRL1 0x05
60*4882a593Smuzhiyun #define TPS65090_REG_CG_CTRL2 0x06
61*4882a593Smuzhiyun #define TPS65090_REG_CG_CTRL3 0x07
62*4882a593Smuzhiyun #define TPS65090_REG_CG_CTRL4 0x08
63*4882a593Smuzhiyun #define TPS65090_REG_CG_CTRL5 0x09
64*4882a593Smuzhiyun #define TPS65090_REG_CG_STATUS1 0x0a
65*4882a593Smuzhiyun #define TPS65090_REG_CG_STATUS2 0x0b
66*4882a593Smuzhiyun #define TPS65090_REG_AD_OUT1 0x17
67*4882a593Smuzhiyun #define TPS65090_REG_AD_OUT2 0x18
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define TPS65090_MAX_REG TPS65090_REG_AD_OUT2
70*4882a593Smuzhiyun #define TPS65090_NUM_REGS (TPS65090_MAX_REG + 1)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct gpio_desc;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct tps65090 {
75*4882a593Smuzhiyun struct device *dev;
76*4882a593Smuzhiyun struct regmap *rmap;
77*4882a593Smuzhiyun struct regmap_irq_chip_data *irq_data;
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * struct tps65090_regulator_plat_data
82*4882a593Smuzhiyun *
83*4882a593Smuzhiyun * @reg_init_data: The regulator init data.
84*4882a593Smuzhiyun * @enable_ext_control: Enable extrenal control or not. Only available for
85*4882a593Smuzhiyun * DCDC1, DCDC2 and DCDC3.
86*4882a593Smuzhiyun * @gpiod: Gpio descriptor if external control is enabled and controlled through
87*4882a593Smuzhiyun * gpio
88*4882a593Smuzhiyun * @overcurrent_wait_valid: True if the overcurrent_wait should be applied.
89*4882a593Smuzhiyun * @overcurrent_wait: Value to set as the overcurrent wait time. This is the
90*4882a593Smuzhiyun * actual bitfield value, not a time in ms (valid value are 0 - 3).
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun struct tps65090_regulator_plat_data {
93*4882a593Smuzhiyun struct regulator_init_data *reg_init_data;
94*4882a593Smuzhiyun bool enable_ext_control;
95*4882a593Smuzhiyun struct gpio_desc *gpiod;
96*4882a593Smuzhiyun bool overcurrent_wait_valid;
97*4882a593Smuzhiyun int overcurrent_wait;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct tps65090_platform_data {
101*4882a593Smuzhiyun int irq_base;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun char **supplied_to;
104*4882a593Smuzhiyun size_t num_supplicants;
105*4882a593Smuzhiyun int enable_low_current_chrg;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX];
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun * NOTE: the functions below are not intended for use outside
112*4882a593Smuzhiyun * of the TPS65090 sub-device drivers
113*4882a593Smuzhiyun */
tps65090_write(struct device * dev,int reg,uint8_t val)114*4882a593Smuzhiyun static inline int tps65090_write(struct device *dev, int reg, uint8_t val)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct tps65090 *tps = dev_get_drvdata(dev);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return regmap_write(tps->rmap, reg, val);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
tps65090_read(struct device * dev,int reg,uint8_t * val)121*4882a593Smuzhiyun static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct tps65090 *tps = dev_get_drvdata(dev);
124*4882a593Smuzhiyun unsigned int temp_val;
125*4882a593Smuzhiyun int ret;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = regmap_read(tps->rmap, reg, &temp_val);
128*4882a593Smuzhiyun if (!ret)
129*4882a593Smuzhiyun *val = temp_val;
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
tps65090_set_bits(struct device * dev,int reg,uint8_t bit_num)133*4882a593Smuzhiyun static inline int tps65090_set_bits(struct device *dev, int reg,
134*4882a593Smuzhiyun uint8_t bit_num)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun struct tps65090 *tps = dev_get_drvdata(dev);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
tps65090_clr_bits(struct device * dev,int reg,uint8_t bit_num)141*4882a593Smuzhiyun static inline int tps65090_clr_bits(struct device *dev, int reg,
142*4882a593Smuzhiyun uint8_t bit_num)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun struct tps65090 *tps = dev_get_drvdata(dev);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun #endif /*__LINUX_MFD_TPS65090_H */
150