1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/ 3*4882a593Smuzhiyun * Andrew F. Davis <afd@ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 6*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License version 2 as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10*4882a593Smuzhiyun * kind, whether expressed or implied; without even the implied warranty 11*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*4882a593Smuzhiyun * GNU General Public License version 2 for more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Based on the TPS65912 driver 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __LINUX_MFD_TPS65086_H 18*4882a593Smuzhiyun #define __LINUX_MFD_TPS65086_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <linux/device.h> 21*4882a593Smuzhiyun #include <linux/regmap.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* List of registers for TPS65086 */ 24*4882a593Smuzhiyun #define TPS65086_DEVICEID 0x01 25*4882a593Smuzhiyun #define TPS65086_IRQ 0x02 26*4882a593Smuzhiyun #define TPS65086_IRQ_MASK 0x03 27*4882a593Smuzhiyun #define TPS65086_PMICSTAT 0x04 28*4882a593Smuzhiyun #define TPS65086_SHUTDNSRC 0x05 29*4882a593Smuzhiyun #define TPS65086_BUCK1CTRL 0x20 30*4882a593Smuzhiyun #define TPS65086_BUCK2CTRL 0x21 31*4882a593Smuzhiyun #define TPS65086_BUCK3DECAY 0x22 32*4882a593Smuzhiyun #define TPS65086_BUCK3VID 0x23 33*4882a593Smuzhiyun #define TPS65086_BUCK3SLPCTRL 0x24 34*4882a593Smuzhiyun #define TPS65086_BUCK4CTRL 0x25 35*4882a593Smuzhiyun #define TPS65086_BUCK5CTRL 0x26 36*4882a593Smuzhiyun #define TPS65086_BUCK6CTRL 0x27 37*4882a593Smuzhiyun #define TPS65086_LDOA2CTRL 0x28 38*4882a593Smuzhiyun #define TPS65086_LDOA3CTRL 0x29 39*4882a593Smuzhiyun #define TPS65086_DISCHCTRL1 0x40 40*4882a593Smuzhiyun #define TPS65086_DISCHCTRL2 0x41 41*4882a593Smuzhiyun #define TPS65086_DISCHCTRL3 0x42 42*4882a593Smuzhiyun #define TPS65086_PG_DELAY1 0x43 43*4882a593Smuzhiyun #define TPS65086_FORCESHUTDN 0x91 44*4882a593Smuzhiyun #define TPS65086_BUCK1SLPCTRL 0x92 45*4882a593Smuzhiyun #define TPS65086_BUCK2SLPCTRL 0x93 46*4882a593Smuzhiyun #define TPS65086_BUCK4VID 0x94 47*4882a593Smuzhiyun #define TPS65086_BUCK4SLPVID 0x95 48*4882a593Smuzhiyun #define TPS65086_BUCK5VID 0x96 49*4882a593Smuzhiyun #define TPS65086_BUCK5SLPVID 0x97 50*4882a593Smuzhiyun #define TPS65086_BUCK6VID 0x98 51*4882a593Smuzhiyun #define TPS65086_BUCK6SLPVID 0x99 52*4882a593Smuzhiyun #define TPS65086_LDOA2VID 0x9A 53*4882a593Smuzhiyun #define TPS65086_LDOA3VID 0x9B 54*4882a593Smuzhiyun #define TPS65086_BUCK123CTRL 0x9C 55*4882a593Smuzhiyun #define TPS65086_PG_DELAY2 0x9D 56*4882a593Smuzhiyun #define TPS65086_PIN_EN_MASK1 0x9E 57*4882a593Smuzhiyun #define TPS65086_PIN_EN_MASK2 0x9F 58*4882a593Smuzhiyun #define TPS65086_SWVTT_EN 0x9F 59*4882a593Smuzhiyun #define TPS65086_PIN_EN_OVR1 0xA0 60*4882a593Smuzhiyun #define TPS65086_PIN_EN_OVR2 0xA1 61*4882a593Smuzhiyun #define TPS65086_GPOCTRL 0xA1 62*4882a593Smuzhiyun #define TPS65086_PWR_FAULT_MASK1 0xA2 63*4882a593Smuzhiyun #define TPS65086_PWR_FAULT_MASK2 0xA3 64*4882a593Smuzhiyun #define TPS65086_GPO1PG_CTRL1 0xA4 65*4882a593Smuzhiyun #define TPS65086_GPO1PG_CTRL2 0xA5 66*4882a593Smuzhiyun #define TPS65086_GPO4PG_CTRL1 0xA6 67*4882a593Smuzhiyun #define TPS65086_GPO4PG_CTRL2 0xA7 68*4882a593Smuzhiyun #define TPS65086_GPO2PG_CTRL1 0xA8 69*4882a593Smuzhiyun #define TPS65086_GPO2PG_CTRL2 0xA9 70*4882a593Smuzhiyun #define TPS65086_GPO3PG_CTRL1 0xAA 71*4882a593Smuzhiyun #define TPS65086_GPO3PG_CTRL2 0xAB 72*4882a593Smuzhiyun #define TPS65086_LDOA1CTRL 0xAE 73*4882a593Smuzhiyun #define TPS65086_PG_STATUS1 0xB0 74*4882a593Smuzhiyun #define TPS65086_PG_STATUS2 0xB1 75*4882a593Smuzhiyun #define TPS65086_PWR_FAULT_STATUS1 0xB2 76*4882a593Smuzhiyun #define TPS65086_PWR_FAULT_STATUS2 0xB3 77*4882a593Smuzhiyun #define TPS65086_TEMPCRIT 0xB4 78*4882a593Smuzhiyun #define TPS65086_TEMPHOT 0xB5 79*4882a593Smuzhiyun #define TPS65086_OC_STATUS 0xB6 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* IRQ Register field definitions */ 82*4882a593Smuzhiyun #define TPS65086_IRQ_DIETEMP_MASK BIT(0) 83*4882a593Smuzhiyun #define TPS65086_IRQ_SHUTDN_MASK BIT(3) 84*4882a593Smuzhiyun #define TPS65086_IRQ_FAULT_MASK BIT(7) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* DEVICEID Register field definitions */ 87*4882a593Smuzhiyun #define TPS65086_DEVICEID_PART_MASK GENMASK(3, 0) 88*4882a593Smuzhiyun #define TPS65086_DEVICEID_OTP_MASK GENMASK(5, 4) 89*4882a593Smuzhiyun #define TPS65086_DEVICEID_REV_MASK GENMASK(7, 6) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* VID Masks */ 92*4882a593Smuzhiyun #define BUCK_VID_MASK GENMASK(7, 1) 93*4882a593Smuzhiyun #define VDOA1_VID_MASK GENMASK(4, 1) 94*4882a593Smuzhiyun #define VDOA23_VID_MASK GENMASK(3, 0) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Define the TPS65086 IRQ numbers */ 97*4882a593Smuzhiyun enum tps65086_irqs { 98*4882a593Smuzhiyun TPS65086_IRQ_DIETEMP, 99*4882a593Smuzhiyun TPS65086_IRQ_SHUTDN, 100*4882a593Smuzhiyun TPS65086_IRQ_FAULT, 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /** 104*4882a593Smuzhiyun * struct tps65086 - state holder for the tps65086 driver 105*4882a593Smuzhiyun * 106*4882a593Smuzhiyun * Device data may be used to access the TPS65086 chip 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun struct tps65086 { 109*4882a593Smuzhiyun struct device *dev; 110*4882a593Smuzhiyun struct regmap *regmap; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* IRQ Data */ 113*4882a593Smuzhiyun int irq; 114*4882a593Smuzhiyun struct regmap_irq_chip_data *irq_data; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif /* __LINUX_MFD_TPS65086_H */ 118