1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef MFD_TMIO_H 3*4882a593Smuzhiyun #define MFD_TMIO_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/device.h> 6*4882a593Smuzhiyun #include <linux/fb.h> 7*4882a593Smuzhiyun #include <linux/io.h> 8*4882a593Smuzhiyun #include <linux/jiffies.h> 9*4882a593Smuzhiyun #include <linux/mmc/card.h> 10*4882a593Smuzhiyun #include <linux/platform_device.h> 11*4882a593Smuzhiyun #include <linux/pm_runtime.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define tmio_ioread8(addr) readb(addr) 14*4882a593Smuzhiyun #define tmio_ioread16(addr) readw(addr) 15*4882a593Smuzhiyun #define tmio_ioread16_rep(r, b, l) readsw(r, b, l) 16*4882a593Smuzhiyun #define tmio_ioread32(addr) \ 17*4882a593Smuzhiyun (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16)) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define tmio_iowrite8(val, addr) writeb((val), (addr)) 20*4882a593Smuzhiyun #define tmio_iowrite16(val, addr) writew((val), (addr)) 21*4882a593Smuzhiyun #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l) 22*4882a593Smuzhiyun #define tmio_iowrite32(val, addr) \ 23*4882a593Smuzhiyun do { \ 24*4882a593Smuzhiyun writew((val), (addr)); \ 25*4882a593Smuzhiyun writew((val) >> 16, (addr) + 2); \ 26*4882a593Smuzhiyun } while (0) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define sd_config_write8(base, shift, reg, val) \ 29*4882a593Smuzhiyun tmio_iowrite8((val), (base) + ((reg) << (shift))) 30*4882a593Smuzhiyun #define sd_config_write16(base, shift, reg, val) \ 31*4882a593Smuzhiyun tmio_iowrite16((val), (base) + ((reg) << (shift))) 32*4882a593Smuzhiyun #define sd_config_write32(base, shift, reg, val) \ 33*4882a593Smuzhiyun do { \ 34*4882a593Smuzhiyun tmio_iowrite16((val), (base) + ((reg) << (shift))); \ 35*4882a593Smuzhiyun tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ 36*4882a593Smuzhiyun } while (0) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* tmio MMC platform flags */ 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * Some controllers can support a 2-byte block size when the bus width 41*4882a593Smuzhiyun * is configured in 4-bit mode. 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define TMIO_MMC_BLKSZ_2BYTES BIT(1) 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * Some controllers can support SDIO IRQ signalling. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define TMIO_MMC_SDIO_IRQ BIT(2) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Some features are only available or tested on R-Car Gen2 or later */ 50*4882a593Smuzhiyun #define TMIO_MMC_MIN_RCAR2 BIT(3) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * Some controllers require waiting for the SD bus to become 54*4882a593Smuzhiyun * idle before writing to some registers. 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun #define TMIO_MMC_HAS_IDLE_WAIT BIT(4) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* BIT(5) is unused */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Some controllers have CMD12 automatically 62*4882a593Smuzhiyun * issue/non-issue register 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun #define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Controller has some SDIO status bits which must be 1 */ 67*4882a593Smuzhiyun #define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * Some controllers have a 32-bit wide data port register 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun #define TMIO_MMC_32BIT_DATA_PORT BIT(9) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * Some controllers allows to set SDx actual clock 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun #define TMIO_MMC_CLK_ACTUAL BIT(10) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Some controllers have a CBSY bit */ 80*4882a593Smuzhiyun #define TMIO_MMC_HAVE_CBSY BIT(11) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 83*4882a593Smuzhiyun int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 84*4882a593Smuzhiyun void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); 85*4882a593Smuzhiyun void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct dma_chan; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * data for the MMC controller 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun struct tmio_mmc_data { 93*4882a593Smuzhiyun void *chan_priv_tx; 94*4882a593Smuzhiyun void *chan_priv_rx; 95*4882a593Smuzhiyun unsigned int hclk; 96*4882a593Smuzhiyun unsigned long capabilities; 97*4882a593Smuzhiyun unsigned long capabilities2; 98*4882a593Smuzhiyun unsigned long flags; 99*4882a593Smuzhiyun u32 ocr_mask; /* available voltages */ 100*4882a593Smuzhiyun int alignment_shift; 101*4882a593Smuzhiyun dma_addr_t dma_rx_offset; 102*4882a593Smuzhiyun unsigned int max_blk_count; 103*4882a593Smuzhiyun unsigned short max_segs; 104*4882a593Smuzhiyun void (*set_pwr)(struct platform_device *host, int state); 105*4882a593Smuzhiyun void (*set_clk_div)(struct platform_device *host, int state); 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * data for the NAND controller 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun struct tmio_nand_data { 112*4882a593Smuzhiyun struct nand_bbt_descr *badblock_pattern; 113*4882a593Smuzhiyun struct mtd_partition *partition; 114*4882a593Smuzhiyun unsigned int num_partitions; 115*4882a593Smuzhiyun const char *const *part_parsers; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define FBIO_TMIO_ACC_WRITE 0x7C639300 119*4882a593Smuzhiyun #define FBIO_TMIO_ACC_SYNC 0x7C639301 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun struct tmio_fb_data { 122*4882a593Smuzhiyun int (*lcd_set_power)(struct platform_device *fb_dev, 123*4882a593Smuzhiyun bool on); 124*4882a593Smuzhiyun int (*lcd_mode)(struct platform_device *fb_dev, 125*4882a593Smuzhiyun const struct fb_videomode *mode); 126*4882a593Smuzhiyun int num_modes; 127*4882a593Smuzhiyun struct fb_videomode *modes; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* in mm: size of screen */ 130*4882a593Smuzhiyun int height; 131*4882a593Smuzhiyun int width; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif 135