1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __LINUX_IMX7_IOMUXC_GPR_H 7*4882a593Smuzhiyun #define __LINUX_IMX7_IOMUXC_GPR_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IOMUXC_GPR0 0x00 10*4882a593Smuzhiyun #define IOMUXC_GPR1 0x04 11*4882a593Smuzhiyun #define IOMUXC_GPR2 0x08 12*4882a593Smuzhiyun #define IOMUXC_GPR3 0x0c 13*4882a593Smuzhiyun #define IOMUXC_GPR4 0x10 14*4882a593Smuzhiyun #define IOMUXC_GPR5 0x14 15*4882a593Smuzhiyun #define IOMUXC_GPR6 0x18 16*4882a593Smuzhiyun #define IOMUXC_GPR7 0x1c 17*4882a593Smuzhiyun #define IOMUXC_GPR8 0x20 18*4882a593Smuzhiyun #define IOMUXC_GPR9 0x24 19*4882a593Smuzhiyun #define IOMUXC_GPR10 0x28 20*4882a593Smuzhiyun #define IOMUXC_GPR11 0x2c 21*4882a593Smuzhiyun #define IOMUXC_GPR12 0x30 22*4882a593Smuzhiyun #define IOMUXC_GPR13 0x34 23*4882a593Smuzhiyun #define IOMUXC_GPR14 0x38 24*4882a593Smuzhiyun #define IOMUXC_GPR15 0x3c 25*4882a593Smuzhiyun #define IOMUXC_GPR16 0x40 26*4882a593Smuzhiyun #define IOMUXC_GPR17 0x44 27*4882a593Smuzhiyun #define IOMUXC_GPR18 0x48 28*4882a593Smuzhiyun #define IOMUXC_GPR19 0x4c 29*4882a593Smuzhiyun #define IOMUXC_GPR20 0x50 30*4882a593Smuzhiyun #define IOMUXC_GPR21 0x54 31*4882a593Smuzhiyun #define IOMUXC_GPR22 0x58 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* For imx7d iomux gpr register field define */ 34*4882a593Smuzhiyun #define IMX7D_GPR1_IRQ_MASK (0x1 << 12) 35*4882a593Smuzhiyun #define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13) 36*4882a593Smuzhiyun #define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14) 37*4882a593Smuzhiyun #define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13) 38*4882a593Smuzhiyun #define IMX7D_GPR1_ENET1_CLK_DIR_MASK (0x1 << 17) 39*4882a593Smuzhiyun #define IMX7D_GPR1_ENET2_CLK_DIR_MASK (0x1 << 18) 40*4882a593Smuzhiyun #define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __LINUX_IMX7_IOMUXC_GPR_H */ 49