1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2005 Ivan Kokshaysky 4*4882a593Smuzhiyun * Copyright (C) SAN People 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * System Timer (ST) - System peripherals registers. 7*4882a593Smuzhiyun * Based on AT91RM9200 datasheet revision E. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _LINUX_MFD_SYSCON_ATMEL_ST_H 11*4882a593Smuzhiyun #define _LINUX_MFD_SYSCON_ATMEL_ST_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/bitops.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define AT91_ST_CR 0x00 /* Control Register */ 16*4882a593Smuzhiyun #define AT91_ST_WDRST BIT(0) /* Watchdog Timer Restart */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */ 19*4882a593Smuzhiyun #define AT91_ST_PIV 0xffff /* Period Interval Value */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */ 22*4882a593Smuzhiyun #define AT91_ST_WDV 0xffff /* Watchdog Counter Value */ 23*4882a593Smuzhiyun #define AT91_ST_RSTEN BIT(16) /* Reset Enable */ 24*4882a593Smuzhiyun #define AT91_ST_EXTEN BIT(17) /* External Signal Assertion Enable */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define AT91_ST_RTMR 0x0c /* Real-time Mode Register */ 27*4882a593Smuzhiyun #define AT91_ST_RTPRES 0xffff /* Real-time Prescalar Value */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define AT91_ST_SR 0x10 /* Status Register */ 30*4882a593Smuzhiyun #define AT91_ST_PITS BIT(0) /* Period Interval Timer Status */ 31*4882a593Smuzhiyun #define AT91_ST_WDOVF BIT(1) /* Watchdog Overflow */ 32*4882a593Smuzhiyun #define AT91_ST_RTTINC BIT(2) /* Real-time Timer Increment */ 33*4882a593Smuzhiyun #define AT91_ST_ALMS BIT(3) /* Alarm Status */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define AT91_ST_IER 0x14 /* Interrupt Enable Register */ 36*4882a593Smuzhiyun #define AT91_ST_IDR 0x18 /* Interrupt Disable Register */ 37*4882a593Smuzhiyun #define AT91_ST_IMR 0x1c /* Interrupt Mask Register */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */ 40*4882a593Smuzhiyun #define AT91_ST_ALMV 0xfffff /* Alarm Value */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AT91_ST_CRTR 0x24 /* Current Real-time Register */ 43*4882a593Smuzhiyun #define AT91_ST_CRTV 0xfffff /* Current Real-Time Value */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /* _LINUX_MFD_SYSCON_ATMEL_ST_H */ 46