1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2005 Ivan Kokshaysky 4*4882a593Smuzhiyun * Copyright (C) SAN People 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals 7*4882a593Smuzhiyun * registers. 8*4882a593Smuzhiyun * Based on AT91RM9200 datasheet revision E. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_ 12*4882a593Smuzhiyun #define _LINUX_MFD_SYSCON_ATMEL_MC_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Memory Controller */ 15*4882a593Smuzhiyun #define AT91_MC_RCR 0x00 16*4882a593Smuzhiyun #define AT91_MC_RCB BIT(0) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define AT91_MC_ASR 0x04 19*4882a593Smuzhiyun #define AT91_MC_UNADD BIT(0) 20*4882a593Smuzhiyun #define AT91_MC_MISADD BIT(1) 21*4882a593Smuzhiyun #define AT91_MC_ABTSZ GENMASK(9, 8) 22*4882a593Smuzhiyun #define AT91_MC_ABTSZ_BYTE (0 << 8) 23*4882a593Smuzhiyun #define AT91_MC_ABTSZ_HALFWORD (1 << 8) 24*4882a593Smuzhiyun #define AT91_MC_ABTSZ_WORD (2 << 8) 25*4882a593Smuzhiyun #define AT91_MC_ABTTYP GENMASK(11, 10) 26*4882a593Smuzhiyun #define AT91_MC_ABTTYP_DATAREAD (0 << 10) 27*4882a593Smuzhiyun #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) 28*4882a593Smuzhiyun #define AT91_MC_ABTTYP_FETCH (2 << 10) 29*4882a593Smuzhiyun #define AT91_MC_MST(n) BIT(16 + (n)) 30*4882a593Smuzhiyun #define AT91_MC_SVMST(n) BIT(24 + (n)) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define AT91_MC_AASR 0x08 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AT91_MC_MPR 0x0c 35*4882a593Smuzhiyun #define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4)) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* External Bus Interface (EBI) registers */ 38*4882a593Smuzhiyun #define AT91_MC_EBI_CSA 0x60 39*4882a593Smuzhiyun #define AT91_MC_EBI_CS(n) BIT(x) 40*4882a593Smuzhiyun #define AT91_MC_EBI_NUM_CS 8 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AT91_MC_EBI_CFGR 0x64 43*4882a593Smuzhiyun #define AT91_MC_EBI_DBPUC BIT(0) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Static Memory Controller (SMC) registers */ 46*4882a593Smuzhiyun #define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4)) 47*4882a593Smuzhiyun #define AT91_MC_SMC_NWS GENMASK(6, 0) 48*4882a593Smuzhiyun #define AT91_MC_SMC_NWS_(x) ((x) << 0) 49*4882a593Smuzhiyun #define AT91_MC_SMC_WSEN BIT(7) 50*4882a593Smuzhiyun #define AT91_MC_SMC_TDF GENMASK(11, 8) 51*4882a593Smuzhiyun #define AT91_MC_SMC_TDF_(x) ((x) << 8) 52*4882a593Smuzhiyun #define AT91_MC_SMC_TDF_MAX 0xf 53*4882a593Smuzhiyun #define AT91_MC_SMC_BAT BIT(12) 54*4882a593Smuzhiyun #define AT91_MC_SMC_DBW GENMASK(14, 13) 55*4882a593Smuzhiyun #define AT91_MC_SMC_DBW_16 (1 << 13) 56*4882a593Smuzhiyun #define AT91_MC_SMC_DBW_8 (2 << 13) 57*4882a593Smuzhiyun #define AT91_MC_SMC_DPR BIT(15) 58*4882a593Smuzhiyun #define AT91_MC_SMC_ACSS GENMASK(17, 16) 59*4882a593Smuzhiyun #define AT91_MC_SMC_ACSS_(x) ((x) << 16) 60*4882a593Smuzhiyun #define AT91_MC_SMC_ACSS_MAX 3 61*4882a593Smuzhiyun #define AT91_MC_SMC_RWSETUP GENMASK(26, 24) 62*4882a593Smuzhiyun #define AT91_MC_SMC_RWSETUP_(x) ((x) << 24) 63*4882a593Smuzhiyun #define AT91_MC_SMC_RWHOLD GENMASK(30, 28) 64*4882a593Smuzhiyun #define AT91_MC_SMC_RWHOLD_(x) ((x) << 28) 65*4882a593Smuzhiyun #define AT91_MC_SMC_RWHOLDSETUP_MAX 7 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* SDRAM Controller registers */ 68*4882a593Smuzhiyun #define AT91_MC_SDRAMC_MR 0x90 69*4882a593Smuzhiyun #define AT91_MC_SDRAMC_MODE GENMASK(3, 0) 70*4882a593Smuzhiyun #define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0) 71*4882a593Smuzhiyun #define AT91_MC_SDRAMC_MODE_NOP (1 << 0) 72*4882a593Smuzhiyun #define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0) 73*4882a593Smuzhiyun #define AT91_MC_SDRAMC_MODE_LMR (3 << 0) 74*4882a593Smuzhiyun #define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0) 75*4882a593Smuzhiyun #define AT91_MC_SDRAMC_DBW_16 BIT(4) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define AT91_MC_SDRAMC_TR 0x94 78*4882a593Smuzhiyun #define AT91_MC_SDRAMC_COUNT GENMASK(11, 0) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define AT91_MC_SDRAMC_CR 0x98 81*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NC GENMASK(1, 0) 82*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NC_8 (0 << 0) 83*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NC_9 (1 << 0) 84*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NC_10 (2 << 0) 85*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NC_11 (3 << 0) 86*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NR GENMASK(3, 2) 87*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NR_11 (0 << 2) 88*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NR_12 (1 << 2) 89*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NR_13 (2 << 2) 90*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NB BIT(4) 91*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NB_2 (0 << 4) 92*4882a593Smuzhiyun #define AT91_MC_SDRAMC_NB_4 (1 << 4) 93*4882a593Smuzhiyun #define AT91_MC_SDRAMC_CAS GENMASK(6, 5) 94*4882a593Smuzhiyun #define AT91_MC_SDRAMC_CAS_2 (2 << 5) 95*4882a593Smuzhiyun #define AT91_MC_SDRAMC_TWR GENMASK(10, 7) 96*4882a593Smuzhiyun #define AT91_MC_SDRAMC_TRC GENMASK(14, 11) 97*4882a593Smuzhiyun #define AT91_MC_SDRAMC_TRP GENMASK(18, 15) 98*4882a593Smuzhiyun #define AT91_MC_SDRAMC_TRCD GENMASK(22, 19) 99*4882a593Smuzhiyun #define AT91_MC_SDRAMC_TRAS GENMASK(26, 23) 100*4882a593Smuzhiyun #define AT91_MC_SDRAMC_TXSR GENMASK(30, 27) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define AT91_MC_SDRAMC_SRR 0x9c 103*4882a593Smuzhiyun #define AT91_MC_SDRAMC_SRCB BIT(0) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define AT91_MC_SDRAMC_LPR 0xa0 106*4882a593Smuzhiyun #define AT91_MC_SDRAMC_LPCB BIT(0) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define AT91_MC_SDRAMC_IER 0xa4 109*4882a593Smuzhiyun #define AT91_MC_SDRAMC_IDR 0xa8 110*4882a593Smuzhiyun #define AT91_MC_SDRAMC_IMR 0xac 111*4882a593Smuzhiyun #define AT91_MC_SDRAMC_ISR 0xb0 112*4882a593Smuzhiyun #define AT91_MC_SDRAMC_RES BIT(0) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Burst Flash Controller register */ 115*4882a593Smuzhiyun #define AT91_MC_BFC_MR 0xc0 116*4882a593Smuzhiyun #define AT91_MC_BFC_BFCOM GENMASK(1, 0) 117*4882a593Smuzhiyun #define AT91_MC_BFC_BFCOM_DISABLED (0 << 0) 118*4882a593Smuzhiyun #define AT91_MC_BFC_BFCOM_ASYNC (1 << 0) 119*4882a593Smuzhiyun #define AT91_MC_BFC_BFCOM_BURST (2 << 0) 120*4882a593Smuzhiyun #define AT91_MC_BFC_BFCC GENMASK(3, 2) 121*4882a593Smuzhiyun #define AT91_MC_BFC_BFCC_MCK (1 << 2) 122*4882a593Smuzhiyun #define AT91_MC_BFC_BFCC_DIV2 (2 << 2) 123*4882a593Smuzhiyun #define AT91_MC_BFC_BFCC_DIV4 (3 << 2) 124*4882a593Smuzhiyun #define AT91_MC_BFC_AVL GENMASK(7, 4) 125*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES GENMASK(10, 8) 126*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8) 127*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_16 (1 << 8) 128*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_32 (2 << 8) 129*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_64 (3 << 8) 130*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_128 (4 << 8) 131*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_256 (5 << 8) 132*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_512 (6 << 8) 133*4882a593Smuzhiyun #define AT91_MC_BFC_PAGES_1024 (7 << 8) 134*4882a593Smuzhiyun #define AT91_MC_BFC_OEL GENMASK(13, 12) 135*4882a593Smuzhiyun #define AT91_MC_BFC_BAAEN BIT(16) 136*4882a593Smuzhiyun #define AT91_MC_BFC_BFOEH BIT(17) 137*4882a593Smuzhiyun #define AT91_MC_BFC_MUXEN BIT(18) 138*4882a593Smuzhiyun #define AT91_MC_BFC_RDYEN BIT(19) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */ 141