1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Atmel Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Memory Controllers (MATRIX, EBI) - System peripherals registers. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _LINUX_MFD_SYSCON_ATMEL_MATRIX_H 9*4882a593Smuzhiyun #define _LINUX_MFD_SYSCON_ATMEL_MATRIX_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define AT91SAM9260_MATRIX_MCFG 0x00 12*4882a593Smuzhiyun #define AT91SAM9260_MATRIX_SCFG 0x40 13*4882a593Smuzhiyun #define AT91SAM9260_MATRIX_PRS 0x80 14*4882a593Smuzhiyun #define AT91SAM9260_MATRIX_MRCR 0x100 15*4882a593Smuzhiyun #define AT91SAM9260_MATRIX_EBICSA 0x11c 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define AT91SAM9261_MATRIX_MRCR 0x0 18*4882a593Smuzhiyun #define AT91SAM9261_MATRIX_SCFG 0x4 19*4882a593Smuzhiyun #define AT91SAM9261_MATRIX_TCR 0x24 20*4882a593Smuzhiyun #define AT91SAM9261_MATRIX_EBICSA 0x30 21*4882a593Smuzhiyun #define AT91SAM9261_MATRIX_USBPUCR 0x34 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define AT91SAM9263_MATRIX_MCFG 0x00 24*4882a593Smuzhiyun #define AT91SAM9263_MATRIX_SCFG 0x40 25*4882a593Smuzhiyun #define AT91SAM9263_MATRIX_PRS 0x80 26*4882a593Smuzhiyun #define AT91SAM9263_MATRIX_MRCR 0x100 27*4882a593Smuzhiyun #define AT91SAM9263_MATRIX_TCR 0x114 28*4882a593Smuzhiyun #define AT91SAM9263_MATRIX_EBI0CSA 0x120 29*4882a593Smuzhiyun #define AT91SAM9263_MATRIX_EBI1CSA 0x124 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define AT91SAM9RL_MATRIX_MCFG 0x00 32*4882a593Smuzhiyun #define AT91SAM9RL_MATRIX_SCFG 0x40 33*4882a593Smuzhiyun #define AT91SAM9RL_MATRIX_PRS 0x80 34*4882a593Smuzhiyun #define AT91SAM9RL_MATRIX_MRCR 0x100 35*4882a593Smuzhiyun #define AT91SAM9RL_MATRIX_TCR 0x114 36*4882a593Smuzhiyun #define AT91SAM9RL_MATRIX_EBICSA 0x120 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_MCFG 0x00 39*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_SCFG 0x40 40*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_PRS 0x80 41*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_MRCR 0x100 42*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_TCR 0x110 43*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_DDRMPR 0x118 44*4882a593Smuzhiyun #define AT91SAM9G45_MATRIX_EBICSA 0x128 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define AT91SAM9N12_MATRIX_MCFG 0x00 47*4882a593Smuzhiyun #define AT91SAM9N12_MATRIX_SCFG 0x40 48*4882a593Smuzhiyun #define AT91SAM9N12_MATRIX_PRS 0x80 49*4882a593Smuzhiyun #define AT91SAM9N12_MATRIX_MRCR 0x100 50*4882a593Smuzhiyun #define AT91SAM9N12_MATRIX_EBICSA 0x118 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define AT91SAM9X5_MATRIX_MCFG 0x00 53*4882a593Smuzhiyun #define AT91SAM9X5_MATRIX_SCFG 0x40 54*4882a593Smuzhiyun #define AT91SAM9X5_MATRIX_PRS 0x80 55*4882a593Smuzhiyun #define AT91SAM9X5_MATRIX_MRCR 0x100 56*4882a593Smuzhiyun #define AT91SAM9X5_MATRIX_EBICSA 0x120 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define SAMA5D3_MATRIX_MCFG 0x00 59*4882a593Smuzhiyun #define SAMA5D3_MATRIX_SCFG 0x40 60*4882a593Smuzhiyun #define SAMA5D3_MATRIX_PRS 0x80 61*4882a593Smuzhiyun #define SAMA5D3_MATRIX_MRCR 0x100 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define AT91_MATRIX_MCFG(o, x) ((o) + ((x) * 0x4)) 64*4882a593Smuzhiyun #define AT91_MATRIX_ULBT GENMASK(2, 0) 65*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 66*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 67*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_FOUR (2 << 0) 68*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 69*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define AT91_MATRIX_SCFG(o, x) ((o) + ((x) * 0x4)) 72*4882a593Smuzhiyun #define AT91_MATRIX_SLOT_CYCLE GENMASK(7, 0) 73*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE GENMASK(17, 16) 74*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 75*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 76*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 77*4882a593Smuzhiyun #define AT91_MATRIX_FIXED_DEFMSTR GENMASK(20, 18) 78*4882a593Smuzhiyun #define AT91_MATRIX_ARBT GENMASK(25, 24) 79*4882a593Smuzhiyun #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 80*4882a593Smuzhiyun #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define AT91_MATRIX_ITCM_SIZE GENMASK(3, 0) 83*4882a593Smuzhiyun #define AT91_MATRIX_ITCM_0 (0 << 0) 84*4882a593Smuzhiyun #define AT91_MATRIX_ITCM_16 (5 << 0) 85*4882a593Smuzhiyun #define AT91_MATRIX_ITCM_32 (6 << 0) 86*4882a593Smuzhiyun #define AT91_MATRIX_ITCM_64 (7 << 0) 87*4882a593Smuzhiyun #define AT91_MATRIX_DTCM_SIZE GENMASK(7, 4) 88*4882a593Smuzhiyun #define AT91_MATRIX_DTCM_0 (0 << 4) 89*4882a593Smuzhiyun #define AT91_MATRIX_DTCM_16 (5 << 4) 90*4882a593Smuzhiyun #define AT91_MATRIX_DTCM_32 (6 << 4) 91*4882a593Smuzhiyun #define AT91_MATRIX_DTCM_64 (7 << 4) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define AT91_MATRIX_PRAS(o, x) ((o) + ((x) * 0x8)) 94*4882a593Smuzhiyun #define AT91_MATRIX_PRBS(o, x) ((o) + ((x) * 0x8) + 0x4) 95*4882a593Smuzhiyun #define AT91_MATRIX_MPR(x) GENMASK(((x) * 0x4) + 1, ((x) * 0x4)) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define AT91_MATRIX_RCB(x) BIT(x) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define AT91_MATRIX_CSA(cs, val) (val << (cs)) 100*4882a593Smuzhiyun #define AT91_MATRIX_DBPUC BIT(8) 101*4882a593Smuzhiyun #define AT91_MATRIX_DBPDC BIT(9) 102*4882a593Smuzhiyun #define AT91_MATRIX_VDDIOMSEL BIT(16) 103*4882a593Smuzhiyun #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) 104*4882a593Smuzhiyun #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) 105*4882a593Smuzhiyun #define AT91_MATRIX_EBI_IOSR BIT(17) 106*4882a593Smuzhiyun #define AT91_MATRIX_DDR_IOSR BIT(18) 107*4882a593Smuzhiyun #define AT91_MATRIX_NFD0_SELECT BIT(24) 108*4882a593Smuzhiyun #define AT91_MATRIX_DDR_MP_EN BIT(25) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define AT91_MATRIX_USBPUCR_PUON BIT(30) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* _LINUX_MFD_SYSCON_ATMEL_MATRIX_H */ 113