1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * STM32 Low-Power Timer parent driver. 4*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2017 5*4882a593Smuzhiyun * Author: Fabrice Gasnier <fabrice.gasnier@st.com> 6*4882a593Smuzhiyun * Inspired by Benjamin Gaignard's stm32-timers driver 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _LINUX_STM32_LPTIMER_H_ 10*4882a593Smuzhiyun #define _LINUX_STM32_LPTIMER_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/clk.h> 13*4882a593Smuzhiyun #include <linux/regmap.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define STM32_LPTIM_ISR 0x00 /* Interrupt and Status Reg */ 16*4882a593Smuzhiyun #define STM32_LPTIM_ICR 0x04 /* Interrupt Clear Reg */ 17*4882a593Smuzhiyun #define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ 18*4882a593Smuzhiyun #define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ 19*4882a593Smuzhiyun #define STM32_LPTIM_CR 0x10 /* Control Reg */ 20*4882a593Smuzhiyun #define STM32_LPTIM_CMP 0x14 /* Compare Reg */ 21*4882a593Smuzhiyun #define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ 22*4882a593Smuzhiyun #define STM32_LPTIM_CNT 0x1C /* Counter Reg */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* STM32_LPTIM_ISR - bit fields */ 25*4882a593Smuzhiyun #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) 26*4882a593Smuzhiyun #define STM32_LPTIM_ARROK BIT(4) 27*4882a593Smuzhiyun #define STM32_LPTIM_CMPOK BIT(3) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* STM32_LPTIM_ICR - bit fields */ 30*4882a593Smuzhiyun #define STM32_LPTIM_ARRMCF BIT(1) 31*4882a593Smuzhiyun #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* STM32_LPTIM_IER - bit flieds */ 34*4882a593Smuzhiyun #define STM32_LPTIM_ARRMIE BIT(1) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* STM32_LPTIM_CR - bit fields */ 37*4882a593Smuzhiyun #define STM32_LPTIM_CNTSTRT BIT(2) 38*4882a593Smuzhiyun #define STM32_LPTIM_SNGSTRT BIT(1) 39*4882a593Smuzhiyun #define STM32_LPTIM_ENABLE BIT(0) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* STM32_LPTIM_CFGR - bit fields */ 42*4882a593Smuzhiyun #define STM32_LPTIM_ENC BIT(24) 43*4882a593Smuzhiyun #define STM32_LPTIM_COUNTMODE BIT(23) 44*4882a593Smuzhiyun #define STM32_LPTIM_WAVPOL BIT(21) 45*4882a593Smuzhiyun #define STM32_LPTIM_PRESC GENMASK(11, 9) 46*4882a593Smuzhiyun #define STM32_LPTIM_CKPOL GENMASK(2, 1) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* STM32_LPTIM_ARR */ 49*4882a593Smuzhiyun #define STM32_LPTIM_MAX_ARR 0xFFFF 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /** 52*4882a593Smuzhiyun * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device 53*4882a593Smuzhiyun * @clk: clock reference for this instance 54*4882a593Smuzhiyun * @regmap: register map reference for this instance 55*4882a593Smuzhiyun * @has_encoder: indicates this Low-Power Timer supports encoder mode 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun struct stm32_lptimer { 58*4882a593Smuzhiyun struct clk *clk; 59*4882a593Smuzhiyun struct regmap *regmap; 60*4882a593Smuzhiyun bool has_encoder; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif 64