1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * include/media/si476x-core.h -- Common definitions for si476x core
4*4882a593Smuzhiyun * device
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2012 Innovative Converged Devices(ICD)
7*4882a593Smuzhiyun * Copyright (C) 2013 Andrey Smirnov
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef SI476X_CORE_H
13*4882a593Smuzhiyun #define SI476X_CORE_H
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/kfifo.h>
16*4882a593Smuzhiyun #include <linux/atomic.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun #include <linux/mutex.h>
20*4882a593Smuzhiyun #include <linux/mfd/core.h>
21*4882a593Smuzhiyun #include <linux/videodev2.h>
22*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <linux/mfd/si476x-platform.h>
25*4882a593Smuzhiyun #include <linux/mfd/si476x-reports.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Command Timeouts */
28*4882a593Smuzhiyun #define SI476X_DEFAULT_TIMEOUT 100000
29*4882a593Smuzhiyun #define SI476X_TIMEOUT_TUNE 700000
30*4882a593Smuzhiyun #define SI476X_TIMEOUT_POWER_UP 330000
31*4882a593Smuzhiyun #define SI476X_STATUS_POLL_US 0
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* -------------------- si476x-i2c.c ----------------------- */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun enum si476x_freq_supported_chips {
36*4882a593Smuzhiyun SI476X_CHIP_SI4761 = 1,
37*4882a593Smuzhiyun SI476X_CHIP_SI4764,
38*4882a593Smuzhiyun SI476X_CHIP_SI4768,
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun enum si476x_part_revisions {
42*4882a593Smuzhiyun SI476X_REVISION_A10 = 0,
43*4882a593Smuzhiyun SI476X_REVISION_A20 = 1,
44*4882a593Smuzhiyun SI476X_REVISION_A30 = 2,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun enum si476x_mfd_cells {
48*4882a593Smuzhiyun SI476X_RADIO_CELL = 0,
49*4882a593Smuzhiyun SI476X_CODEC_CELL,
50*4882a593Smuzhiyun SI476X_MFD_CELLS,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /**
54*4882a593Smuzhiyun * enum si476x_power_state - possible power state of the si476x
55*4882a593Smuzhiyun * device.
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * @SI476X_POWER_DOWN: In this state all regulators are turned off
58*4882a593Smuzhiyun * and the reset line is pulled low. The device is completely
59*4882a593Smuzhiyun * inactive.
60*4882a593Smuzhiyun * @SI476X_POWER_UP_FULL: In this state all the power regualtors are
61*4882a593Smuzhiyun * turned on, reset line pulled high, IRQ line is enabled(polling is
62*4882a593Smuzhiyun * active for polling use scenario) and device is turned on with
63*4882a593Smuzhiyun * POWER_UP command. The device is ready to be used.
64*4882a593Smuzhiyun * @SI476X_POWER_INCONSISTENT: This state indicates that previous
65*4882a593Smuzhiyun * power down was inconsistent, meaning some of the regulators were
66*4882a593Smuzhiyun * not turned down and thus use of the device, without power-cycling
67*4882a593Smuzhiyun * is impossible.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun enum si476x_power_state {
70*4882a593Smuzhiyun SI476X_POWER_DOWN = 0,
71*4882a593Smuzhiyun SI476X_POWER_UP_FULL = 1,
72*4882a593Smuzhiyun SI476X_POWER_INCONSISTENT = 2,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /**
76*4882a593Smuzhiyun * struct si476x_core - internal data structure representing the
77*4882a593Smuzhiyun * underlying "core" device which all the MFD cell-devices use.
78*4882a593Smuzhiyun *
79*4882a593Smuzhiyun * @client: Actual I2C client used to transfer commands to the chip.
80*4882a593Smuzhiyun * @chip_id: Last digit of the chip model(E.g. "1" for SI4761)
81*4882a593Smuzhiyun * @cells: MFD cell devices created by this driver.
82*4882a593Smuzhiyun * @cmd_lock: Mutex used to serialize all the requests to the core
83*4882a593Smuzhiyun * device. This filed should not be used directly. Instead
84*4882a593Smuzhiyun * si476x_core_lock()/si476x_core_unlock() should be used to get
85*4882a593Smuzhiyun * exclusive access to the "core" device.
86*4882a593Smuzhiyun * @users: Active users counter(Used by the radio cell)
87*4882a593Smuzhiyun * @rds_read_queue: Wait queue used to wait for RDS data.
88*4882a593Smuzhiyun * @rds_fifo: FIFO in which all the RDS data received from the chip is
89*4882a593Smuzhiyun * placed.
90*4882a593Smuzhiyun * @rds_fifo_drainer: Worker that drains on-chip RDS FIFO.
91*4882a593Smuzhiyun * @rds_drainer_is_working: Flag used for launching only one instance
92*4882a593Smuzhiyun * of the @rds_fifo_drainer.
93*4882a593Smuzhiyun * @rds_drainer_status_lock: Lock used to guard access to the
94*4882a593Smuzhiyun * @rds_drainer_is_working variable.
95*4882a593Smuzhiyun * @command: Wait queue for wainting on the command comapletion.
96*4882a593Smuzhiyun * @cts: Clear To Send flag set upon receiving first status with CTS
97*4882a593Smuzhiyun * set.
98*4882a593Smuzhiyun * @tuning: Wait queue used for wainting for tune/seek comand
99*4882a593Smuzhiyun * completion.
100*4882a593Smuzhiyun * @stc: Similar to @cts, but for the STC bit of the status value.
101*4882a593Smuzhiyun * @power_up_parameters: Parameters used as argument for POWER_UP
102*4882a593Smuzhiyun * command when the device is started.
103*4882a593Smuzhiyun * @state: Current power state of the device.
104*4882a593Smuzhiyun * @supplues: Structure containing handles to all power supplies used
105*4882a593Smuzhiyun * by the device (NULL ones are ignored).
106*4882a593Smuzhiyun * @gpio_reset: GPIO pin connectet to the RSTB pin of the chip.
107*4882a593Smuzhiyun * @pinmux: Chip's configurable pins configuration.
108*4882a593Smuzhiyun * @diversity_mode: Chips role when functioning in diversity mode.
109*4882a593Smuzhiyun * @status_monitor: Polling worker used in polling use case scenarion
110*4882a593Smuzhiyun * (when IRQ is not avalible).
111*4882a593Smuzhiyun * @revision: Chip's running firmware revision number(Used for correct
112*4882a593Smuzhiyun * command set support).
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun struct si476x_core {
116*4882a593Smuzhiyun struct i2c_client *client;
117*4882a593Smuzhiyun struct regmap *regmap;
118*4882a593Smuzhiyun int chip_id;
119*4882a593Smuzhiyun struct mfd_cell cells[SI476X_MFD_CELLS];
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun struct mutex cmd_lock; /* for serializing fm radio operations */
122*4882a593Smuzhiyun atomic_t users;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun wait_queue_head_t rds_read_queue;
125*4882a593Smuzhiyun struct kfifo rds_fifo;
126*4882a593Smuzhiyun struct work_struct rds_fifo_drainer;
127*4882a593Smuzhiyun bool rds_drainer_is_working;
128*4882a593Smuzhiyun struct mutex rds_drainer_status_lock;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun wait_queue_head_t command;
131*4882a593Smuzhiyun atomic_t cts;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun wait_queue_head_t tuning;
134*4882a593Smuzhiyun atomic_t stc;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun struct si476x_power_up_args power_up_parameters;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun enum si476x_power_state power_state;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun struct regulator_bulk_data supplies[4];
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun int gpio_reset;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun struct si476x_pinmux pinmux;
145*4882a593Smuzhiyun enum si476x_phase_diversity_mode diversity_mode;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun atomic_t is_alive;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun struct delayed_work status_monitor;
150*4882a593Smuzhiyun #define SI476X_WORK_TO_CORE(w) container_of(to_delayed_work(w), \
151*4882a593Smuzhiyun struct si476x_core, \
152*4882a593Smuzhiyun status_monitor)
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun int revision;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun int rds_fifo_depth;
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
i2c_mfd_cell_to_core(struct device * dev)159*4882a593Smuzhiyun static inline struct si476x_core *i2c_mfd_cell_to_core(struct device *dev)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev->parent);
162*4882a593Smuzhiyun return i2c_get_clientdata(client);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /**
167*4882a593Smuzhiyun * si476x_core_lock() - lock the core device to get an exclusive access
168*4882a593Smuzhiyun * to it.
169*4882a593Smuzhiyun */
si476x_core_lock(struct si476x_core * core)170*4882a593Smuzhiyun static inline void si476x_core_lock(struct si476x_core *core)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun mutex_lock(&core->cmd_lock);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /**
176*4882a593Smuzhiyun * si476x_core_unlock() - unlock the core device to relinquish an
177*4882a593Smuzhiyun * exclusive access to it.
178*4882a593Smuzhiyun */
si476x_core_unlock(struct si476x_core * core)179*4882a593Smuzhiyun static inline void si476x_core_unlock(struct si476x_core *core)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun mutex_unlock(&core->cmd_lock);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* *_TUNE_FREQ family of commands accept frequency in multiples of
185*4882a593Smuzhiyun 10kHz */
hz_to_si476x(struct si476x_core * core,int freq)186*4882a593Smuzhiyun static inline u16 hz_to_si476x(struct si476x_core *core, int freq)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun u16 result;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun switch (core->power_up_parameters.func) {
191*4882a593Smuzhiyun default:
192*4882a593Smuzhiyun case SI476X_FUNC_FM_RECEIVER:
193*4882a593Smuzhiyun result = freq / 10000;
194*4882a593Smuzhiyun break;
195*4882a593Smuzhiyun case SI476X_FUNC_AM_RECEIVER:
196*4882a593Smuzhiyun result = freq / 1000;
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return result;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
si476x_to_hz(struct si476x_core * core,u16 freq)203*4882a593Smuzhiyun static inline int si476x_to_hz(struct si476x_core *core, u16 freq)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun int result;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun switch (core->power_up_parameters.func) {
208*4882a593Smuzhiyun default:
209*4882a593Smuzhiyun case SI476X_FUNC_FM_RECEIVER:
210*4882a593Smuzhiyun result = freq * 10000;
211*4882a593Smuzhiyun break;
212*4882a593Smuzhiyun case SI476X_FUNC_AM_RECEIVER:
213*4882a593Smuzhiyun result = freq * 1000;
214*4882a593Smuzhiyun break;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return result;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /* Since the V4L2_TUNER_CAP_LOW flag is supplied, V4L2 subsystem
221*4882a593Smuzhiyun * mesures frequency in 62.5 Hz units */
222*4882a593Smuzhiyun
hz_to_v4l2(int freq)223*4882a593Smuzhiyun static inline int hz_to_v4l2(int freq)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun return (freq * 10) / 625;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
v4l2_to_hz(int freq)228*4882a593Smuzhiyun static inline int v4l2_to_hz(int freq)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun return (freq * 625) / 10;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
v4l2_to_si476x(struct si476x_core * core,int freq)233*4882a593Smuzhiyun static inline u16 v4l2_to_si476x(struct si476x_core *core, int freq)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun return hz_to_si476x(core, v4l2_to_hz(freq));
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
si476x_to_v4l2(struct si476x_core * core,u16 freq)238*4882a593Smuzhiyun static inline int si476x_to_v4l2(struct si476x_core *core, u16 freq)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun return hz_to_v4l2(si476x_to_hz(core, freq));
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /**
246*4882a593Smuzhiyun * struct si476x_func_info - structure containing result of the
247*4882a593Smuzhiyun * FUNC_INFO command.
248*4882a593Smuzhiyun *
249*4882a593Smuzhiyun * @firmware.major: Firmware major number.
250*4882a593Smuzhiyun * @firmware.minor[...]: Firmware minor numbers.
251*4882a593Smuzhiyun * @patch_id:
252*4882a593Smuzhiyun * @func: Mode tuner is working in.
253*4882a593Smuzhiyun */
254*4882a593Smuzhiyun struct si476x_func_info {
255*4882a593Smuzhiyun struct {
256*4882a593Smuzhiyun u8 major, minor[2];
257*4882a593Smuzhiyun } firmware;
258*4882a593Smuzhiyun u16 patch_id;
259*4882a593Smuzhiyun enum si476x_func func;
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun /**
263*4882a593Smuzhiyun * struct si476x_power_down_args - structure used to pass parameters
264*4882a593Smuzhiyun * to POWER_DOWN command
265*4882a593Smuzhiyun *
266*4882a593Smuzhiyun * @xosc: true - Power down, but leav oscillator running.
267*4882a593Smuzhiyun * false - Full power down.
268*4882a593Smuzhiyun */
269*4882a593Smuzhiyun struct si476x_power_down_args {
270*4882a593Smuzhiyun bool xosc;
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /**
274*4882a593Smuzhiyun * enum si476x_tunemode - enum representing possible tune modes for
275*4882a593Smuzhiyun * the chip.
276*4882a593Smuzhiyun * @SI476X_TM_VALIDATED_NORMAL_TUNE: Unconditionally stay on the new
277*4882a593Smuzhiyun * channel after tune, tune status is valid.
278*4882a593Smuzhiyun * @SI476X_TM_INVALIDATED_FAST_TUNE: Unconditionally stay in the new
279*4882a593Smuzhiyun * channel after tune, tune status invalid.
280*4882a593Smuzhiyun * @SI476X_TM_VALIDATED_AF_TUNE: Jump back to previous channel if
281*4882a593Smuzhiyun * metric thresholds are not met.
282*4882a593Smuzhiyun * @SI476X_TM_VALIDATED_AF_CHECK: Unconditionally jump back to the
283*4882a593Smuzhiyun * previous channel.
284*4882a593Smuzhiyun */
285*4882a593Smuzhiyun enum si476x_tunemode {
286*4882a593Smuzhiyun SI476X_TM_VALIDATED_NORMAL_TUNE = 0,
287*4882a593Smuzhiyun SI476X_TM_INVALIDATED_FAST_TUNE = 1,
288*4882a593Smuzhiyun SI476X_TM_VALIDATED_AF_TUNE = 2,
289*4882a593Smuzhiyun SI476X_TM_VALIDATED_AF_CHECK = 3,
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun /**
293*4882a593Smuzhiyun * enum si476x_smoothmetrics - enum containing the possible setting fo
294*4882a593Smuzhiyun * audio transitioning of the chip
295*4882a593Smuzhiyun * @SI476X_SM_INITIALIZE_AUDIO: Initialize audio state to match this
296*4882a593Smuzhiyun * new channel
297*4882a593Smuzhiyun * @SI476X_SM_TRANSITION_AUDIO: Transition audio state from previous
298*4882a593Smuzhiyun * channel values to the new values
299*4882a593Smuzhiyun */
300*4882a593Smuzhiyun enum si476x_smoothmetrics {
301*4882a593Smuzhiyun SI476X_SM_INITIALIZE_AUDIO = 0,
302*4882a593Smuzhiyun SI476X_SM_TRANSITION_AUDIO = 1,
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /**
306*4882a593Smuzhiyun * struct si476x_rds_status_report - the structure representing the
307*4882a593Smuzhiyun * response to 'FM_RD_STATUS' command
308*4882a593Smuzhiyun * @rdstpptyint: Traffic program flag(TP) and/or program type(PTY)
309*4882a593Smuzhiyun * code has changed.
310*4882a593Smuzhiyun * @rdspiint: Program identification(PI) code has changed.
311*4882a593Smuzhiyun * @rdssyncint: RDS synchronization has changed.
312*4882a593Smuzhiyun * @rdsfifoint: RDS was received and the RDS FIFO has at least
313*4882a593Smuzhiyun * 'FM_RDS_INTERRUPT_FIFO_COUNT' elements in it.
314*4882a593Smuzhiyun * @tpptyvalid: TP flag and PTY code are valid falg.
315*4882a593Smuzhiyun * @pivalid: PI code is valid flag.
316*4882a593Smuzhiyun * @rdssync: RDS is currently synchronized.
317*4882a593Smuzhiyun * @rdsfifolost: On or more RDS groups have been lost/discarded flag.
318*4882a593Smuzhiyun * @tp: Current channel's TP flag.
319*4882a593Smuzhiyun * @pty: Current channel's PTY code.
320*4882a593Smuzhiyun * @pi: Current channel's PI code.
321*4882a593Smuzhiyun * @rdsfifoused: Number of blocks remaining in the RDS FIFO (0 if
322*4882a593Smuzhiyun * empty).
323*4882a593Smuzhiyun */
324*4882a593Smuzhiyun struct si476x_rds_status_report {
325*4882a593Smuzhiyun bool rdstpptyint, rdspiint, rdssyncint, rdsfifoint;
326*4882a593Smuzhiyun bool tpptyvalid, pivalid, rdssync, rdsfifolost;
327*4882a593Smuzhiyun bool tp;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun u8 pty;
330*4882a593Smuzhiyun u16 pi;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun u8 rdsfifoused;
333*4882a593Smuzhiyun u8 ble[4];
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun struct v4l2_rds_data rds[4];
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun struct si476x_rsq_status_args {
339*4882a593Smuzhiyun bool primary;
340*4882a593Smuzhiyun bool rsqack;
341*4882a593Smuzhiyun bool attune;
342*4882a593Smuzhiyun bool cancel;
343*4882a593Smuzhiyun bool stcack;
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun enum si476x_injside {
347*4882a593Smuzhiyun SI476X_INJSIDE_AUTO = 0,
348*4882a593Smuzhiyun SI476X_INJSIDE_LOW = 1,
349*4882a593Smuzhiyun SI476X_INJSIDE_HIGH = 2,
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun struct si476x_tune_freq_args {
353*4882a593Smuzhiyun bool zifsr;
354*4882a593Smuzhiyun bool hd;
355*4882a593Smuzhiyun enum si476x_injside injside;
356*4882a593Smuzhiyun int freq;
357*4882a593Smuzhiyun enum si476x_tunemode tunemode;
358*4882a593Smuzhiyun enum si476x_smoothmetrics smoothmetrics;
359*4882a593Smuzhiyun int antcap;
360*4882a593Smuzhiyun };
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun int si476x_core_stop(struct si476x_core *, bool);
363*4882a593Smuzhiyun int si476x_core_start(struct si476x_core *, bool);
364*4882a593Smuzhiyun int si476x_core_set_power_state(struct si476x_core *, enum si476x_power_state);
365*4882a593Smuzhiyun bool si476x_core_has_am(struct si476x_core *);
366*4882a593Smuzhiyun bool si476x_core_has_diversity(struct si476x_core *);
367*4882a593Smuzhiyun bool si476x_core_is_a_secondary_tuner(struct si476x_core *);
368*4882a593Smuzhiyun bool si476x_core_is_a_primary_tuner(struct si476x_core *);
369*4882a593Smuzhiyun bool si476x_core_is_in_am_receiver_mode(struct si476x_core *core);
370*4882a593Smuzhiyun bool si476x_core_is_powered_up(struct si476x_core *core);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun enum si476x_i2c_type {
373*4882a593Smuzhiyun SI476X_I2C_SEND,
374*4882a593Smuzhiyun SI476X_I2C_RECV
375*4882a593Smuzhiyun };
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun int si476x_core_i2c_xfer(struct si476x_core *,
378*4882a593Smuzhiyun enum si476x_i2c_type,
379*4882a593Smuzhiyun char *, int);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun /* -------------------- si476x-cmd.c ----------------------- */
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun int si476x_core_cmd_func_info(struct si476x_core *, struct si476x_func_info *);
385*4882a593Smuzhiyun int si476x_core_cmd_set_property(struct si476x_core *, u16, u16);
386*4882a593Smuzhiyun int si476x_core_cmd_get_property(struct si476x_core *, u16);
387*4882a593Smuzhiyun int si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *,
388*4882a593Smuzhiyun enum si476x_dclk_config,
389*4882a593Smuzhiyun enum si476x_dfs_config,
390*4882a593Smuzhiyun enum si476x_dout_config,
391*4882a593Smuzhiyun enum si476x_xout_config);
392*4882a593Smuzhiyun int si476x_core_cmd_zif_pin_cfg(struct si476x_core *,
393*4882a593Smuzhiyun enum si476x_iqclk_config,
394*4882a593Smuzhiyun enum si476x_iqfs_config,
395*4882a593Smuzhiyun enum si476x_iout_config,
396*4882a593Smuzhiyun enum si476x_qout_config);
397*4882a593Smuzhiyun int si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(struct si476x_core *,
398*4882a593Smuzhiyun enum si476x_icin_config,
399*4882a593Smuzhiyun enum si476x_icip_config,
400*4882a593Smuzhiyun enum si476x_icon_config,
401*4882a593Smuzhiyun enum si476x_icop_config);
402*4882a593Smuzhiyun int si476x_core_cmd_ana_audio_pin_cfg(struct si476x_core *,
403*4882a593Smuzhiyun enum si476x_lrout_config);
404*4882a593Smuzhiyun int si476x_core_cmd_intb_pin_cfg(struct si476x_core *, enum si476x_intb_config,
405*4882a593Smuzhiyun enum si476x_a1_config);
406*4882a593Smuzhiyun int si476x_core_cmd_fm_seek_start(struct si476x_core *, bool, bool);
407*4882a593Smuzhiyun int si476x_core_cmd_am_seek_start(struct si476x_core *, bool, bool);
408*4882a593Smuzhiyun int si476x_core_cmd_fm_rds_status(struct si476x_core *, bool, bool, bool,
409*4882a593Smuzhiyun struct si476x_rds_status_report *);
410*4882a593Smuzhiyun int si476x_core_cmd_fm_rds_blockcount(struct si476x_core *, bool,
411*4882a593Smuzhiyun struct si476x_rds_blockcount_report *);
412*4882a593Smuzhiyun int si476x_core_cmd_fm_tune_freq(struct si476x_core *,
413*4882a593Smuzhiyun struct si476x_tune_freq_args *);
414*4882a593Smuzhiyun int si476x_core_cmd_am_tune_freq(struct si476x_core *,
415*4882a593Smuzhiyun struct si476x_tune_freq_args *);
416*4882a593Smuzhiyun int si476x_core_cmd_am_rsq_status(struct si476x_core *,
417*4882a593Smuzhiyun struct si476x_rsq_status_args *,
418*4882a593Smuzhiyun struct si476x_rsq_status_report *);
419*4882a593Smuzhiyun int si476x_core_cmd_fm_rsq_status(struct si476x_core *,
420*4882a593Smuzhiyun struct si476x_rsq_status_args *,
421*4882a593Smuzhiyun struct si476x_rsq_status_report *);
422*4882a593Smuzhiyun int si476x_core_cmd_power_up(struct si476x_core *,
423*4882a593Smuzhiyun struct si476x_power_up_args *);
424*4882a593Smuzhiyun int si476x_core_cmd_power_down(struct si476x_core *,
425*4882a593Smuzhiyun struct si476x_power_down_args *);
426*4882a593Smuzhiyun int si476x_core_cmd_fm_phase_div_status(struct si476x_core *);
427*4882a593Smuzhiyun int si476x_core_cmd_fm_phase_diversity(struct si476x_core *,
428*4882a593Smuzhiyun enum si476x_phase_diversity_mode);
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun int si476x_core_cmd_fm_acf_status(struct si476x_core *,
431*4882a593Smuzhiyun struct si476x_acf_status_report *);
432*4882a593Smuzhiyun int si476x_core_cmd_am_acf_status(struct si476x_core *,
433*4882a593Smuzhiyun struct si476x_acf_status_report *);
434*4882a593Smuzhiyun int si476x_core_cmd_agc_status(struct si476x_core *,
435*4882a593Smuzhiyun struct si476x_agc_status_report *);
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun enum si476x_power_grid_type {
438*4882a593Smuzhiyun SI476X_POWER_GRID_50HZ = 0,
439*4882a593Smuzhiyun SI476X_POWER_GRID_60HZ,
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun /* Properties */
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun enum si476x_interrupt_flags {
445*4882a593Smuzhiyun SI476X_STCIEN = (1 << 0),
446*4882a593Smuzhiyun SI476X_ACFIEN = (1 << 1),
447*4882a593Smuzhiyun SI476X_RDSIEN = (1 << 2),
448*4882a593Smuzhiyun SI476X_RSQIEN = (1 << 3),
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun SI476X_ERRIEN = (1 << 6),
451*4882a593Smuzhiyun SI476X_CTSIEN = (1 << 7),
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun SI476X_STCREP = (1 << 8),
454*4882a593Smuzhiyun SI476X_ACFREP = (1 << 9),
455*4882a593Smuzhiyun SI476X_RDSREP = (1 << 10),
456*4882a593Smuzhiyun SI476X_RSQREP = (1 << 11),
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun enum si476x_rdsint_sources {
460*4882a593Smuzhiyun SI476X_RDSTPPTY = (1 << 4),
461*4882a593Smuzhiyun SI476X_RDSPI = (1 << 3),
462*4882a593Smuzhiyun SI476X_RDSSYNC = (1 << 1),
463*4882a593Smuzhiyun SI476X_RDSRECV = (1 << 0),
464*4882a593Smuzhiyun };
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun enum si476x_status_response_bits {
467*4882a593Smuzhiyun SI476X_CTS = (1 << 7),
468*4882a593Smuzhiyun SI476X_ERR = (1 << 6),
469*4882a593Smuzhiyun /* Status response for WB receiver */
470*4882a593Smuzhiyun SI476X_WB_ASQ_INT = (1 << 4),
471*4882a593Smuzhiyun SI476X_RSQ_INT = (1 << 3),
472*4882a593Smuzhiyun /* Status response for FM receiver */
473*4882a593Smuzhiyun SI476X_FM_RDS_INT = (1 << 2),
474*4882a593Smuzhiyun SI476X_ACF_INT = (1 << 1),
475*4882a593Smuzhiyun SI476X_STC_INT = (1 << 0),
476*4882a593Smuzhiyun };
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun /* -------------------- si476x-prop.c ----------------------- */
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun enum si476x_common_receiver_properties {
481*4882a593Smuzhiyun SI476X_PROP_INT_CTL_ENABLE = 0x0000,
482*4882a593Smuzhiyun SI476X_PROP_DIGITAL_IO_INPUT_SAMPLE_RATE = 0x0200,
483*4882a593Smuzhiyun SI476X_PROP_DIGITAL_IO_INPUT_FORMAT = 0x0201,
484*4882a593Smuzhiyun SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202,
485*4882a593Smuzhiyun SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT = 0x0203,
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun SI476X_PROP_SEEK_BAND_BOTTOM = 0x1100,
488*4882a593Smuzhiyun SI476X_PROP_SEEK_BAND_TOP = 0x1101,
489*4882a593Smuzhiyun SI476X_PROP_SEEK_FREQUENCY_SPACING = 0x1102,
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun SI476X_PROP_VALID_MAX_TUNE_ERROR = 0x2000,
492*4882a593Smuzhiyun SI476X_PROP_VALID_SNR_THRESHOLD = 0x2003,
493*4882a593Smuzhiyun SI476X_PROP_VALID_RSSI_THRESHOLD = 0x2004,
494*4882a593Smuzhiyun };
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun enum si476x_am_receiver_properties {
497*4882a593Smuzhiyun SI476X_PROP_AUDIO_PWR_LINE_FILTER = 0x0303,
498*4882a593Smuzhiyun };
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun enum si476x_fm_receiver_properties {
501*4882a593Smuzhiyun SI476X_PROP_AUDIO_DEEMPHASIS = 0x0302,
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun SI476X_PROP_FM_RDS_INTERRUPT_SOURCE = 0x4000,
504*4882a593Smuzhiyun SI476X_PROP_FM_RDS_INTERRUPT_FIFO_COUNT = 0x4001,
505*4882a593Smuzhiyun SI476X_PROP_FM_RDS_CONFIG = 0x4002,
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun enum si476x_prop_audio_pwr_line_filter_bits {
509*4882a593Smuzhiyun SI476X_PROP_PWR_HARMONICS_MASK = 0x001f,
510*4882a593Smuzhiyun SI476X_PROP_PWR_GRID_MASK = 0x0100,
511*4882a593Smuzhiyun SI476X_PROP_PWR_ENABLE_MASK = 0x0200,
512*4882a593Smuzhiyun SI476X_PROP_PWR_GRID_50HZ = 0x0000,
513*4882a593Smuzhiyun SI476X_PROP_PWR_GRID_60HZ = 0x0100,
514*4882a593Smuzhiyun };
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun enum si476x_prop_fm_rds_config_bits {
517*4882a593Smuzhiyun SI476X_PROP_RDSEN_MASK = 0x1,
518*4882a593Smuzhiyun SI476X_PROP_RDSEN = 0x1,
519*4882a593Smuzhiyun };
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun struct regmap *devm_regmap_init_si476x(struct si476x_core *);
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun #endif /* SI476X_CORE_H */
525