xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/s5m8767.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2011 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *              http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_S5M8767_H
8*4882a593Smuzhiyun #define __LINUX_MFD_S5M8767_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* S5M8767 registers */
11*4882a593Smuzhiyun enum s5m8767_reg {
12*4882a593Smuzhiyun 	S5M8767_REG_ID,
13*4882a593Smuzhiyun 	S5M8767_REG_INT1,
14*4882a593Smuzhiyun 	S5M8767_REG_INT2,
15*4882a593Smuzhiyun 	S5M8767_REG_INT3,
16*4882a593Smuzhiyun 	S5M8767_REG_INT1M,
17*4882a593Smuzhiyun 	S5M8767_REG_INT2M,
18*4882a593Smuzhiyun 	S5M8767_REG_INT3M,
19*4882a593Smuzhiyun 	S5M8767_REG_STATUS1,
20*4882a593Smuzhiyun 	S5M8767_REG_STATUS2,
21*4882a593Smuzhiyun 	S5M8767_REG_STATUS3,
22*4882a593Smuzhiyun 	S5M8767_REG_CTRL1,
23*4882a593Smuzhiyun 	S5M8767_REG_CTRL2,
24*4882a593Smuzhiyun 	S5M8767_REG_LOWBAT1,
25*4882a593Smuzhiyun 	S5M8767_REG_LOWBAT2,
26*4882a593Smuzhiyun 	S5M8767_REG_BUCHG,
27*4882a593Smuzhiyun 	S5M8767_REG_DVSRAMP,
28*4882a593Smuzhiyun 	S5M8767_REG_DVSTIMER2 = 0x10,
29*4882a593Smuzhiyun 	S5M8767_REG_DVSTIMER3,
30*4882a593Smuzhiyun 	S5M8767_REG_DVSTIMER4,
31*4882a593Smuzhiyun 	S5M8767_REG_LDO1,
32*4882a593Smuzhiyun 	S5M8767_REG_LDO2,
33*4882a593Smuzhiyun 	S5M8767_REG_LDO3,
34*4882a593Smuzhiyun 	S5M8767_REG_LDO4,
35*4882a593Smuzhiyun 	S5M8767_REG_LDO5,
36*4882a593Smuzhiyun 	S5M8767_REG_LDO6,
37*4882a593Smuzhiyun 	S5M8767_REG_LDO7,
38*4882a593Smuzhiyun 	S5M8767_REG_LDO8,
39*4882a593Smuzhiyun 	S5M8767_REG_LDO9,
40*4882a593Smuzhiyun 	S5M8767_REG_LDO10,
41*4882a593Smuzhiyun 	S5M8767_REG_LDO11,
42*4882a593Smuzhiyun 	S5M8767_REG_LDO12,
43*4882a593Smuzhiyun 	S5M8767_REG_LDO13,
44*4882a593Smuzhiyun 	S5M8767_REG_LDO14 = 0x20,
45*4882a593Smuzhiyun 	S5M8767_REG_LDO15,
46*4882a593Smuzhiyun 	S5M8767_REG_LDO16,
47*4882a593Smuzhiyun 	S5M8767_REG_LDO17,
48*4882a593Smuzhiyun 	S5M8767_REG_LDO18,
49*4882a593Smuzhiyun 	S5M8767_REG_LDO19,
50*4882a593Smuzhiyun 	S5M8767_REG_LDO20,
51*4882a593Smuzhiyun 	S5M8767_REG_LDO21,
52*4882a593Smuzhiyun 	S5M8767_REG_LDO22,
53*4882a593Smuzhiyun 	S5M8767_REG_LDO23,
54*4882a593Smuzhiyun 	S5M8767_REG_LDO24,
55*4882a593Smuzhiyun 	S5M8767_REG_LDO25,
56*4882a593Smuzhiyun 	S5M8767_REG_LDO26,
57*4882a593Smuzhiyun 	S5M8767_REG_LDO27,
58*4882a593Smuzhiyun 	S5M8767_REG_LDO28,
59*4882a593Smuzhiyun 	S5M8767_REG_UVLO = 0x31,
60*4882a593Smuzhiyun 	S5M8767_REG_BUCK1CTRL1,
61*4882a593Smuzhiyun 	S5M8767_REG_BUCK1CTRL2,
62*4882a593Smuzhiyun 	S5M8767_REG_BUCK2CTRL,
63*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS1,
64*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS2,
65*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS3,
66*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS4,
67*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS5,
68*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS6,
69*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS7,
70*4882a593Smuzhiyun 	S5M8767_REG_BUCK2DVS8,
71*4882a593Smuzhiyun 	S5M8767_REG_BUCK3CTRL,
72*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS1,
73*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS2,
74*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS3,
75*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS4,
76*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS5,
77*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS6,
78*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS7,
79*4882a593Smuzhiyun 	S5M8767_REG_BUCK3DVS8,
80*4882a593Smuzhiyun 	S5M8767_REG_BUCK4CTRL,
81*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS1,
82*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS2,
83*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS3,
84*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS4,
85*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS5,
86*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS6,
87*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS7,
88*4882a593Smuzhiyun 	S5M8767_REG_BUCK4DVS8,
89*4882a593Smuzhiyun 	S5M8767_REG_BUCK5CTRL1,
90*4882a593Smuzhiyun 	S5M8767_REG_BUCK5CTRL2,
91*4882a593Smuzhiyun 	S5M8767_REG_BUCK5CTRL3,
92*4882a593Smuzhiyun 	S5M8767_REG_BUCK5CTRL4,
93*4882a593Smuzhiyun 	S5M8767_REG_BUCK5CTRL5,
94*4882a593Smuzhiyun 	S5M8767_REG_BUCK6CTRL1,
95*4882a593Smuzhiyun 	S5M8767_REG_BUCK6CTRL2,
96*4882a593Smuzhiyun 	S5M8767_REG_BUCK7CTRL1,
97*4882a593Smuzhiyun 	S5M8767_REG_BUCK7CTRL2,
98*4882a593Smuzhiyun 	S5M8767_REG_BUCK8CTRL1,
99*4882a593Smuzhiyun 	S5M8767_REG_BUCK8CTRL2,
100*4882a593Smuzhiyun 	S5M8767_REG_BUCK9CTRL1,
101*4882a593Smuzhiyun 	S5M8767_REG_BUCK9CTRL2,
102*4882a593Smuzhiyun 	S5M8767_REG_LDO1CTRL,
103*4882a593Smuzhiyun 	S5M8767_REG_LDO2_1CTRL,
104*4882a593Smuzhiyun 	S5M8767_REG_LDO2_2CTRL,
105*4882a593Smuzhiyun 	S5M8767_REG_LDO2_3CTRL,
106*4882a593Smuzhiyun 	S5M8767_REG_LDO2_4CTRL,
107*4882a593Smuzhiyun 	S5M8767_REG_LDO3CTRL,
108*4882a593Smuzhiyun 	S5M8767_REG_LDO4CTRL,
109*4882a593Smuzhiyun 	S5M8767_REG_LDO5CTRL,
110*4882a593Smuzhiyun 	S5M8767_REG_LDO6CTRL,
111*4882a593Smuzhiyun 	S5M8767_REG_LDO7CTRL,
112*4882a593Smuzhiyun 	S5M8767_REG_LDO8CTRL,
113*4882a593Smuzhiyun 	S5M8767_REG_LDO9CTRL,
114*4882a593Smuzhiyun 	S5M8767_REG_LDO10CTRL,
115*4882a593Smuzhiyun 	S5M8767_REG_LDO11CTRL,
116*4882a593Smuzhiyun 	S5M8767_REG_LDO12CTRL,
117*4882a593Smuzhiyun 	S5M8767_REG_LDO13CTRL,
118*4882a593Smuzhiyun 	S5M8767_REG_LDO14CTRL,
119*4882a593Smuzhiyun 	S5M8767_REG_LDO15CTRL,
120*4882a593Smuzhiyun 	S5M8767_REG_LDO16CTRL,
121*4882a593Smuzhiyun 	S5M8767_REG_LDO17CTRL,
122*4882a593Smuzhiyun 	S5M8767_REG_LDO18CTRL,
123*4882a593Smuzhiyun 	S5M8767_REG_LDO19CTRL,
124*4882a593Smuzhiyun 	S5M8767_REG_LDO20CTRL,
125*4882a593Smuzhiyun 	S5M8767_REG_LDO21CTRL,
126*4882a593Smuzhiyun 	S5M8767_REG_LDO22CTRL,
127*4882a593Smuzhiyun 	S5M8767_REG_LDO23CTRL,
128*4882a593Smuzhiyun 	S5M8767_REG_LDO24CTRL,
129*4882a593Smuzhiyun 	S5M8767_REG_LDO25CTRL,
130*4882a593Smuzhiyun 	S5M8767_REG_LDO26CTRL,
131*4882a593Smuzhiyun 	S5M8767_REG_LDO27CTRL,
132*4882a593Smuzhiyun 	S5M8767_REG_LDO28CTRL,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /* S5M8767 regulator ids */
136*4882a593Smuzhiyun enum s5m8767_regulators {
137*4882a593Smuzhiyun 	S5M8767_LDO1,
138*4882a593Smuzhiyun 	S5M8767_LDO2,
139*4882a593Smuzhiyun 	S5M8767_LDO3,
140*4882a593Smuzhiyun 	S5M8767_LDO4,
141*4882a593Smuzhiyun 	S5M8767_LDO5,
142*4882a593Smuzhiyun 	S5M8767_LDO6,
143*4882a593Smuzhiyun 	S5M8767_LDO7,
144*4882a593Smuzhiyun 	S5M8767_LDO8,
145*4882a593Smuzhiyun 	S5M8767_LDO9,
146*4882a593Smuzhiyun 	S5M8767_LDO10,
147*4882a593Smuzhiyun 	S5M8767_LDO11,
148*4882a593Smuzhiyun 	S5M8767_LDO12,
149*4882a593Smuzhiyun 	S5M8767_LDO13,
150*4882a593Smuzhiyun 	S5M8767_LDO14,
151*4882a593Smuzhiyun 	S5M8767_LDO15,
152*4882a593Smuzhiyun 	S5M8767_LDO16,
153*4882a593Smuzhiyun 	S5M8767_LDO17,
154*4882a593Smuzhiyun 	S5M8767_LDO18,
155*4882a593Smuzhiyun 	S5M8767_LDO19,
156*4882a593Smuzhiyun 	S5M8767_LDO20,
157*4882a593Smuzhiyun 	S5M8767_LDO21,
158*4882a593Smuzhiyun 	S5M8767_LDO22,
159*4882a593Smuzhiyun 	S5M8767_LDO23,
160*4882a593Smuzhiyun 	S5M8767_LDO24,
161*4882a593Smuzhiyun 	S5M8767_LDO25,
162*4882a593Smuzhiyun 	S5M8767_LDO26,
163*4882a593Smuzhiyun 	S5M8767_LDO27,
164*4882a593Smuzhiyun 	S5M8767_LDO28,
165*4882a593Smuzhiyun 	S5M8767_BUCK1,
166*4882a593Smuzhiyun 	S5M8767_BUCK2,
167*4882a593Smuzhiyun 	S5M8767_BUCK3,
168*4882a593Smuzhiyun 	S5M8767_BUCK4,
169*4882a593Smuzhiyun 	S5M8767_BUCK5,
170*4882a593Smuzhiyun 	S5M8767_BUCK6,
171*4882a593Smuzhiyun 	S5M8767_BUCK7,
172*4882a593Smuzhiyun 	S5M8767_BUCK8,
173*4882a593Smuzhiyun 	S5M8767_BUCK9,
174*4882a593Smuzhiyun 	S5M8767_AP_EN32KHZ,
175*4882a593Smuzhiyun 	S5M8767_CP_EN32KHZ,
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	S5M8767_REG_MAX,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /* LDO_EN/BUCK_EN field in registers */
181*4882a593Smuzhiyun #define S5M8767_ENCTRL_SHIFT		6
182*4882a593Smuzhiyun #define S5M8767_ENCTRL_MASK		(0x3 << S5M8767_ENCTRL_SHIFT)
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /*
185*4882a593Smuzhiyun  * LDO_EN/BUCK_EN register value for controlling this Buck or LDO
186*4882a593Smuzhiyun  * by GPIO (PWREN, BUCKEN).
187*4882a593Smuzhiyun  */
188*4882a593Smuzhiyun #define S5M8767_ENCTRL_USE_GPIO		0x1
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun /*
191*4882a593Smuzhiyun  * Values for BUCK_RAMP field in DVS_RAMP register, matching raw values
192*4882a593Smuzhiyun  * in mV/us.
193*4882a593Smuzhiyun  */
194*4882a593Smuzhiyun enum s5m8767_dvs_buck_ramp_values {
195*4882a593Smuzhiyun 	S5M8767_DVS_BUCK_RAMP_5		= 0x4,
196*4882a593Smuzhiyun 	S5M8767_DVS_BUCK_RAMP_10	= 0x9,
197*4882a593Smuzhiyun 	S5M8767_DVS_BUCK_RAMP_12_5	= 0xb,
198*4882a593Smuzhiyun 	S5M8767_DVS_BUCK_RAMP_25	= 0xd,
199*4882a593Smuzhiyun 	S5M8767_DVS_BUCK_RAMP_50	= 0xe,
200*4882a593Smuzhiyun 	S5M8767_DVS_BUCK_RAMP_100	= 0xf,
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun #define S5M8767_DVS_BUCK_RAMP_SHIFT	4
203*4882a593Smuzhiyun #define S5M8767_DVS_BUCK_RAMP_MASK	(0xf << S5M8767_DVS_BUCK_RAMP_SHIFT)
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #endif /* __LINUX_MFD_S5M8767_H */
206