xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/s2mpu02.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *              http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_S2MPU02_H
8*4882a593Smuzhiyun #define __LINUX_MFD_S2MPU02_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* S2MPU02 registers */
11*4882a593Smuzhiyun enum S2MPU02_reg {
12*4882a593Smuzhiyun 	S2MPU02_REG_ID,
13*4882a593Smuzhiyun 	S2MPU02_REG_INT1,
14*4882a593Smuzhiyun 	S2MPU02_REG_INT2,
15*4882a593Smuzhiyun 	S2MPU02_REG_INT3,
16*4882a593Smuzhiyun 	S2MPU02_REG_INT1M,
17*4882a593Smuzhiyun 	S2MPU02_REG_INT2M,
18*4882a593Smuzhiyun 	S2MPU02_REG_INT3M,
19*4882a593Smuzhiyun 	S2MPU02_REG_ST1,
20*4882a593Smuzhiyun 	S2MPU02_REG_ST2,
21*4882a593Smuzhiyun 	S2MPU02_REG_PWRONSRC,
22*4882a593Smuzhiyun 	S2MPU02_REG_OFFSRC,
23*4882a593Smuzhiyun 	S2MPU02_REG_BU_CHG,
24*4882a593Smuzhiyun 	S2MPU02_REG_RTCCTRL,
25*4882a593Smuzhiyun 	S2MPU02_REG_PMCTRL1,
26*4882a593Smuzhiyun 	S2MPU02_REG_RSVD1,
27*4882a593Smuzhiyun 	S2MPU02_REG_RSVD2,
28*4882a593Smuzhiyun 	S2MPU02_REG_RSVD3,
29*4882a593Smuzhiyun 	S2MPU02_REG_RSVD4,
30*4882a593Smuzhiyun 	S2MPU02_REG_RSVD5,
31*4882a593Smuzhiyun 	S2MPU02_REG_RSVD6,
32*4882a593Smuzhiyun 	S2MPU02_REG_RSVD7,
33*4882a593Smuzhiyun 	S2MPU02_REG_WRSTEN,
34*4882a593Smuzhiyun 	S2MPU02_REG_RSVD8,
35*4882a593Smuzhiyun 	S2MPU02_REG_RSVD9,
36*4882a593Smuzhiyun 	S2MPU02_REG_RSVD10,
37*4882a593Smuzhiyun 	S2MPU02_REG_B1CTRL1,
38*4882a593Smuzhiyun 	S2MPU02_REG_B1CTRL2,
39*4882a593Smuzhiyun 	S2MPU02_REG_B2CTRL1,
40*4882a593Smuzhiyun 	S2MPU02_REG_B2CTRL2,
41*4882a593Smuzhiyun 	S2MPU02_REG_B3CTRL1,
42*4882a593Smuzhiyun 	S2MPU02_REG_B3CTRL2,
43*4882a593Smuzhiyun 	S2MPU02_REG_B4CTRL1,
44*4882a593Smuzhiyun 	S2MPU02_REG_B4CTRL2,
45*4882a593Smuzhiyun 	S2MPU02_REG_B5CTRL1,
46*4882a593Smuzhiyun 	S2MPU02_REG_B5CTRL2,
47*4882a593Smuzhiyun 	S2MPU02_REG_B5CTRL3,
48*4882a593Smuzhiyun 	S2MPU02_REG_B5CTRL4,
49*4882a593Smuzhiyun 	S2MPU02_REG_B5CTRL5,
50*4882a593Smuzhiyun 	S2MPU02_REG_B6CTRL1,
51*4882a593Smuzhiyun 	S2MPU02_REG_B6CTRL2,
52*4882a593Smuzhiyun 	S2MPU02_REG_B7CTRL1,
53*4882a593Smuzhiyun 	S2MPU02_REG_B7CTRL2,
54*4882a593Smuzhiyun 	S2MPU02_REG_RAMP1,
55*4882a593Smuzhiyun 	S2MPU02_REG_RAMP2,
56*4882a593Smuzhiyun 	S2MPU02_REG_L1CTRL,
57*4882a593Smuzhiyun 	S2MPU02_REG_L2CTRL1,
58*4882a593Smuzhiyun 	S2MPU02_REG_L2CTRL2,
59*4882a593Smuzhiyun 	S2MPU02_REG_L2CTRL3,
60*4882a593Smuzhiyun 	S2MPU02_REG_L2CTRL4,
61*4882a593Smuzhiyun 	S2MPU02_REG_L3CTRL,
62*4882a593Smuzhiyun 	S2MPU02_REG_L4CTRL,
63*4882a593Smuzhiyun 	S2MPU02_REG_L5CTRL,
64*4882a593Smuzhiyun 	S2MPU02_REG_L6CTRL,
65*4882a593Smuzhiyun 	S2MPU02_REG_L7CTRL,
66*4882a593Smuzhiyun 	S2MPU02_REG_L8CTRL,
67*4882a593Smuzhiyun 	S2MPU02_REG_L9CTRL,
68*4882a593Smuzhiyun 	S2MPU02_REG_L10CTRL,
69*4882a593Smuzhiyun 	S2MPU02_REG_L11CTRL,
70*4882a593Smuzhiyun 	S2MPU02_REG_L12CTRL,
71*4882a593Smuzhiyun 	S2MPU02_REG_L13CTRL,
72*4882a593Smuzhiyun 	S2MPU02_REG_L14CTRL,
73*4882a593Smuzhiyun 	S2MPU02_REG_L15CTRL,
74*4882a593Smuzhiyun 	S2MPU02_REG_L16CTRL,
75*4882a593Smuzhiyun 	S2MPU02_REG_L17CTRL,
76*4882a593Smuzhiyun 	S2MPU02_REG_L18CTRL,
77*4882a593Smuzhiyun 	S2MPU02_REG_L19CTRL,
78*4882a593Smuzhiyun 	S2MPU02_REG_L20CTRL,
79*4882a593Smuzhiyun 	S2MPU02_REG_L21CTRL,
80*4882a593Smuzhiyun 	S2MPU02_REG_L22CTRL,
81*4882a593Smuzhiyun 	S2MPU02_REG_L23CTRL,
82*4882a593Smuzhiyun 	S2MPU02_REG_L24CTRL,
83*4882a593Smuzhiyun 	S2MPU02_REG_L25CTRL,
84*4882a593Smuzhiyun 	S2MPU02_REG_L26CTRL,
85*4882a593Smuzhiyun 	S2MPU02_REG_L27CTRL,
86*4882a593Smuzhiyun 	S2MPU02_REG_L28CTRL,
87*4882a593Smuzhiyun 	S2MPU02_REG_LDODSCH1,
88*4882a593Smuzhiyun 	S2MPU02_REG_LDODSCH2,
89*4882a593Smuzhiyun 	S2MPU02_REG_LDODSCH3,
90*4882a593Smuzhiyun 	S2MPU02_REG_LDODSCH4,
91*4882a593Smuzhiyun 	S2MPU02_REG_SELMIF,
92*4882a593Smuzhiyun 	S2MPU02_REG_RSVD11,
93*4882a593Smuzhiyun 	S2MPU02_REG_RSVD12,
94*4882a593Smuzhiyun 	S2MPU02_REG_RSVD13,
95*4882a593Smuzhiyun 	S2MPU02_REG_DVSSEL,
96*4882a593Smuzhiyun 	S2MPU02_REG_DVSPTR,
97*4882a593Smuzhiyun 	S2MPU02_REG_DVSDATA,
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* S2MPU02 regulator ids */
101*4882a593Smuzhiyun enum S2MPU02_regulators {
102*4882a593Smuzhiyun 	S2MPU02_LDO1,
103*4882a593Smuzhiyun 	S2MPU02_LDO2,
104*4882a593Smuzhiyun 	S2MPU02_LDO3,
105*4882a593Smuzhiyun 	S2MPU02_LDO4,
106*4882a593Smuzhiyun 	S2MPU02_LDO5,
107*4882a593Smuzhiyun 	S2MPU02_LDO6,
108*4882a593Smuzhiyun 	S2MPU02_LDO7,
109*4882a593Smuzhiyun 	S2MPU02_LDO8,
110*4882a593Smuzhiyun 	S2MPU02_LDO9,
111*4882a593Smuzhiyun 	S2MPU02_LDO10,
112*4882a593Smuzhiyun 	S2MPU02_LDO11,
113*4882a593Smuzhiyun 	S2MPU02_LDO12,
114*4882a593Smuzhiyun 	S2MPU02_LDO13,
115*4882a593Smuzhiyun 	S2MPU02_LDO14,
116*4882a593Smuzhiyun 	S2MPU02_LDO15,
117*4882a593Smuzhiyun 	S2MPU02_LDO16,
118*4882a593Smuzhiyun 	S2MPU02_LDO17,
119*4882a593Smuzhiyun 	S2MPU02_LDO18,
120*4882a593Smuzhiyun 	S2MPU02_LDO19,
121*4882a593Smuzhiyun 	S2MPU02_LDO20,
122*4882a593Smuzhiyun 	S2MPU02_LDO21,
123*4882a593Smuzhiyun 	S2MPU02_LDO22,
124*4882a593Smuzhiyun 	S2MPU02_LDO23,
125*4882a593Smuzhiyun 	S2MPU02_LDO24,
126*4882a593Smuzhiyun 	S2MPU02_LDO25,
127*4882a593Smuzhiyun 	S2MPU02_LDO26,
128*4882a593Smuzhiyun 	S2MPU02_LDO27,
129*4882a593Smuzhiyun 	S2MPU02_LDO28,
130*4882a593Smuzhiyun 	S2MPU02_BUCK1,
131*4882a593Smuzhiyun 	S2MPU02_BUCK2,
132*4882a593Smuzhiyun 	S2MPU02_BUCK3,
133*4882a593Smuzhiyun 	S2MPU02_BUCK4,
134*4882a593Smuzhiyun 	S2MPU02_BUCK5,
135*4882a593Smuzhiyun 	S2MPU02_BUCK6,
136*4882a593Smuzhiyun 	S2MPU02_BUCK7,
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	S2MPU02_REGULATOR_MAX,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun /* Regulator constraints for BUCKx */
142*4882a593Smuzhiyun #define S2MPU02_BUCK1234_MIN_600MV	600000
143*4882a593Smuzhiyun #define S2MPU02_BUCK5_MIN_1081_25MV	1081250
144*4882a593Smuzhiyun #define S2MPU02_BUCK6_MIN_1700MV	1700000
145*4882a593Smuzhiyun #define S2MPU02_BUCK7_MIN_900MV		900000
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun #define S2MPU02_BUCK1234_STEP_6_25MV	6250
148*4882a593Smuzhiyun #define S2MPU02_BUCK5_STEP_6_25MV	6250
149*4882a593Smuzhiyun #define S2MPU02_BUCK6_STEP_2_50MV	2500
150*4882a593Smuzhiyun #define S2MPU02_BUCK7_STEP_6_25MV	6250
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #define S2MPU02_BUCK1234_START_SEL	0x00
153*4882a593Smuzhiyun #define S2MPU02_BUCK5_START_SEL		0x4D
154*4882a593Smuzhiyun #define S2MPU02_BUCK6_START_SEL		0x28
155*4882a593Smuzhiyun #define S2MPU02_BUCK7_START_SEL		0x30
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun #define S2MPU02_BUCK_RAMP_DELAY		12500
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun /* Regulator constraints for different types of LDOx */
160*4882a593Smuzhiyun #define S2MPU02_LDO_MIN_900MV		900000
161*4882a593Smuzhiyun #define S2MPU02_LDO_MIN_1050MV		1050000
162*4882a593Smuzhiyun #define S2MPU02_LDO_MIN_1600MV		1600000
163*4882a593Smuzhiyun #define S2MPU02_LDO_STEP_12_5MV		12500
164*4882a593Smuzhiyun #define S2MPU02_LDO_STEP_25MV		25000
165*4882a593Smuzhiyun #define S2MPU02_LDO_STEP_50MV		50000
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define S2MPU02_LDO_GROUP1_START_SEL	0x8
168*4882a593Smuzhiyun #define S2MPU02_LDO_GROUP2_START_SEL	0xA
169*4882a593Smuzhiyun #define S2MPU02_LDO_GROUP3_START_SEL	0x10
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun #define S2MPU02_LDO_VSEL_MASK		0x3F
172*4882a593Smuzhiyun #define S2MPU02_BUCK_VSEL_MASK		0xFF
173*4882a593Smuzhiyun #define S2MPU02_ENABLE_MASK		(0x03 << S2MPU02_ENABLE_SHIFT)
174*4882a593Smuzhiyun #define S2MPU02_ENABLE_SHIFT		6
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun /* On/Off controlled by PWREN */
177*4882a593Smuzhiyun #define S2MPU02_ENABLE_SUSPEND		(0x01 << S2MPU02_ENABLE_SHIFT)
178*4882a593Smuzhiyun #define S2MPU02_DISABLE_SUSPEND		(0x11 << S2MPU02_ENABLE_SHIFT)
179*4882a593Smuzhiyun #define S2MPU02_LDO_N_VOLTAGES		(S2MPU02_LDO_VSEL_MASK + 1)
180*4882a593Smuzhiyun #define S2MPU02_BUCK_N_VOLTAGES		(S2MPU02_BUCK_VSEL_MASK + 1)
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun /* RAMP delay for BUCK1234*/
183*4882a593Smuzhiyun #define S2MPU02_BUCK1_RAMP_SHIFT	6
184*4882a593Smuzhiyun #define S2MPU02_BUCK2_RAMP_SHIFT	4
185*4882a593Smuzhiyun #define S2MPU02_BUCK3_RAMP_SHIFT	2
186*4882a593Smuzhiyun #define S2MPU02_BUCK4_RAMP_SHIFT	0
187*4882a593Smuzhiyun #define S2MPU02_BUCK1234_RAMP_MASK	0x3
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun #endif /*  __LINUX_MFD_S2MPU02_H */
190