xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/s2mps15.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2015 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *              http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_S2MPS15_H
8*4882a593Smuzhiyun #define __LINUX_MFD_S2MPS15_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* S2MPS15 registers */
11*4882a593Smuzhiyun enum s2mps15_reg {
12*4882a593Smuzhiyun 	S2MPS15_REG_ID,
13*4882a593Smuzhiyun 	S2MPS15_REG_INT1,
14*4882a593Smuzhiyun 	S2MPS15_REG_INT2,
15*4882a593Smuzhiyun 	S2MPS15_REG_INT3,
16*4882a593Smuzhiyun 	S2MPS15_REG_INT1M,
17*4882a593Smuzhiyun 	S2MPS15_REG_INT2M,
18*4882a593Smuzhiyun 	S2MPS15_REG_INT3M,
19*4882a593Smuzhiyun 	S2MPS15_REG_ST1,
20*4882a593Smuzhiyun 	S2MPS15_REG_ST2,
21*4882a593Smuzhiyun 	S2MPS15_REG_PWRONSRC,
22*4882a593Smuzhiyun 	S2MPS15_REG_OFFSRC,
23*4882a593Smuzhiyun 	S2MPS15_REG_BU_CHG,
24*4882a593Smuzhiyun 	S2MPS15_REG_RTC_BUF,
25*4882a593Smuzhiyun 	S2MPS15_REG_CTRL1,
26*4882a593Smuzhiyun 	S2MPS15_REG_CTRL2,
27*4882a593Smuzhiyun 	S2MPS15_REG_RSVD1,
28*4882a593Smuzhiyun 	S2MPS15_REG_RSVD2,
29*4882a593Smuzhiyun 	S2MPS15_REG_RSVD3,
30*4882a593Smuzhiyun 	S2MPS15_REG_RSVD4,
31*4882a593Smuzhiyun 	S2MPS15_REG_RSVD5,
32*4882a593Smuzhiyun 	S2MPS15_REG_RSVD6,
33*4882a593Smuzhiyun 	S2MPS15_REG_CTRL3,
34*4882a593Smuzhiyun 	S2MPS15_REG_RSVD7,
35*4882a593Smuzhiyun 	S2MPS15_REG_RSVD8,
36*4882a593Smuzhiyun 	S2MPS15_REG_RSVD9,
37*4882a593Smuzhiyun 	S2MPS15_REG_B1CTRL1,
38*4882a593Smuzhiyun 	S2MPS15_REG_B1CTRL2,
39*4882a593Smuzhiyun 	S2MPS15_REG_B2CTRL1,
40*4882a593Smuzhiyun 	S2MPS15_REG_B2CTRL2,
41*4882a593Smuzhiyun 	S2MPS15_REG_B3CTRL1,
42*4882a593Smuzhiyun 	S2MPS15_REG_B3CTRL2,
43*4882a593Smuzhiyun 	S2MPS15_REG_B4CTRL1,
44*4882a593Smuzhiyun 	S2MPS15_REG_B4CTRL2,
45*4882a593Smuzhiyun 	S2MPS15_REG_B5CTRL1,
46*4882a593Smuzhiyun 	S2MPS15_REG_B5CTRL2,
47*4882a593Smuzhiyun 	S2MPS15_REG_B6CTRL1,
48*4882a593Smuzhiyun 	S2MPS15_REG_B6CTRL2,
49*4882a593Smuzhiyun 	S2MPS15_REG_B7CTRL1,
50*4882a593Smuzhiyun 	S2MPS15_REG_B7CTRL2,
51*4882a593Smuzhiyun 	S2MPS15_REG_B8CTRL1,
52*4882a593Smuzhiyun 	S2MPS15_REG_B8CTRL2,
53*4882a593Smuzhiyun 	S2MPS15_REG_B9CTRL1,
54*4882a593Smuzhiyun 	S2MPS15_REG_B9CTRL2,
55*4882a593Smuzhiyun 	S2MPS15_REG_B10CTRL1,
56*4882a593Smuzhiyun 	S2MPS15_REG_B10CTRL2,
57*4882a593Smuzhiyun 	S2MPS15_REG_BBCTRL1,
58*4882a593Smuzhiyun 	S2MPS15_REG_BBCTRL2,
59*4882a593Smuzhiyun 	S2MPS15_REG_BRAMP,
60*4882a593Smuzhiyun 	S2MPS15_REG_LDODVS1,
61*4882a593Smuzhiyun 	S2MPS15_REG_LDODVS2,
62*4882a593Smuzhiyun 	S2MPS15_REG_LDODVS3,
63*4882a593Smuzhiyun 	S2MPS15_REG_LDODVS4,
64*4882a593Smuzhiyun 	S2MPS15_REG_L1CTRL,
65*4882a593Smuzhiyun 	S2MPS15_REG_L2CTRL,
66*4882a593Smuzhiyun 	S2MPS15_REG_L3CTRL,
67*4882a593Smuzhiyun 	S2MPS15_REG_L4CTRL,
68*4882a593Smuzhiyun 	S2MPS15_REG_L5CTRL,
69*4882a593Smuzhiyun 	S2MPS15_REG_L6CTRL,
70*4882a593Smuzhiyun 	S2MPS15_REG_L7CTRL,
71*4882a593Smuzhiyun 	S2MPS15_REG_L8CTRL,
72*4882a593Smuzhiyun 	S2MPS15_REG_L9CTRL,
73*4882a593Smuzhiyun 	S2MPS15_REG_L10CTRL,
74*4882a593Smuzhiyun 	S2MPS15_REG_L11CTRL,
75*4882a593Smuzhiyun 	S2MPS15_REG_L12CTRL,
76*4882a593Smuzhiyun 	S2MPS15_REG_L13CTRL,
77*4882a593Smuzhiyun 	S2MPS15_REG_L14CTRL,
78*4882a593Smuzhiyun 	S2MPS15_REG_L15CTRL,
79*4882a593Smuzhiyun 	S2MPS15_REG_L16CTRL,
80*4882a593Smuzhiyun 	S2MPS15_REG_L17CTRL,
81*4882a593Smuzhiyun 	S2MPS15_REG_L18CTRL,
82*4882a593Smuzhiyun 	S2MPS15_REG_L19CTRL,
83*4882a593Smuzhiyun 	S2MPS15_REG_L20CTRL,
84*4882a593Smuzhiyun 	S2MPS15_REG_L21CTRL,
85*4882a593Smuzhiyun 	S2MPS15_REG_L22CTRL,
86*4882a593Smuzhiyun 	S2MPS15_REG_L23CTRL,
87*4882a593Smuzhiyun 	S2MPS15_REG_L24CTRL,
88*4882a593Smuzhiyun 	S2MPS15_REG_L25CTRL,
89*4882a593Smuzhiyun 	S2MPS15_REG_L26CTRL,
90*4882a593Smuzhiyun 	S2MPS15_REG_L27CTRL,
91*4882a593Smuzhiyun 	S2MPS15_REG_LDODSCH1,
92*4882a593Smuzhiyun 	S2MPS15_REG_LDODSCH2,
93*4882a593Smuzhiyun 	S2MPS15_REG_LDODSCH3,
94*4882a593Smuzhiyun 	S2MPS15_REG_LDODSCH4,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* S2MPS15 regulator ids */
98*4882a593Smuzhiyun enum s2mps15_regulators {
99*4882a593Smuzhiyun 	S2MPS15_LDO1,
100*4882a593Smuzhiyun 	S2MPS15_LDO2,
101*4882a593Smuzhiyun 	S2MPS15_LDO3,
102*4882a593Smuzhiyun 	S2MPS15_LDO4,
103*4882a593Smuzhiyun 	S2MPS15_LDO5,
104*4882a593Smuzhiyun 	S2MPS15_LDO6,
105*4882a593Smuzhiyun 	S2MPS15_LDO7,
106*4882a593Smuzhiyun 	S2MPS15_LDO8,
107*4882a593Smuzhiyun 	S2MPS15_LDO9,
108*4882a593Smuzhiyun 	S2MPS15_LDO10,
109*4882a593Smuzhiyun 	S2MPS15_LDO11,
110*4882a593Smuzhiyun 	S2MPS15_LDO12,
111*4882a593Smuzhiyun 	S2MPS15_LDO13,
112*4882a593Smuzhiyun 	S2MPS15_LDO14,
113*4882a593Smuzhiyun 	S2MPS15_LDO15,
114*4882a593Smuzhiyun 	S2MPS15_LDO16,
115*4882a593Smuzhiyun 	S2MPS15_LDO17,
116*4882a593Smuzhiyun 	S2MPS15_LDO18,
117*4882a593Smuzhiyun 	S2MPS15_LDO19,
118*4882a593Smuzhiyun 	S2MPS15_LDO20,
119*4882a593Smuzhiyun 	S2MPS15_LDO21,
120*4882a593Smuzhiyun 	S2MPS15_LDO22,
121*4882a593Smuzhiyun 	S2MPS15_LDO23,
122*4882a593Smuzhiyun 	S2MPS15_LDO24,
123*4882a593Smuzhiyun 	S2MPS15_LDO25,
124*4882a593Smuzhiyun 	S2MPS15_LDO26,
125*4882a593Smuzhiyun 	S2MPS15_LDO27,
126*4882a593Smuzhiyun 	S2MPS15_BUCK1,
127*4882a593Smuzhiyun 	S2MPS15_BUCK2,
128*4882a593Smuzhiyun 	S2MPS15_BUCK3,
129*4882a593Smuzhiyun 	S2MPS15_BUCK4,
130*4882a593Smuzhiyun 	S2MPS15_BUCK5,
131*4882a593Smuzhiyun 	S2MPS15_BUCK6,
132*4882a593Smuzhiyun 	S2MPS15_BUCK7,
133*4882a593Smuzhiyun 	S2MPS15_BUCK8,
134*4882a593Smuzhiyun 	S2MPS15_BUCK9,
135*4882a593Smuzhiyun 	S2MPS15_BUCK10,
136*4882a593Smuzhiyun 	S2MPS15_BUCK11,
137*4882a593Smuzhiyun 	S2MPS15_REGULATOR_MAX,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun #define S2MPS15_LDO_VSEL_MASK		(0x3F)
141*4882a593Smuzhiyun #define S2MPS15_BUCK_VSEL_MASK		(0xFF)
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define S2MPS15_ENABLE_SHIFT		(0x06)
144*4882a593Smuzhiyun #define S2MPS15_ENABLE_MASK		(0x03 << S2MPS15_ENABLE_SHIFT)
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #define S2MPS15_LDO_N_VOLTAGES		(S2MPS15_LDO_VSEL_MASK + 1)
147*4882a593Smuzhiyun #define S2MPS15_BUCK_N_VOLTAGES	(S2MPS15_BUCK_VSEL_MASK + 1)
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun #endif /* __LINUX_MFD_S2MPS15_H */
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