xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/s2mps14.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *              http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_S2MPS14_H
8*4882a593Smuzhiyun #define __LINUX_MFD_S2MPS14_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* S2MPS14 registers */
11*4882a593Smuzhiyun enum s2mps14_reg {
12*4882a593Smuzhiyun 	S2MPS14_REG_ID,
13*4882a593Smuzhiyun 	S2MPS14_REG_INT1,
14*4882a593Smuzhiyun 	S2MPS14_REG_INT2,
15*4882a593Smuzhiyun 	S2MPS14_REG_INT3,
16*4882a593Smuzhiyun 	S2MPS14_REG_INT1M,
17*4882a593Smuzhiyun 	S2MPS14_REG_INT2M,
18*4882a593Smuzhiyun 	S2MPS14_REG_INT3M,
19*4882a593Smuzhiyun 	S2MPS14_REG_ST1,
20*4882a593Smuzhiyun 	S2MPS14_REG_ST2,
21*4882a593Smuzhiyun 	S2MPS14_REG_PWRONSRC,
22*4882a593Smuzhiyun 	S2MPS14_REG_OFFSRC,
23*4882a593Smuzhiyun 	S2MPS14_REG_BU_CHG,
24*4882a593Smuzhiyun 	S2MPS14_REG_RTCCTRL,
25*4882a593Smuzhiyun 	S2MPS14_REG_CTRL1,
26*4882a593Smuzhiyun 	S2MPS14_REG_CTRL2,
27*4882a593Smuzhiyun 	S2MPS14_REG_RSVD1,
28*4882a593Smuzhiyun 	S2MPS14_REG_RSVD2,
29*4882a593Smuzhiyun 	S2MPS14_REG_RSVD3,
30*4882a593Smuzhiyun 	S2MPS14_REG_RSVD4,
31*4882a593Smuzhiyun 	S2MPS14_REG_RSVD5,
32*4882a593Smuzhiyun 	S2MPS14_REG_RSVD6,
33*4882a593Smuzhiyun 	S2MPS14_REG_CTRL3,
34*4882a593Smuzhiyun 	S2MPS14_REG_RSVD7,
35*4882a593Smuzhiyun 	S2MPS14_REG_RSVD8,
36*4882a593Smuzhiyun 	S2MPS14_REG_WRSTBI,
37*4882a593Smuzhiyun 	S2MPS14_REG_B1CTRL1,
38*4882a593Smuzhiyun 	S2MPS14_REG_B1CTRL2,
39*4882a593Smuzhiyun 	S2MPS14_REG_B2CTRL1,
40*4882a593Smuzhiyun 	S2MPS14_REG_B2CTRL2,
41*4882a593Smuzhiyun 	S2MPS14_REG_B3CTRL1,
42*4882a593Smuzhiyun 	S2MPS14_REG_B3CTRL2,
43*4882a593Smuzhiyun 	S2MPS14_REG_B4CTRL1,
44*4882a593Smuzhiyun 	S2MPS14_REG_B4CTRL2,
45*4882a593Smuzhiyun 	S2MPS14_REG_B5CTRL1,
46*4882a593Smuzhiyun 	S2MPS14_REG_B5CTRL2,
47*4882a593Smuzhiyun 	S2MPS14_REG_L1CTRL,
48*4882a593Smuzhiyun 	S2MPS14_REG_L2CTRL,
49*4882a593Smuzhiyun 	S2MPS14_REG_L3CTRL,
50*4882a593Smuzhiyun 	S2MPS14_REG_L4CTRL,
51*4882a593Smuzhiyun 	S2MPS14_REG_L5CTRL,
52*4882a593Smuzhiyun 	S2MPS14_REG_L6CTRL,
53*4882a593Smuzhiyun 	S2MPS14_REG_L7CTRL,
54*4882a593Smuzhiyun 	S2MPS14_REG_L8CTRL,
55*4882a593Smuzhiyun 	S2MPS14_REG_L9CTRL,
56*4882a593Smuzhiyun 	S2MPS14_REG_L10CTRL,
57*4882a593Smuzhiyun 	S2MPS14_REG_L11CTRL,
58*4882a593Smuzhiyun 	S2MPS14_REG_L12CTRL,
59*4882a593Smuzhiyun 	S2MPS14_REG_L13CTRL,
60*4882a593Smuzhiyun 	S2MPS14_REG_L14CTRL,
61*4882a593Smuzhiyun 	S2MPS14_REG_L15CTRL,
62*4882a593Smuzhiyun 	S2MPS14_REG_L16CTRL,
63*4882a593Smuzhiyun 	S2MPS14_REG_L17CTRL,
64*4882a593Smuzhiyun 	S2MPS14_REG_L18CTRL,
65*4882a593Smuzhiyun 	S2MPS14_REG_L19CTRL,
66*4882a593Smuzhiyun 	S2MPS14_REG_L20CTRL,
67*4882a593Smuzhiyun 	S2MPS14_REG_L21CTRL,
68*4882a593Smuzhiyun 	S2MPS14_REG_L22CTRL,
69*4882a593Smuzhiyun 	S2MPS14_REG_L23CTRL,
70*4882a593Smuzhiyun 	S2MPS14_REG_L24CTRL,
71*4882a593Smuzhiyun 	S2MPS14_REG_L25CTRL,
72*4882a593Smuzhiyun 	S2MPS14_REG_LDODSCH1,
73*4882a593Smuzhiyun 	S2MPS14_REG_LDODSCH2,
74*4882a593Smuzhiyun 	S2MPS14_REG_LDODSCH3,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* S2MPS14 regulator ids */
78*4882a593Smuzhiyun enum s2mps14_regulators {
79*4882a593Smuzhiyun 	S2MPS14_LDO1,
80*4882a593Smuzhiyun 	S2MPS14_LDO2,
81*4882a593Smuzhiyun 	S2MPS14_LDO3,
82*4882a593Smuzhiyun 	S2MPS14_LDO4,
83*4882a593Smuzhiyun 	S2MPS14_LDO5,
84*4882a593Smuzhiyun 	S2MPS14_LDO6,
85*4882a593Smuzhiyun 	S2MPS14_LDO7,
86*4882a593Smuzhiyun 	S2MPS14_LDO8,
87*4882a593Smuzhiyun 	S2MPS14_LDO9,
88*4882a593Smuzhiyun 	S2MPS14_LDO10,
89*4882a593Smuzhiyun 	S2MPS14_LDO11,
90*4882a593Smuzhiyun 	S2MPS14_LDO12,
91*4882a593Smuzhiyun 	S2MPS14_LDO13,
92*4882a593Smuzhiyun 	S2MPS14_LDO14,
93*4882a593Smuzhiyun 	S2MPS14_LDO15,
94*4882a593Smuzhiyun 	S2MPS14_LDO16,
95*4882a593Smuzhiyun 	S2MPS14_LDO17,
96*4882a593Smuzhiyun 	S2MPS14_LDO18,
97*4882a593Smuzhiyun 	S2MPS14_LDO19,
98*4882a593Smuzhiyun 	S2MPS14_LDO20,
99*4882a593Smuzhiyun 	S2MPS14_LDO21,
100*4882a593Smuzhiyun 	S2MPS14_LDO22,
101*4882a593Smuzhiyun 	S2MPS14_LDO23,
102*4882a593Smuzhiyun 	S2MPS14_LDO24,
103*4882a593Smuzhiyun 	S2MPS14_LDO25,
104*4882a593Smuzhiyun 	S2MPS14_BUCK1,
105*4882a593Smuzhiyun 	S2MPS14_BUCK2,
106*4882a593Smuzhiyun 	S2MPS14_BUCK3,
107*4882a593Smuzhiyun 	S2MPS14_BUCK4,
108*4882a593Smuzhiyun 	S2MPS14_BUCK5,
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	S2MPS14_REGULATOR_MAX,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* Regulator constraints for BUCKx */
114*4882a593Smuzhiyun #define S2MPS14_BUCK1235_START_SEL	0x20
115*4882a593Smuzhiyun #define S2MPS14_BUCK4_START_SEL		0x40
116*4882a593Smuzhiyun /*
117*4882a593Smuzhiyun  * Default ramp delay in uv/us. Datasheet says that ramp delay can be
118*4882a593Smuzhiyun  * controlled however it does not specify which register is used for that.
119*4882a593Smuzhiyun  * Let's assume that default value will be set.
120*4882a593Smuzhiyun  */
121*4882a593Smuzhiyun #define S2MPS14_BUCK_RAMP_DELAY		12500
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun #define S2MPS14_LDO_VSEL_MASK		0x3F
124*4882a593Smuzhiyun #define S2MPS14_BUCK_VSEL_MASK		0xFF
125*4882a593Smuzhiyun #define S2MPS14_ENABLE_MASK		(0x03 << S2MPS14_ENABLE_SHIFT)
126*4882a593Smuzhiyun #define S2MPS14_ENABLE_SHIFT		6
127*4882a593Smuzhiyun /* On/Off controlled by PWREN */
128*4882a593Smuzhiyun #define S2MPS14_ENABLE_SUSPEND		(0x01 << S2MPS14_ENABLE_SHIFT)
129*4882a593Smuzhiyun /* On/Off controlled by LDO10EN or EMMCEN */
130*4882a593Smuzhiyun #define S2MPS14_ENABLE_EXT_CONTROL	(0x00 << S2MPS14_ENABLE_SHIFT)
131*4882a593Smuzhiyun #define S2MPS14_LDO_N_VOLTAGES		(S2MPS14_LDO_VSEL_MASK + 1)
132*4882a593Smuzhiyun #define S2MPS14_BUCK_N_VOLTAGES		(S2MPS14_BUCK_VSEL_MASK + 1)
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun #endif /*  __LINUX_MFD_S2MPS14_H */
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