xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/s2mps13.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *              http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_S2MPS13_H
8*4882a593Smuzhiyun #define __LINUX_MFD_S2MPS13_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* S2MPS13 registers */
11*4882a593Smuzhiyun enum s2mps13_reg {
12*4882a593Smuzhiyun 	S2MPS13_REG_ID,
13*4882a593Smuzhiyun 	S2MPS13_REG_INT1,
14*4882a593Smuzhiyun 	S2MPS13_REG_INT2,
15*4882a593Smuzhiyun 	S2MPS13_REG_INT3,
16*4882a593Smuzhiyun 	S2MPS13_REG_INT1M,
17*4882a593Smuzhiyun 	S2MPS13_REG_INT2M,
18*4882a593Smuzhiyun 	S2MPS13_REG_INT3M,
19*4882a593Smuzhiyun 	S2MPS13_REG_ST1,
20*4882a593Smuzhiyun 	S2MPS13_REG_ST2,
21*4882a593Smuzhiyun 	S2MPS13_REG_PWRONSRC,
22*4882a593Smuzhiyun 	S2MPS13_REG_OFFSRC,
23*4882a593Smuzhiyun 	S2MPS13_REG_BU_CHG,
24*4882a593Smuzhiyun 	S2MPS13_REG_RTCCTRL,
25*4882a593Smuzhiyun 	S2MPS13_REG_CTRL1,
26*4882a593Smuzhiyun 	S2MPS13_REG_CTRL2,
27*4882a593Smuzhiyun 	S2MPS13_REG_RSVD1,
28*4882a593Smuzhiyun 	S2MPS13_REG_RSVD2,
29*4882a593Smuzhiyun 	S2MPS13_REG_RSVD3,
30*4882a593Smuzhiyun 	S2MPS13_REG_RSVD4,
31*4882a593Smuzhiyun 	S2MPS13_REG_RSVD5,
32*4882a593Smuzhiyun 	S2MPS13_REG_RSVD6,
33*4882a593Smuzhiyun 	S2MPS13_REG_CTRL3,
34*4882a593Smuzhiyun 	S2MPS13_REG_RSVD7,
35*4882a593Smuzhiyun 	S2MPS13_REG_RSVD8,
36*4882a593Smuzhiyun 	S2MPS13_REG_WRSTBI,
37*4882a593Smuzhiyun 	S2MPS13_REG_B1CTRL,
38*4882a593Smuzhiyun 	S2MPS13_REG_B1OUT,
39*4882a593Smuzhiyun 	S2MPS13_REG_B2CTRL,
40*4882a593Smuzhiyun 	S2MPS13_REG_B2OUT,
41*4882a593Smuzhiyun 	S2MPS13_REG_B3CTRL,
42*4882a593Smuzhiyun 	S2MPS13_REG_B3OUT,
43*4882a593Smuzhiyun 	S2MPS13_REG_B4CTRL,
44*4882a593Smuzhiyun 	S2MPS13_REG_B4OUT,
45*4882a593Smuzhiyun 	S2MPS13_REG_B5CTRL,
46*4882a593Smuzhiyun 	S2MPS13_REG_B5OUT,
47*4882a593Smuzhiyun 	S2MPS13_REG_B6CTRL,
48*4882a593Smuzhiyun 	S2MPS13_REG_B6OUT,
49*4882a593Smuzhiyun 	S2MPS13_REG_B7CTRL,
50*4882a593Smuzhiyun 	S2MPS13_REG_B7SW,
51*4882a593Smuzhiyun 	S2MPS13_REG_B7OUT,
52*4882a593Smuzhiyun 	S2MPS13_REG_B8CTRL,
53*4882a593Smuzhiyun 	S2MPS13_REG_B8OUT,
54*4882a593Smuzhiyun 	S2MPS13_REG_B9CTRL,
55*4882a593Smuzhiyun 	S2MPS13_REG_B9OUT,
56*4882a593Smuzhiyun 	S2MPS13_REG_B10CTRL,
57*4882a593Smuzhiyun 	S2MPS13_REG_B10OUT,
58*4882a593Smuzhiyun 	S2MPS13_REG_BB1CTRL,
59*4882a593Smuzhiyun 	S2MPS13_REG_BB1OUT,
60*4882a593Smuzhiyun 	S2MPS13_REG_BUCK_RAMP1,
61*4882a593Smuzhiyun 	S2MPS13_REG_BUCK_RAMP2,
62*4882a593Smuzhiyun 	S2MPS13_REG_LDO_DVS1,
63*4882a593Smuzhiyun 	S2MPS13_REG_LDO_DVS2,
64*4882a593Smuzhiyun 	S2MPS13_REG_LDO_DVS3,
65*4882a593Smuzhiyun 	S2MPS13_REG_B6OUT2,
66*4882a593Smuzhiyun 	S2MPS13_REG_L1CTRL,
67*4882a593Smuzhiyun 	S2MPS13_REG_L2CTRL,
68*4882a593Smuzhiyun 	S2MPS13_REG_L3CTRL,
69*4882a593Smuzhiyun 	S2MPS13_REG_L4CTRL,
70*4882a593Smuzhiyun 	S2MPS13_REG_L5CTRL,
71*4882a593Smuzhiyun 	S2MPS13_REG_L6CTRL,
72*4882a593Smuzhiyun 	S2MPS13_REG_L7CTRL,
73*4882a593Smuzhiyun 	S2MPS13_REG_L8CTRL,
74*4882a593Smuzhiyun 	S2MPS13_REG_L9CTRL,
75*4882a593Smuzhiyun 	S2MPS13_REG_L10CTRL,
76*4882a593Smuzhiyun 	S2MPS13_REG_L11CTRL,
77*4882a593Smuzhiyun 	S2MPS13_REG_L12CTRL,
78*4882a593Smuzhiyun 	S2MPS13_REG_L13CTRL,
79*4882a593Smuzhiyun 	S2MPS13_REG_L14CTRL,
80*4882a593Smuzhiyun 	S2MPS13_REG_L15CTRL,
81*4882a593Smuzhiyun 	S2MPS13_REG_L16CTRL,
82*4882a593Smuzhiyun 	S2MPS13_REG_L17CTRL,
83*4882a593Smuzhiyun 	S2MPS13_REG_L18CTRL,
84*4882a593Smuzhiyun 	S2MPS13_REG_L19CTRL,
85*4882a593Smuzhiyun 	S2MPS13_REG_L20CTRL,
86*4882a593Smuzhiyun 	S2MPS13_REG_L21CTRL,
87*4882a593Smuzhiyun 	S2MPS13_REG_L22CTRL,
88*4882a593Smuzhiyun 	S2MPS13_REG_L23CTRL,
89*4882a593Smuzhiyun 	S2MPS13_REG_L24CTRL,
90*4882a593Smuzhiyun 	S2MPS13_REG_L25CTRL,
91*4882a593Smuzhiyun 	S2MPS13_REG_L26CTRL,
92*4882a593Smuzhiyun 	S2MPS13_REG_L27CTRL,
93*4882a593Smuzhiyun 	S2MPS13_REG_L28CTRL,
94*4882a593Smuzhiyun 	S2MPS13_REG_L29CTRL,
95*4882a593Smuzhiyun 	S2MPS13_REG_L30CTRL,
96*4882a593Smuzhiyun 	S2MPS13_REG_L31CTRL,
97*4882a593Smuzhiyun 	S2MPS13_REG_L32CTRL,
98*4882a593Smuzhiyun 	S2MPS13_REG_L33CTRL,
99*4882a593Smuzhiyun 	S2MPS13_REG_L34CTRL,
100*4882a593Smuzhiyun 	S2MPS13_REG_L35CTRL,
101*4882a593Smuzhiyun 	S2MPS13_REG_L36CTRL,
102*4882a593Smuzhiyun 	S2MPS13_REG_L37CTRL,
103*4882a593Smuzhiyun 	S2MPS13_REG_L38CTRL,
104*4882a593Smuzhiyun 	S2MPS13_REG_L39CTRL,
105*4882a593Smuzhiyun 	S2MPS13_REG_L40CTRL,
106*4882a593Smuzhiyun 	S2MPS13_REG_LDODSCH1,
107*4882a593Smuzhiyun 	S2MPS13_REG_LDODSCH2,
108*4882a593Smuzhiyun 	S2MPS13_REG_LDODSCH3,
109*4882a593Smuzhiyun 	S2MPS13_REG_LDODSCH4,
110*4882a593Smuzhiyun 	S2MPS13_REG_LDODSCH5,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /*  regulator ids */
114*4882a593Smuzhiyun enum s2mps13_regulators {
115*4882a593Smuzhiyun 	S2MPS13_LDO1,
116*4882a593Smuzhiyun 	S2MPS13_LDO2,
117*4882a593Smuzhiyun 	S2MPS13_LDO3,
118*4882a593Smuzhiyun 	S2MPS13_LDO4,
119*4882a593Smuzhiyun 	S2MPS13_LDO5,
120*4882a593Smuzhiyun 	S2MPS13_LDO6,
121*4882a593Smuzhiyun 	S2MPS13_LDO7,
122*4882a593Smuzhiyun 	S2MPS13_LDO8,
123*4882a593Smuzhiyun 	S2MPS13_LDO9,
124*4882a593Smuzhiyun 	S2MPS13_LDO10,
125*4882a593Smuzhiyun 	S2MPS13_LDO11,
126*4882a593Smuzhiyun 	S2MPS13_LDO12,
127*4882a593Smuzhiyun 	S2MPS13_LDO13,
128*4882a593Smuzhiyun 	S2MPS13_LDO14,
129*4882a593Smuzhiyun 	S2MPS13_LDO15,
130*4882a593Smuzhiyun 	S2MPS13_LDO16,
131*4882a593Smuzhiyun 	S2MPS13_LDO17,
132*4882a593Smuzhiyun 	S2MPS13_LDO18,
133*4882a593Smuzhiyun 	S2MPS13_LDO19,
134*4882a593Smuzhiyun 	S2MPS13_LDO20,
135*4882a593Smuzhiyun 	S2MPS13_LDO21,
136*4882a593Smuzhiyun 	S2MPS13_LDO22,
137*4882a593Smuzhiyun 	S2MPS13_LDO23,
138*4882a593Smuzhiyun 	S2MPS13_LDO24,
139*4882a593Smuzhiyun 	S2MPS13_LDO25,
140*4882a593Smuzhiyun 	S2MPS13_LDO26,
141*4882a593Smuzhiyun 	S2MPS13_LDO27,
142*4882a593Smuzhiyun 	S2MPS13_LDO28,
143*4882a593Smuzhiyun 	S2MPS13_LDO29,
144*4882a593Smuzhiyun 	S2MPS13_LDO30,
145*4882a593Smuzhiyun 	S2MPS13_LDO31,
146*4882a593Smuzhiyun 	S2MPS13_LDO32,
147*4882a593Smuzhiyun 	S2MPS13_LDO33,
148*4882a593Smuzhiyun 	S2MPS13_LDO34,
149*4882a593Smuzhiyun 	S2MPS13_LDO35,
150*4882a593Smuzhiyun 	S2MPS13_LDO36,
151*4882a593Smuzhiyun 	S2MPS13_LDO37,
152*4882a593Smuzhiyun 	S2MPS13_LDO38,
153*4882a593Smuzhiyun 	S2MPS13_LDO39,
154*4882a593Smuzhiyun 	S2MPS13_LDO40,
155*4882a593Smuzhiyun 	S2MPS13_BUCK1,
156*4882a593Smuzhiyun 	S2MPS13_BUCK2,
157*4882a593Smuzhiyun 	S2MPS13_BUCK3,
158*4882a593Smuzhiyun 	S2MPS13_BUCK4,
159*4882a593Smuzhiyun 	S2MPS13_BUCK5,
160*4882a593Smuzhiyun 	S2MPS13_BUCK6,
161*4882a593Smuzhiyun 	S2MPS13_BUCK7,
162*4882a593Smuzhiyun 	S2MPS13_BUCK8,
163*4882a593Smuzhiyun 	S2MPS13_BUCK9,
164*4882a593Smuzhiyun 	S2MPS13_BUCK10,
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	S2MPS13_REGULATOR_MAX,
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun  * Default ramp delay in uv/us. Datasheet says that ramp delay can be
171*4882a593Smuzhiyun  * controlled however it does not specify which register is used for that.
172*4882a593Smuzhiyun  * Let's assume that default value will be set.
173*4882a593Smuzhiyun  */
174*4882a593Smuzhiyun #define S2MPS13_BUCK_RAMP_DELAY		12500
175*4882a593Smuzhiyun #define S2MPS13_REG_WRSTBI_MASK		BIT(5)
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun #endif /*  __LINUX_MFD_S2MPS13_H */
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