xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/s2mps11.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2012 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *              http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_S2MPS11_H
8*4882a593Smuzhiyun #define __LINUX_MFD_S2MPS11_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* S2MPS11 registers */
11*4882a593Smuzhiyun enum s2mps11_reg {
12*4882a593Smuzhiyun 	S2MPS11_REG_ID,
13*4882a593Smuzhiyun 	S2MPS11_REG_INT1,
14*4882a593Smuzhiyun 	S2MPS11_REG_INT2,
15*4882a593Smuzhiyun 	S2MPS11_REG_INT3,
16*4882a593Smuzhiyun 	S2MPS11_REG_INT1M,
17*4882a593Smuzhiyun 	S2MPS11_REG_INT2M,
18*4882a593Smuzhiyun 	S2MPS11_REG_INT3M,
19*4882a593Smuzhiyun 	S2MPS11_REG_ST1,
20*4882a593Smuzhiyun 	S2MPS11_REG_ST2,
21*4882a593Smuzhiyun 	S2MPS11_REG_OFFSRC,
22*4882a593Smuzhiyun 	S2MPS11_REG_PWRONSRC,
23*4882a593Smuzhiyun 	S2MPS11_REG_RTC_CTRL,
24*4882a593Smuzhiyun 	S2MPS11_REG_CTRL1,
25*4882a593Smuzhiyun 	S2MPS11_REG_ETC_TEST,
26*4882a593Smuzhiyun 	S2MPS11_REG_RSVD3,
27*4882a593Smuzhiyun 	S2MPS11_REG_BU_CHG,
28*4882a593Smuzhiyun 	S2MPS11_REG_RAMP,
29*4882a593Smuzhiyun 	S2MPS11_REG_RAMP_BUCK,
30*4882a593Smuzhiyun 	S2MPS11_REG_LDO1_8,
31*4882a593Smuzhiyun 	S2MPS11_REG_LDO9_16,
32*4882a593Smuzhiyun 	S2MPS11_REG_LDO17_24,
33*4882a593Smuzhiyun 	S2MPS11_REG_LDO25_32,
34*4882a593Smuzhiyun 	S2MPS11_REG_LDO33_38,
35*4882a593Smuzhiyun 	S2MPS11_REG_LDO1_8_1,
36*4882a593Smuzhiyun 	S2MPS11_REG_LDO9_16_1,
37*4882a593Smuzhiyun 	S2MPS11_REG_LDO17_24_1,
38*4882a593Smuzhiyun 	S2MPS11_REG_LDO25_32_1,
39*4882a593Smuzhiyun 	S2MPS11_REG_LDO33_38_1,
40*4882a593Smuzhiyun 	S2MPS11_REG_OTP_ADRL,
41*4882a593Smuzhiyun 	S2MPS11_REG_OTP_ADRH,
42*4882a593Smuzhiyun 	S2MPS11_REG_OTP_DATA,
43*4882a593Smuzhiyun 	S2MPS11_REG_MON1SEL,
44*4882a593Smuzhiyun 	S2MPS11_REG_MON2SEL,
45*4882a593Smuzhiyun 	S2MPS11_REG_LEE,
46*4882a593Smuzhiyun 	S2MPS11_REG_RSVD_NO,
47*4882a593Smuzhiyun 	S2MPS11_REG_UVLO,
48*4882a593Smuzhiyun 	S2MPS11_REG_LEE_NO,
49*4882a593Smuzhiyun 	S2MPS11_REG_B1CTRL1,
50*4882a593Smuzhiyun 	S2MPS11_REG_B1CTRL2,
51*4882a593Smuzhiyun 	S2MPS11_REG_B2CTRL1,
52*4882a593Smuzhiyun 	S2MPS11_REG_B2CTRL2,
53*4882a593Smuzhiyun 	S2MPS11_REG_B3CTRL1,
54*4882a593Smuzhiyun 	S2MPS11_REG_B3CTRL2,
55*4882a593Smuzhiyun 	S2MPS11_REG_B4CTRL1,
56*4882a593Smuzhiyun 	S2MPS11_REG_B4CTRL2,
57*4882a593Smuzhiyun 	S2MPS11_REG_B5CTRL1,
58*4882a593Smuzhiyun 	S2MPS11_REG_BUCK5_SW,
59*4882a593Smuzhiyun 	S2MPS11_REG_B5CTRL2,
60*4882a593Smuzhiyun 	S2MPS11_REG_B5CTRL3,
61*4882a593Smuzhiyun 	S2MPS11_REG_B5CTRL4,
62*4882a593Smuzhiyun 	S2MPS11_REG_B5CTRL5,
63*4882a593Smuzhiyun 	S2MPS11_REG_B6CTRL1,
64*4882a593Smuzhiyun 	S2MPS11_REG_B6CTRL2,
65*4882a593Smuzhiyun 	S2MPS11_REG_B7CTRL1,
66*4882a593Smuzhiyun 	S2MPS11_REG_B7CTRL2,
67*4882a593Smuzhiyun 	S2MPS11_REG_B8CTRL1,
68*4882a593Smuzhiyun 	S2MPS11_REG_B8CTRL2,
69*4882a593Smuzhiyun 	S2MPS11_REG_B9CTRL1,
70*4882a593Smuzhiyun 	S2MPS11_REG_B9CTRL2,
71*4882a593Smuzhiyun 	S2MPS11_REG_B10CTRL1,
72*4882a593Smuzhiyun 	S2MPS11_REG_B10CTRL2,
73*4882a593Smuzhiyun 	S2MPS11_REG_L1CTRL,
74*4882a593Smuzhiyun 	S2MPS11_REG_L2CTRL,
75*4882a593Smuzhiyun 	S2MPS11_REG_L3CTRL,
76*4882a593Smuzhiyun 	S2MPS11_REG_L4CTRL,
77*4882a593Smuzhiyun 	S2MPS11_REG_L5CTRL,
78*4882a593Smuzhiyun 	S2MPS11_REG_L6CTRL,
79*4882a593Smuzhiyun 	S2MPS11_REG_L7CTRL,
80*4882a593Smuzhiyun 	S2MPS11_REG_L8CTRL,
81*4882a593Smuzhiyun 	S2MPS11_REG_L9CTRL,
82*4882a593Smuzhiyun 	S2MPS11_REG_L10CTRL,
83*4882a593Smuzhiyun 	S2MPS11_REG_L11CTRL,
84*4882a593Smuzhiyun 	S2MPS11_REG_L12CTRL,
85*4882a593Smuzhiyun 	S2MPS11_REG_L13CTRL,
86*4882a593Smuzhiyun 	S2MPS11_REG_L14CTRL,
87*4882a593Smuzhiyun 	S2MPS11_REG_L15CTRL,
88*4882a593Smuzhiyun 	S2MPS11_REG_L16CTRL,
89*4882a593Smuzhiyun 	S2MPS11_REG_L17CTRL,
90*4882a593Smuzhiyun 	S2MPS11_REG_L18CTRL,
91*4882a593Smuzhiyun 	S2MPS11_REG_L19CTRL,
92*4882a593Smuzhiyun 	S2MPS11_REG_L20CTRL,
93*4882a593Smuzhiyun 	S2MPS11_REG_L21CTRL,
94*4882a593Smuzhiyun 	S2MPS11_REG_L22CTRL,
95*4882a593Smuzhiyun 	S2MPS11_REG_L23CTRL,
96*4882a593Smuzhiyun 	S2MPS11_REG_L24CTRL,
97*4882a593Smuzhiyun 	S2MPS11_REG_L25CTRL,
98*4882a593Smuzhiyun 	S2MPS11_REG_L26CTRL,
99*4882a593Smuzhiyun 	S2MPS11_REG_L27CTRL,
100*4882a593Smuzhiyun 	S2MPS11_REG_L28CTRL,
101*4882a593Smuzhiyun 	S2MPS11_REG_L29CTRL,
102*4882a593Smuzhiyun 	S2MPS11_REG_L30CTRL,
103*4882a593Smuzhiyun 	S2MPS11_REG_L31CTRL,
104*4882a593Smuzhiyun 	S2MPS11_REG_L32CTRL,
105*4882a593Smuzhiyun 	S2MPS11_REG_L33CTRL,
106*4882a593Smuzhiyun 	S2MPS11_REG_L34CTRL,
107*4882a593Smuzhiyun 	S2MPS11_REG_L35CTRL,
108*4882a593Smuzhiyun 	S2MPS11_REG_L36CTRL,
109*4882a593Smuzhiyun 	S2MPS11_REG_L37CTRL,
110*4882a593Smuzhiyun 	S2MPS11_REG_L38CTRL,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* S2MPS11 regulator ids */
114*4882a593Smuzhiyun enum s2mps11_regulators {
115*4882a593Smuzhiyun 	S2MPS11_LDO1,
116*4882a593Smuzhiyun 	S2MPS11_LDO2,
117*4882a593Smuzhiyun 	S2MPS11_LDO3,
118*4882a593Smuzhiyun 	S2MPS11_LDO4,
119*4882a593Smuzhiyun 	S2MPS11_LDO5,
120*4882a593Smuzhiyun 	S2MPS11_LDO6,
121*4882a593Smuzhiyun 	S2MPS11_LDO7,
122*4882a593Smuzhiyun 	S2MPS11_LDO8,
123*4882a593Smuzhiyun 	S2MPS11_LDO9,
124*4882a593Smuzhiyun 	S2MPS11_LDO10,
125*4882a593Smuzhiyun 	S2MPS11_LDO11,
126*4882a593Smuzhiyun 	S2MPS11_LDO12,
127*4882a593Smuzhiyun 	S2MPS11_LDO13,
128*4882a593Smuzhiyun 	S2MPS11_LDO14,
129*4882a593Smuzhiyun 	S2MPS11_LDO15,
130*4882a593Smuzhiyun 	S2MPS11_LDO16,
131*4882a593Smuzhiyun 	S2MPS11_LDO17,
132*4882a593Smuzhiyun 	S2MPS11_LDO18,
133*4882a593Smuzhiyun 	S2MPS11_LDO19,
134*4882a593Smuzhiyun 	S2MPS11_LDO20,
135*4882a593Smuzhiyun 	S2MPS11_LDO21,
136*4882a593Smuzhiyun 	S2MPS11_LDO22,
137*4882a593Smuzhiyun 	S2MPS11_LDO23,
138*4882a593Smuzhiyun 	S2MPS11_LDO24,
139*4882a593Smuzhiyun 	S2MPS11_LDO25,
140*4882a593Smuzhiyun 	S2MPS11_LDO26,
141*4882a593Smuzhiyun 	S2MPS11_LDO27,
142*4882a593Smuzhiyun 	S2MPS11_LDO28,
143*4882a593Smuzhiyun 	S2MPS11_LDO29,
144*4882a593Smuzhiyun 	S2MPS11_LDO30,
145*4882a593Smuzhiyun 	S2MPS11_LDO31,
146*4882a593Smuzhiyun 	S2MPS11_LDO32,
147*4882a593Smuzhiyun 	S2MPS11_LDO33,
148*4882a593Smuzhiyun 	S2MPS11_LDO34,
149*4882a593Smuzhiyun 	S2MPS11_LDO35,
150*4882a593Smuzhiyun 	S2MPS11_LDO36,
151*4882a593Smuzhiyun 	S2MPS11_LDO37,
152*4882a593Smuzhiyun 	S2MPS11_LDO38,
153*4882a593Smuzhiyun 	S2MPS11_BUCK1,
154*4882a593Smuzhiyun 	S2MPS11_BUCK2,
155*4882a593Smuzhiyun 	S2MPS11_BUCK3,
156*4882a593Smuzhiyun 	S2MPS11_BUCK4,
157*4882a593Smuzhiyun 	S2MPS11_BUCK5,
158*4882a593Smuzhiyun 	S2MPS11_BUCK6,
159*4882a593Smuzhiyun 	S2MPS11_BUCK7,
160*4882a593Smuzhiyun 	S2MPS11_BUCK8,
161*4882a593Smuzhiyun 	S2MPS11_BUCK9,
162*4882a593Smuzhiyun 	S2MPS11_BUCK10,
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	S2MPS11_REGULATOR_MAX,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define S2MPS11_LDO_VSEL_MASK	0x3F
168*4882a593Smuzhiyun #define S2MPS11_BUCK_VSEL_MASK	0xFF
169*4882a593Smuzhiyun #define S2MPS11_BUCK9_VSEL_MASK	0x1F
170*4882a593Smuzhiyun #define S2MPS11_ENABLE_MASK	(0x03 << S2MPS11_ENABLE_SHIFT)
171*4882a593Smuzhiyun #define S2MPS11_ENABLE_SHIFT	0x06
172*4882a593Smuzhiyun #define S2MPS11_LDO_N_VOLTAGES	(S2MPS11_LDO_VSEL_MASK + 1)
173*4882a593Smuzhiyun #define S2MPS11_BUCK12346_N_VOLTAGES	153
174*4882a593Smuzhiyun #define S2MPS11_BUCK5_N_VOLTAGES	216
175*4882a593Smuzhiyun #define S2MPS11_BUCK7810_N_VOLTAGES	225
176*4882a593Smuzhiyun #define S2MPS11_BUCK9_N_VOLTAGES (S2MPS11_BUCK9_VSEL_MASK + 1)
177*4882a593Smuzhiyun #define S2MPS11_RAMP_DELAY	25000		/* uV/us */
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun #define S2MPS11_CTRL1_PWRHOLD_MASK	BIT(4)
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun #define S2MPS11_BUCK2_RAMP_SHIFT	6
182*4882a593Smuzhiyun #define S2MPS11_BUCK34_RAMP_SHIFT	4
183*4882a593Smuzhiyun #define S2MPS11_BUCK5_RAMP_SHIFT	6
184*4882a593Smuzhiyun #define S2MPS11_BUCK16_RAMP_SHIFT	4
185*4882a593Smuzhiyun #define S2MPS11_BUCK7810_RAMP_SHIFT	2
186*4882a593Smuzhiyun #define S2MPS11_BUCK9_RAMP_SHIFT	0
187*4882a593Smuzhiyun #define S2MPS11_BUCK2_RAMP_EN_SHIFT	3
188*4882a593Smuzhiyun #define S2MPS11_BUCK3_RAMP_EN_SHIFT	2
189*4882a593Smuzhiyun #define S2MPS11_BUCK4_RAMP_EN_SHIFT	1
190*4882a593Smuzhiyun #define S2MPS11_BUCK6_RAMP_EN_SHIFT	0
191*4882a593Smuzhiyun #define S2MPS11_PMIC_EN_SHIFT	6
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun /*
194*4882a593Smuzhiyun  * Bits for "enable suspend" (On/Off controlled by PWREN)
195*4882a593Smuzhiyun  * are the same as in S2MPS14: S2MPS14_ENABLE_SUSPEND
196*4882a593Smuzhiyun  */
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #endif /*  __LINUX_MFD_S2MPS11_H */
199