xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/s2mpa01.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2013 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *		http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_S2MPA01_H
8*4882a593Smuzhiyun #define __LINUX_MFD_S2MPA01_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* S2MPA01 registers */
11*4882a593Smuzhiyun enum s2mpa01_reg {
12*4882a593Smuzhiyun 	S2MPA01_REG_ID,
13*4882a593Smuzhiyun 	S2MPA01_REG_INT1,
14*4882a593Smuzhiyun 	S2MPA01_REG_INT2,
15*4882a593Smuzhiyun 	S2MPA01_REG_INT3,
16*4882a593Smuzhiyun 	S2MPA01_REG_INT1M,
17*4882a593Smuzhiyun 	S2MPA01_REG_INT2M,
18*4882a593Smuzhiyun 	S2MPA01_REG_INT3M,
19*4882a593Smuzhiyun 	S2MPA01_REG_ST1,
20*4882a593Smuzhiyun 	S2MPA01_REG_ST2,
21*4882a593Smuzhiyun 	S2MPA01_REG_PWRONSRC,
22*4882a593Smuzhiyun 	S2MPA01_REG_OFFSRC,
23*4882a593Smuzhiyun 	S2MPA01_REG_RTC_BUF,
24*4882a593Smuzhiyun 	S2MPA01_REG_CTRL1,
25*4882a593Smuzhiyun 	S2MPA01_REG_ETC_TEST,
26*4882a593Smuzhiyun 	S2MPA01_REG_RSVD1,
27*4882a593Smuzhiyun 	S2MPA01_REG_BU_CHG,
28*4882a593Smuzhiyun 	S2MPA01_REG_RAMP1,
29*4882a593Smuzhiyun 	S2MPA01_REG_RAMP2,
30*4882a593Smuzhiyun 	S2MPA01_REG_LDO_DSCH1,
31*4882a593Smuzhiyun 	S2MPA01_REG_LDO_DSCH2,
32*4882a593Smuzhiyun 	S2MPA01_REG_LDO_DSCH3,
33*4882a593Smuzhiyun 	S2MPA01_REG_LDO_DSCH4,
34*4882a593Smuzhiyun 	S2MPA01_REG_OTP_ADRL,
35*4882a593Smuzhiyun 	S2MPA01_REG_OTP_ADRH,
36*4882a593Smuzhiyun 	S2MPA01_REG_OTP_DATA,
37*4882a593Smuzhiyun 	S2MPA01_REG_MON1SEL,
38*4882a593Smuzhiyun 	S2MPA01_REG_MON2SEL,
39*4882a593Smuzhiyun 	S2MPA01_REG_LEE,
40*4882a593Smuzhiyun 	S2MPA01_REG_RSVD2,
41*4882a593Smuzhiyun 	S2MPA01_REG_RSVD3,
42*4882a593Smuzhiyun 	S2MPA01_REG_RSVD4,
43*4882a593Smuzhiyun 	S2MPA01_REG_RSVD5,
44*4882a593Smuzhiyun 	S2MPA01_REG_RSVD6,
45*4882a593Smuzhiyun 	S2MPA01_REG_TOP_RSVD,
46*4882a593Smuzhiyun 	S2MPA01_REG_DVS_SEL,
47*4882a593Smuzhiyun 	S2MPA01_REG_DVS_PTR,
48*4882a593Smuzhiyun 	S2MPA01_REG_DVS_DATA,
49*4882a593Smuzhiyun 	S2MPA01_REG_RSVD_NO,
50*4882a593Smuzhiyun 	S2MPA01_REG_UVLO,
51*4882a593Smuzhiyun 	S2MPA01_REG_LEE_NO,
52*4882a593Smuzhiyun 	S2MPA01_REG_B1CTRL1,
53*4882a593Smuzhiyun 	S2MPA01_REG_B1CTRL2,
54*4882a593Smuzhiyun 	S2MPA01_REG_B2CTRL1,
55*4882a593Smuzhiyun 	S2MPA01_REG_B2CTRL2,
56*4882a593Smuzhiyun 	S2MPA01_REG_B3CTRL1,
57*4882a593Smuzhiyun 	S2MPA01_REG_B3CTRL2,
58*4882a593Smuzhiyun 	S2MPA01_REG_B4CTRL1,
59*4882a593Smuzhiyun 	S2MPA01_REG_B4CTRL2,
60*4882a593Smuzhiyun 	S2MPA01_REG_B5CTRL1,
61*4882a593Smuzhiyun 	S2MPA01_REG_B5CTRL2,
62*4882a593Smuzhiyun 	S2MPA01_REG_B5CTRL3,
63*4882a593Smuzhiyun 	S2MPA01_REG_B5CTRL4,
64*4882a593Smuzhiyun 	S2MPA01_REG_B5CTRL5,
65*4882a593Smuzhiyun 	S2MPA01_REG_B5CTRL6,
66*4882a593Smuzhiyun 	S2MPA01_REG_B6CTRL1,
67*4882a593Smuzhiyun 	S2MPA01_REG_B6CTRL2,
68*4882a593Smuzhiyun 	S2MPA01_REG_B7CTRL1,
69*4882a593Smuzhiyun 	S2MPA01_REG_B7CTRL2,
70*4882a593Smuzhiyun 	S2MPA01_REG_B8CTRL1,
71*4882a593Smuzhiyun 	S2MPA01_REG_B8CTRL2,
72*4882a593Smuzhiyun 	S2MPA01_REG_B9CTRL1,
73*4882a593Smuzhiyun 	S2MPA01_REG_B9CTRL2,
74*4882a593Smuzhiyun 	S2MPA01_REG_B10CTRL1,
75*4882a593Smuzhiyun 	S2MPA01_REG_B10CTRL2,
76*4882a593Smuzhiyun 	S2MPA01_REG_L1CTRL,
77*4882a593Smuzhiyun 	S2MPA01_REG_L2CTRL,
78*4882a593Smuzhiyun 	S2MPA01_REG_L3CTRL,
79*4882a593Smuzhiyun 	S2MPA01_REG_L4CTRL,
80*4882a593Smuzhiyun 	S2MPA01_REG_L5CTRL,
81*4882a593Smuzhiyun 	S2MPA01_REG_L6CTRL,
82*4882a593Smuzhiyun 	S2MPA01_REG_L7CTRL,
83*4882a593Smuzhiyun 	S2MPA01_REG_L8CTRL,
84*4882a593Smuzhiyun 	S2MPA01_REG_L9CTRL,
85*4882a593Smuzhiyun 	S2MPA01_REG_L10CTRL,
86*4882a593Smuzhiyun 	S2MPA01_REG_L11CTRL,
87*4882a593Smuzhiyun 	S2MPA01_REG_L12CTRL,
88*4882a593Smuzhiyun 	S2MPA01_REG_L13CTRL,
89*4882a593Smuzhiyun 	S2MPA01_REG_L14CTRL,
90*4882a593Smuzhiyun 	S2MPA01_REG_L15CTRL,
91*4882a593Smuzhiyun 	S2MPA01_REG_L16CTRL,
92*4882a593Smuzhiyun 	S2MPA01_REG_L17CTRL,
93*4882a593Smuzhiyun 	S2MPA01_REG_L18CTRL,
94*4882a593Smuzhiyun 	S2MPA01_REG_L19CTRL,
95*4882a593Smuzhiyun 	S2MPA01_REG_L20CTRL,
96*4882a593Smuzhiyun 	S2MPA01_REG_L21CTRL,
97*4882a593Smuzhiyun 	S2MPA01_REG_L22CTRL,
98*4882a593Smuzhiyun 	S2MPA01_REG_L23CTRL,
99*4882a593Smuzhiyun 	S2MPA01_REG_L24CTRL,
100*4882a593Smuzhiyun 	S2MPA01_REG_L25CTRL,
101*4882a593Smuzhiyun 	S2MPA01_REG_L26CTRL,
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	S2MPA01_REG_LDO_OVCB1,
104*4882a593Smuzhiyun 	S2MPA01_REG_LDO_OVCB2,
105*4882a593Smuzhiyun 	S2MPA01_REG_LDO_OVCB3,
106*4882a593Smuzhiyun 	S2MPA01_REG_LDO_OVCB4,
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* S2MPA01 regulator ids */
111*4882a593Smuzhiyun enum s2mpa01_regulators {
112*4882a593Smuzhiyun 	S2MPA01_LDO1,
113*4882a593Smuzhiyun 	S2MPA01_LDO2,
114*4882a593Smuzhiyun 	S2MPA01_LDO3,
115*4882a593Smuzhiyun 	S2MPA01_LDO4,
116*4882a593Smuzhiyun 	S2MPA01_LDO5,
117*4882a593Smuzhiyun 	S2MPA01_LDO6,
118*4882a593Smuzhiyun 	S2MPA01_LDO7,
119*4882a593Smuzhiyun 	S2MPA01_LDO8,
120*4882a593Smuzhiyun 	S2MPA01_LDO9,
121*4882a593Smuzhiyun 	S2MPA01_LDO10,
122*4882a593Smuzhiyun 	S2MPA01_LDO11,
123*4882a593Smuzhiyun 	S2MPA01_LDO12,
124*4882a593Smuzhiyun 	S2MPA01_LDO13,
125*4882a593Smuzhiyun 	S2MPA01_LDO14,
126*4882a593Smuzhiyun 	S2MPA01_LDO15,
127*4882a593Smuzhiyun 	S2MPA01_LDO16,
128*4882a593Smuzhiyun 	S2MPA01_LDO17,
129*4882a593Smuzhiyun 	S2MPA01_LDO18,
130*4882a593Smuzhiyun 	S2MPA01_LDO19,
131*4882a593Smuzhiyun 	S2MPA01_LDO20,
132*4882a593Smuzhiyun 	S2MPA01_LDO21,
133*4882a593Smuzhiyun 	S2MPA01_LDO22,
134*4882a593Smuzhiyun 	S2MPA01_LDO23,
135*4882a593Smuzhiyun 	S2MPA01_LDO24,
136*4882a593Smuzhiyun 	S2MPA01_LDO25,
137*4882a593Smuzhiyun 	S2MPA01_LDO26,
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	S2MPA01_BUCK1,
140*4882a593Smuzhiyun 	S2MPA01_BUCK2,
141*4882a593Smuzhiyun 	S2MPA01_BUCK3,
142*4882a593Smuzhiyun 	S2MPA01_BUCK4,
143*4882a593Smuzhiyun 	S2MPA01_BUCK5,
144*4882a593Smuzhiyun 	S2MPA01_BUCK6,
145*4882a593Smuzhiyun 	S2MPA01_BUCK7,
146*4882a593Smuzhiyun 	S2MPA01_BUCK8,
147*4882a593Smuzhiyun 	S2MPA01_BUCK9,
148*4882a593Smuzhiyun 	S2MPA01_BUCK10,
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	S2MPA01_REGULATOR_MAX,
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun #define S2MPA01_LDO_VSEL_MASK	0x3F
154*4882a593Smuzhiyun #define S2MPA01_BUCK_VSEL_MASK	0xFF
155*4882a593Smuzhiyun #define S2MPA01_ENABLE_MASK	(0x03 << S2MPA01_ENABLE_SHIFT)
156*4882a593Smuzhiyun #define S2MPA01_ENABLE_SHIFT	0x06
157*4882a593Smuzhiyun #define S2MPA01_LDO_N_VOLTAGES	(S2MPA01_LDO_VSEL_MASK + 1)
158*4882a593Smuzhiyun #define S2MPA01_BUCK_N_VOLTAGES (S2MPA01_BUCK_VSEL_MASK + 1)
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun #define S2MPA01_RAMP_DELAY	12500	/* uV/us */
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun #define S2MPA01_BUCK16_RAMP_SHIFT	4
163*4882a593Smuzhiyun #define S2MPA01_BUCK24_RAMP_SHIFT	6
164*4882a593Smuzhiyun #define S2MPA01_BUCK3_RAMP_SHIFT	4
165*4882a593Smuzhiyun #define S2MPA01_BUCK5_RAMP_SHIFT	6
166*4882a593Smuzhiyun #define S2MPA01_BUCK7_RAMP_SHIFT	2
167*4882a593Smuzhiyun #define S2MPA01_BUCK8910_RAMP_SHIFT	0
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun #define S2MPA01_BUCK1_RAMP_EN_SHIFT	3
170*4882a593Smuzhiyun #define S2MPA01_BUCK2_RAMP_EN_SHIFT	2
171*4882a593Smuzhiyun #define S2MPA01_BUCK3_RAMP_EN_SHIFT	1
172*4882a593Smuzhiyun #define S2MPA01_BUCK4_RAMP_EN_SHIFT	0
173*4882a593Smuzhiyun #define S2MPA01_PMIC_EN_SHIFT	6
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #endif /*__LINUX_MFD_S2MPA01_H */
176