xref: /OK3568_Linux_fs/kernel/include/linux/mfd/samsung/rtc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun  *              http://www.samsung.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_MFD_SEC_RTC_H
8*4882a593Smuzhiyun #define __LINUX_MFD_SEC_RTC_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun enum s5m_rtc_reg {
11*4882a593Smuzhiyun 	S5M_RTC_SEC,
12*4882a593Smuzhiyun 	S5M_RTC_MIN,
13*4882a593Smuzhiyun 	S5M_RTC_HOUR,
14*4882a593Smuzhiyun 	S5M_RTC_WEEKDAY,
15*4882a593Smuzhiyun 	S5M_RTC_DATE,
16*4882a593Smuzhiyun 	S5M_RTC_MONTH,
17*4882a593Smuzhiyun 	S5M_RTC_YEAR1,
18*4882a593Smuzhiyun 	S5M_RTC_YEAR2,
19*4882a593Smuzhiyun 	S5M_ALARM0_SEC,
20*4882a593Smuzhiyun 	S5M_ALARM0_MIN,
21*4882a593Smuzhiyun 	S5M_ALARM0_HOUR,
22*4882a593Smuzhiyun 	S5M_ALARM0_WEEKDAY,
23*4882a593Smuzhiyun 	S5M_ALARM0_DATE,
24*4882a593Smuzhiyun 	S5M_ALARM0_MONTH,
25*4882a593Smuzhiyun 	S5M_ALARM0_YEAR1,
26*4882a593Smuzhiyun 	S5M_ALARM0_YEAR2,
27*4882a593Smuzhiyun 	S5M_ALARM1_SEC,
28*4882a593Smuzhiyun 	S5M_ALARM1_MIN,
29*4882a593Smuzhiyun 	S5M_ALARM1_HOUR,
30*4882a593Smuzhiyun 	S5M_ALARM1_WEEKDAY,
31*4882a593Smuzhiyun 	S5M_ALARM1_DATE,
32*4882a593Smuzhiyun 	S5M_ALARM1_MONTH,
33*4882a593Smuzhiyun 	S5M_ALARM1_YEAR1,
34*4882a593Smuzhiyun 	S5M_ALARM1_YEAR2,
35*4882a593Smuzhiyun 	S5M_ALARM0_CONF,
36*4882a593Smuzhiyun 	S5M_ALARM1_CONF,
37*4882a593Smuzhiyun 	S5M_RTC_STATUS,
38*4882a593Smuzhiyun 	S5M_WTSR_SMPL_CNTL,
39*4882a593Smuzhiyun 	S5M_RTC_UDR_CON,
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	S5M_RTC_REG_MAX,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun enum s2mps_rtc_reg {
45*4882a593Smuzhiyun 	S2MPS_RTC_CTRL,
46*4882a593Smuzhiyun 	S2MPS_WTSR_SMPL_CNTL,
47*4882a593Smuzhiyun 	S2MPS_RTC_UDR_CON,
48*4882a593Smuzhiyun 	S2MPS_RSVD,
49*4882a593Smuzhiyun 	S2MPS_RTC_SEC,
50*4882a593Smuzhiyun 	S2MPS_RTC_MIN,
51*4882a593Smuzhiyun 	S2MPS_RTC_HOUR,
52*4882a593Smuzhiyun 	S2MPS_RTC_WEEKDAY,
53*4882a593Smuzhiyun 	S2MPS_RTC_DATE,
54*4882a593Smuzhiyun 	S2MPS_RTC_MONTH,
55*4882a593Smuzhiyun 	S2MPS_RTC_YEAR,
56*4882a593Smuzhiyun 	S2MPS_ALARM0_SEC,
57*4882a593Smuzhiyun 	S2MPS_ALARM0_MIN,
58*4882a593Smuzhiyun 	S2MPS_ALARM0_HOUR,
59*4882a593Smuzhiyun 	S2MPS_ALARM0_WEEKDAY,
60*4882a593Smuzhiyun 	S2MPS_ALARM0_DATE,
61*4882a593Smuzhiyun 	S2MPS_ALARM0_MONTH,
62*4882a593Smuzhiyun 	S2MPS_ALARM0_YEAR,
63*4882a593Smuzhiyun 	S2MPS_ALARM1_SEC,
64*4882a593Smuzhiyun 	S2MPS_ALARM1_MIN,
65*4882a593Smuzhiyun 	S2MPS_ALARM1_HOUR,
66*4882a593Smuzhiyun 	S2MPS_ALARM1_WEEKDAY,
67*4882a593Smuzhiyun 	S2MPS_ALARM1_DATE,
68*4882a593Smuzhiyun 	S2MPS_ALARM1_MONTH,
69*4882a593Smuzhiyun 	S2MPS_ALARM1_YEAR,
70*4882a593Smuzhiyun 	S2MPS_OFFSRC,
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	S2MPS_RTC_REG_MAX,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define RTC_I2C_ADDR		(0x0C >> 1)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define HOUR_12			(1 << 7)
78*4882a593Smuzhiyun #define HOUR_AMPM		(1 << 6)
79*4882a593Smuzhiyun #define HOUR_PM			(1 << 5)
80*4882a593Smuzhiyun #define S5M_ALARM0_STATUS	(1 << 1)
81*4882a593Smuzhiyun #define S5M_ALARM1_STATUS	(1 << 2)
82*4882a593Smuzhiyun #define S5M_UPDATE_AD		(1 << 0)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define S2MPS_ALARM0_STATUS	(1 << 2)
85*4882a593Smuzhiyun #define S2MPS_ALARM1_STATUS	(1 << 1)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* RTC Control Register */
88*4882a593Smuzhiyun #define BCD_EN_SHIFT		0
89*4882a593Smuzhiyun #define BCD_EN_MASK		(1 << BCD_EN_SHIFT)
90*4882a593Smuzhiyun #define MODEL24_SHIFT		1
91*4882a593Smuzhiyun #define MODEL24_MASK		(1 << MODEL24_SHIFT)
92*4882a593Smuzhiyun /* RTC Update Register1 */
93*4882a593Smuzhiyun #define S5M_RTC_UDR_SHIFT	0
94*4882a593Smuzhiyun #define S5M_RTC_UDR_MASK	(1 << S5M_RTC_UDR_SHIFT)
95*4882a593Smuzhiyun #define S2MPS_RTC_WUDR_SHIFT	4
96*4882a593Smuzhiyun #define S2MPS_RTC_WUDR_MASK	(1 << S2MPS_RTC_WUDR_SHIFT)
97*4882a593Smuzhiyun #define S2MPS15_RTC_AUDR_SHIFT	4
98*4882a593Smuzhiyun #define S2MPS15_RTC_AUDR_MASK	(1 << S2MPS15_RTC_AUDR_SHIFT)
99*4882a593Smuzhiyun #define S2MPS13_RTC_AUDR_SHIFT	1
100*4882a593Smuzhiyun #define S2MPS13_RTC_AUDR_MASK	(1 << S2MPS13_RTC_AUDR_SHIFT)
101*4882a593Smuzhiyun #define S2MPS15_RTC_WUDR_SHIFT	1
102*4882a593Smuzhiyun #define S2MPS15_RTC_WUDR_MASK	(1 << S2MPS15_RTC_WUDR_SHIFT)
103*4882a593Smuzhiyun #define S2MPS_RTC_RUDR_SHIFT	0
104*4882a593Smuzhiyun #define S2MPS_RTC_RUDR_MASK	(1 << S2MPS_RTC_RUDR_SHIFT)
105*4882a593Smuzhiyun #define RTC_TCON_SHIFT		1
106*4882a593Smuzhiyun #define RTC_TCON_MASK		(1 << RTC_TCON_SHIFT)
107*4882a593Smuzhiyun #define S5M_RTC_TIME_EN_SHIFT	3
108*4882a593Smuzhiyun #define S5M_RTC_TIME_EN_MASK	(1 << S5M_RTC_TIME_EN_SHIFT)
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun  * UDR_T field in S5M_RTC_UDR_CON register determines the time needed
111*4882a593Smuzhiyun  * for updating alarm and time registers. Default is 7.32 ms.
112*4882a593Smuzhiyun  */
113*4882a593Smuzhiyun #define S5M_RTC_UDR_T_SHIFT	6
114*4882a593Smuzhiyun #define S5M_RTC_UDR_T_MASK	(0x3 << S5M_RTC_UDR_T_SHIFT)
115*4882a593Smuzhiyun #define S5M_RTC_UDR_T_7320_US	(0x0 << S5M_RTC_UDR_T_SHIFT)
116*4882a593Smuzhiyun #define S5M_RTC_UDR_T_1830_US	(0x1 << S5M_RTC_UDR_T_SHIFT)
117*4882a593Smuzhiyun #define S5M_RTC_UDR_T_3660_US	(0x2 << S5M_RTC_UDR_T_SHIFT)
118*4882a593Smuzhiyun #define S5M_RTC_UDR_T_450_US	(0x3 << S5M_RTC_UDR_T_SHIFT)
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /* RTC Hour register */
121*4882a593Smuzhiyun #define HOUR_PM_SHIFT		6
122*4882a593Smuzhiyun #define HOUR_PM_MASK		(1 << HOUR_PM_SHIFT)
123*4882a593Smuzhiyun /* RTC Alarm Enable */
124*4882a593Smuzhiyun #define ALARM_ENABLE_SHIFT	7
125*4882a593Smuzhiyun #define ALARM_ENABLE_MASK	(1 << ALARM_ENABLE_SHIFT)
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define SMPL_ENABLE_SHIFT	7
128*4882a593Smuzhiyun #define SMPL_ENABLE_MASK	(1 << SMPL_ENABLE_SHIFT)
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun #define WTSR_ENABLE_SHIFT	6
131*4882a593Smuzhiyun #define WTSR_ENABLE_MASK	(1 << WTSR_ENABLE_SHIFT)
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #endif /*  __LINUX_MFD_SEC_RTC_H */
134