1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __LINUX_MFD_PCF50633_PMIC_H 3*4882a593Smuzhiyun #define __LINUX_MFD_PCF50633_PMIC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/mfd/pcf50633/core.h> 6*4882a593Smuzhiyun #include <linux/platform_device.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define PCF50633_REG_AUTOOUT 0x1a 9*4882a593Smuzhiyun #define PCF50633_REG_AUTOENA 0x1b 10*4882a593Smuzhiyun #define PCF50633_REG_AUTOCTL 0x1c 11*4882a593Smuzhiyun #define PCF50633_REG_AUTOMXC 0x1d 12*4882a593Smuzhiyun #define PCF50633_REG_DOWN1OUT 0x1e 13*4882a593Smuzhiyun #define PCF50633_REG_DOWN1ENA 0x1f 14*4882a593Smuzhiyun #define PCF50633_REG_DOWN1CTL 0x20 15*4882a593Smuzhiyun #define PCF50633_REG_DOWN1MXC 0x21 16*4882a593Smuzhiyun #define PCF50633_REG_DOWN2OUT 0x22 17*4882a593Smuzhiyun #define PCF50633_REG_DOWN2ENA 0x23 18*4882a593Smuzhiyun #define PCF50633_REG_DOWN2CTL 0x24 19*4882a593Smuzhiyun #define PCF50633_REG_DOWN2MXC 0x25 20*4882a593Smuzhiyun #define PCF50633_REG_MEMLDOOUT 0x26 21*4882a593Smuzhiyun #define PCF50633_REG_MEMLDOENA 0x27 22*4882a593Smuzhiyun #define PCF50633_REG_LDO1OUT 0x2d 23*4882a593Smuzhiyun #define PCF50633_REG_LDO1ENA 0x2e 24*4882a593Smuzhiyun #define PCF50633_REG_LDO2OUT 0x2f 25*4882a593Smuzhiyun #define PCF50633_REG_LDO2ENA 0x30 26*4882a593Smuzhiyun #define PCF50633_REG_LDO3OUT 0x31 27*4882a593Smuzhiyun #define PCF50633_REG_LDO3ENA 0x32 28*4882a593Smuzhiyun #define PCF50633_REG_LDO4OUT 0x33 29*4882a593Smuzhiyun #define PCF50633_REG_LDO4ENA 0x34 30*4882a593Smuzhiyun #define PCF50633_REG_LDO5OUT 0x35 31*4882a593Smuzhiyun #define PCF50633_REG_LDO5ENA 0x36 32*4882a593Smuzhiyun #define PCF50633_REG_LDO6OUT 0x37 33*4882a593Smuzhiyun #define PCF50633_REG_LDO6ENA 0x38 34*4882a593Smuzhiyun #define PCF50633_REG_HCLDOOUT 0x39 35*4882a593Smuzhiyun #define PCF50633_REG_HCLDOENA 0x3a 36*4882a593Smuzhiyun #define PCF50633_REG_HCLDOOVL 0x40 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum pcf50633_regulator_enable { 39*4882a593Smuzhiyun PCF50633_REGULATOR_ON = 0x01, 40*4882a593Smuzhiyun PCF50633_REGULATOR_ON_GPIO1 = 0x02, 41*4882a593Smuzhiyun PCF50633_REGULATOR_ON_GPIO2 = 0x04, 42*4882a593Smuzhiyun PCF50633_REGULATOR_ON_GPIO3 = 0x08, 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun #define PCF50633_REGULATOR_ON_MASK 0x0f 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun enum pcf50633_regulator_phase { 47*4882a593Smuzhiyun PCF50633_REGULATOR_ACTPH1 = 0x00, 48*4882a593Smuzhiyun PCF50633_REGULATOR_ACTPH2 = 0x10, 49*4882a593Smuzhiyun PCF50633_REGULATOR_ACTPH3 = 0x20, 50*4882a593Smuzhiyun PCF50633_REGULATOR_ACTPH4 = 0x30, 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun #define PCF50633_REGULATOR_ACTPH_MASK 0x30 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun enum pcf50633_regulator_id { 55*4882a593Smuzhiyun PCF50633_REGULATOR_AUTO, 56*4882a593Smuzhiyun PCF50633_REGULATOR_DOWN1, 57*4882a593Smuzhiyun PCF50633_REGULATOR_DOWN2, 58*4882a593Smuzhiyun PCF50633_REGULATOR_LDO1, 59*4882a593Smuzhiyun PCF50633_REGULATOR_LDO2, 60*4882a593Smuzhiyun PCF50633_REGULATOR_LDO3, 61*4882a593Smuzhiyun PCF50633_REGULATOR_LDO4, 62*4882a593Smuzhiyun PCF50633_REGULATOR_LDO5, 63*4882a593Smuzhiyun PCF50633_REGULATOR_LDO6, 64*4882a593Smuzhiyun PCF50633_REGULATOR_HCLDO, 65*4882a593Smuzhiyun PCF50633_REGULATOR_MEMLDO, 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun 69