1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * adc.h -- Driver for NXP PCF50633 ADC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) 2006-2008 by Openmoko, Inc. 6*4882a593Smuzhiyun * All rights reserved. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __LINUX_MFD_PCF50633_ADC_H 10*4882a593Smuzhiyun #define __LINUX_MFD_PCF50633_ADC_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/mfd/pcf50633/core.h> 13*4882a593Smuzhiyun #include <linux/platform_device.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* ADC Registers */ 16*4882a593Smuzhiyun #define PCF50633_REG_ADCC3 0x52 17*4882a593Smuzhiyun #define PCF50633_REG_ADCC2 0x53 18*4882a593Smuzhiyun #define PCF50633_REG_ADCC1 0x54 19*4882a593Smuzhiyun #define PCF50633_REG_ADCS1 0x55 20*4882a593Smuzhiyun #define PCF50633_REG_ADCS2 0x56 21*4882a593Smuzhiyun #define PCF50633_REG_ADCS3 0x57 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define PCF50633_ADCC1_ADCSTART 0x01 24*4882a593Smuzhiyun #define PCF50633_ADCC1_RES_8BIT 0x02 25*4882a593Smuzhiyun #define PCF50633_ADCC1_RES_10BIT 0x00 26*4882a593Smuzhiyun #define PCF50633_ADCC1_AVERAGE_NO 0x00 27*4882a593Smuzhiyun #define PCF50633_ADCC1_AVERAGE_4 0x04 28*4882a593Smuzhiyun #define PCF50633_ADCC1_AVERAGE_8 0x08 29*4882a593Smuzhiyun #define PCF50633_ADCC1_AVERAGE_16 0x0c 30*4882a593Smuzhiyun #define PCF50633_ADCC1_MUX_BATSNS_RES 0x00 31*4882a593Smuzhiyun #define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10 32*4882a593Smuzhiyun #define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20 33*4882a593Smuzhiyun #define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30 34*4882a593Smuzhiyun #define PCF50633_ADCC1_MUX_BATTEMP 0x60 35*4882a593Smuzhiyun #define PCF50633_ADCC1_MUX_ADCIN1 0x70 36*4882a593Smuzhiyun #define PCF50633_ADCC1_AVERAGE_MASK 0x0c 37*4882a593Smuzhiyun #define PCF50633_ADCC1_ADCMUX_MASK 0xf0 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PCF50633_ADCC2_RATIO_NONE 0x00 40*4882a593Smuzhiyun #define PCF50633_ADCC2_RATIO_BATTEMP 0x01 41*4882a593Smuzhiyun #define PCF50633_ADCC2_RATIO_ADCIN1 0x02 42*4882a593Smuzhiyun #define PCF50633_ADCC2_RATIO_BOTH 0x03 43*4882a593Smuzhiyun #define PCF50633_ADCC2_RATIOSETTL_100US 0x04 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define PCF50633_ADCC3_ACCSW_EN 0x01 46*4882a593Smuzhiyun #define PCF50633_ADCC3_NTCSW_EN 0x04 47*4882a593Smuzhiyun #define PCF50633_ADCC3_RES_DIV_TWO 0x10 48*4882a593Smuzhiyun #define PCF50633_ADCC3_RES_DIV_THREE 0x00 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define PCF50633_ADCS3_REF_NTCSW 0x00 51*4882a593Smuzhiyun #define PCF50633_ADCS3_REF_ACCSW 0x10 52*4882a593Smuzhiyun #define PCF50633_ADCS3_REF_2V0 0x20 53*4882a593Smuzhiyun #define PCF50633_ADCS3_REF_VISA 0x30 54*4882a593Smuzhiyun #define PCF50633_ADCS3_REF_2V0_2 0x70 55*4882a593Smuzhiyun #define PCF50633_ADCS3_ADCRDY 0x80 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define PCF50633_ADCS3_ADCDAT1L_MASK 0x03 58*4882a593Smuzhiyun #define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c 59*4882a593Smuzhiyun #define PCF50633_ADCS3_ADCDAT2L_SHIFT 2 60*4882a593Smuzhiyun #define PCF50633_ASCS3_REF_MASK 0x70 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun extern int 63*4882a593Smuzhiyun pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, 64*4882a593Smuzhiyun void (*callback)(struct pcf50633 *, void *, int), 65*4882a593Smuzhiyun void *callback_param); 66*4882a593Smuzhiyun extern int 67*4882a593Smuzhiyun pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* __LINUX_PCF50633_ADC_H */ 70