1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014-2019 MediaTek Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Tianping.Fang <tianping.fang@mediatek.com> 6*4882a593Smuzhiyun * Sean Wang <sean.wang@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _LINUX_MFD_MT6397_RTC_H_ 10*4882a593Smuzhiyun #define _LINUX_MFD_MT6397_RTC_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/jiffies.h> 13*4882a593Smuzhiyun #include <linux/mutex.h> 14*4882a593Smuzhiyun #include <linux/regmap.h> 15*4882a593Smuzhiyun #include <linux/rtc.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define RTC_BBPU 0x0000 18*4882a593Smuzhiyun #define RTC_BBPU_CBUSY BIT(6) 19*4882a593Smuzhiyun #define RTC_BBPU_KEY (0x43 << 8) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define RTC_WRTGR_MT6358 0x003a 22*4882a593Smuzhiyun #define RTC_WRTGR_MT6397 0x003c 23*4882a593Smuzhiyun #define RTC_WRTGR_MT6323 RTC_WRTGR_MT6397 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define RTC_IRQ_STA 0x0002 26*4882a593Smuzhiyun #define RTC_IRQ_STA_AL BIT(0) 27*4882a593Smuzhiyun #define RTC_IRQ_STA_LP BIT(3) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define RTC_IRQ_EN 0x0004 30*4882a593Smuzhiyun #define RTC_IRQ_EN_AL BIT(0) 31*4882a593Smuzhiyun #define RTC_IRQ_EN_ONESHOT BIT(2) 32*4882a593Smuzhiyun #define RTC_IRQ_EN_LP BIT(3) 33*4882a593Smuzhiyun #define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define RTC_AL_MASK 0x0008 36*4882a593Smuzhiyun #define RTC_AL_MASK_DOW BIT(4) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define RTC_TC_SEC 0x000a 39*4882a593Smuzhiyun /* Min, Hour, Dom... register offset to RTC_TC_SEC */ 40*4882a593Smuzhiyun #define RTC_OFFSET_SEC 0 41*4882a593Smuzhiyun #define RTC_OFFSET_MIN 1 42*4882a593Smuzhiyun #define RTC_OFFSET_HOUR 2 43*4882a593Smuzhiyun #define RTC_OFFSET_DOM 3 44*4882a593Smuzhiyun #define RTC_OFFSET_DOW 4 45*4882a593Smuzhiyun #define RTC_OFFSET_MTH 5 46*4882a593Smuzhiyun #define RTC_OFFSET_YEAR 6 47*4882a593Smuzhiyun #define RTC_OFFSET_COUNT 7 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define RTC_AL_SEC 0x0018 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define RTC_AL_SEC_MASK 0x003f 52*4882a593Smuzhiyun #define RTC_AL_MIN_MASK 0x003f 53*4882a593Smuzhiyun #define RTC_AL_HOU_MASK 0x001f 54*4882a593Smuzhiyun #define RTC_AL_DOM_MASK 0x001f 55*4882a593Smuzhiyun #define RTC_AL_DOW_MASK 0x0007 56*4882a593Smuzhiyun #define RTC_AL_MTH_MASK 0x000f 57*4882a593Smuzhiyun #define RTC_AL_YEA_MASK 0x007f 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define RTC_PDN2 0x002e 60*4882a593Smuzhiyun #define RTC_PDN2_PWRON_ALARM BIT(4) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define RTC_MIN_YEAR 1968 63*4882a593Smuzhiyun #define RTC_BASE_YEAR 1900 64*4882a593Smuzhiyun #define RTC_NUM_YEARS 128 65*4882a593Smuzhiyun #define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define MTK_RTC_POLL_DELAY_US 10 68*4882a593Smuzhiyun #define MTK_RTC_POLL_TIMEOUT (jiffies_to_usecs(HZ)) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct mtk_rtc_data { 71*4882a593Smuzhiyun u32 wrtgr; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct mt6397_rtc { 75*4882a593Smuzhiyun struct rtc_device *rtc_dev; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Protect register access from multiple tasks */ 78*4882a593Smuzhiyun struct mutex lock; 79*4882a593Smuzhiyun struct regmap *regmap; 80*4882a593Smuzhiyun int irq; 81*4882a593Smuzhiyun u32 addr_base; 82*4882a593Smuzhiyun const struct mtk_rtc_data *data; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* _LINUX_MFD_MT6397_RTC_H_ */ 86