1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Functions to access Menelaus power management chip 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ASM_ARCH_MENELAUS_H 7*4882a593Smuzhiyun #define __ASM_ARCH_MENELAUS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct device; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct menelaus_platform_data { 12*4882a593Smuzhiyun int (* late_init)(struct device *dev); 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask), 16*4882a593Smuzhiyun void *data); 17*4882a593Smuzhiyun extern void menelaus_unregister_mmc_callback(void); 18*4882a593Smuzhiyun extern int menelaus_set_mmc_opendrain(int slot, int enable); 19*4882a593Smuzhiyun extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on); 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun extern int menelaus_set_vmem(unsigned int mV); 22*4882a593Smuzhiyun extern int menelaus_set_vio(unsigned int mV); 23*4882a593Smuzhiyun extern int menelaus_set_vmmc(unsigned int mV); 24*4882a593Smuzhiyun extern int menelaus_set_vaux(unsigned int mV); 25*4882a593Smuzhiyun extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); 26*4882a593Smuzhiyun extern int menelaus_set_slot_sel(int enable); 27*4882a593Smuzhiyun extern int menelaus_get_slot_pin_states(void); 28*4882a593Smuzhiyun extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define EN_VPLL_SLEEP (1 << 7) 31*4882a593Smuzhiyun #define EN_VMMC_SLEEP (1 << 6) 32*4882a593Smuzhiyun #define EN_VAUX_SLEEP (1 << 5) 33*4882a593Smuzhiyun #define EN_VIO_SLEEP (1 << 4) 34*4882a593Smuzhiyun #define EN_VMEM_SLEEP (1 << 3) 35*4882a593Smuzhiyun #define EN_DC3_SLEEP (1 << 2) 36*4882a593Smuzhiyun #define EN_DC2_SLEEP (1 << 1) 37*4882a593Smuzhiyun #define EN_VC_SLEEP (1 << 0) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun extern int menelaus_set_regulator_sleep(int enable, u32 val); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif 42