1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Defining registers address and its bit definitions of MAX96745 4 * 5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 6 */ 7 8 #ifndef _MFD_MAX96745_H_ 9 #define _MFD_MAX96745_H_ 10 11 #include <linux/bitfield.h> 12 13 struct max96745 { 14 struct device *dev; 15 struct regmap *regmap; 16 struct i2c_mux_core *muxc; 17 struct gpio_desc *enable_gpio; 18 struct gpio_desc *pwdnb_gpio; 19 struct extcon_dev *extcon; 20 bool idle_disc; 21 }; 22 23 #define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 8)) 24 #define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 8)) 25 #define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 8)) 26 #define GPIO_D_REG(gpio) (0x0203 + ((gpio) * 8)) 27 28 /* 0005h */ 29 #define PU_LF3 BIT(3) 30 #define PU_LF2 BIT(2) 31 #define PU_LF1 BIT(1) 32 #define PU_LF0 BIT(0) 33 34 /* 0010h */ 35 #define RESET_ALL BIT(7) 36 #define SLEEP BIT(3) 37 38 /* 0011h */ 39 #define CXTP_B BIT(2) 40 #define CXTP_A BIT(0) 41 42 /* 0013h */ 43 #define LOCKED BIT(3) 44 #define ERROR BIT(2) 45 46 /* 0026h */ 47 #define LF_0 GENMASK(2, 0) 48 #define LF_1 GENMASK(6, 4) 49 50 /* 0027h */ 51 #define LF_2 GENMASK(2, 0) 52 #define LF_3 GENMASK(6, 4) 53 54 /* 0028h, 0032h */ 55 #define LINK_EN BIT(7) 56 #define TX_RATE GENMASK(3, 2) 57 58 /* 0029h, 0033h */ 59 #define RESET_LINK BIT(0) 60 #define RESET_ONESHOT BIT(1) 61 62 /* 002Ah, 0034h */ 63 #define LINK_LOCKED BIT(0) 64 65 /* 0076h, 0086h */ 66 #define DIS_REM_CC BIT(7) 67 68 /* 0100h */ 69 #define VID_LINK_SEL GENMASK(2, 1) 70 #define VID_TX_EN BIT(0) 71 72 /* 0101h */ 73 #define BPP GENMASK(5, 0) 74 75 /* 0102h */ 76 #define PCLKDET_A BIT(7) 77 #define DRIFT_ERR_A BIT(6) 78 #define OVERFLOW_A BIT(5) 79 #define FIFO_WARN_A BIT(4) 80 #define LIM_HEART BIT(2) 81 82 /* 0107h */ 83 #define VID_TX_ACTIVE_B BIT(7) 84 #define VID_TX_ACTIVE_A BIT(6) 85 86 /* 0108h */ 87 #define PCLKDET_B BIT(7) 88 #define DRIFT_ERR_B BIT(6) 89 #define OVERFLOW_B BIT(5) 90 #define FIFO_WARN_B BIT(4) 91 92 /* 0200h */ 93 #define RES_CFG BIT(7) 94 #define TX_COM_EN BIT(5) 95 #define GPIO_OUT BIT(4) 96 #define GPIO_IN BIT(3) 97 #define GPIO_OUT_DIS BIT(0) 98 99 /* 0201h */ 100 #define PULL_UPDN_SEL GENMASK(7, 6) 101 #define OUT_TYPEC BIT(5) 102 #define GPIO_TX_ID GENMASK(4, 0) 103 104 /* 0202h */ 105 #define OVR_RES_CFG BIT(7) 106 #define IO_EDGE_RATE GENMASK(6, 5) 107 #define GPIO_RX_ID GENMASK(4, 0) 108 109 /* 0203h */ 110 #define GPIO_IO_RX_EN BIT(5) 111 #define GPIO_OUT_LGC BIT(4) 112 #define GPIO_RX_EN_B BIT(3) 113 #define GPIO_TX_EN_B BIT(2) 114 #define GPIO_RX_EN_A BIT(1) 115 #define GPIO_TX_EN_A BIT(0) 116 117 /* 0750h */ 118 #define FRCZEROPAD GENMASK(7, 6) 119 #define FRCZPEN BIT(5) 120 #define FRCSDGAIN BIT(4) 121 #define FRCSDEN BIT(3) 122 #define FRCGAIN GENMASK(2, 1) 123 #define FRCEN BIT(0) 124 125 /* 0751h */ 126 #define FRCDATAWIDTH BIT(3) 127 #define FRCASYNCEN BIT(2) 128 #define FRCHSPOL BIT(1) 129 #define FRCVSPOL BIT(0) 130 131 /* 0752h */ 132 #define FRCDCMODE GENMASK(1, 0) 133 134 /* 641Ah */ 135 #define DPRX_TRAIN_STATE GENMASK(7, 4) 136 137 /* 7000h */ 138 #define LINK_ENABLE BIT(0) 139 140 /* 7070h */ 141 #define MAX_LANE_COUNT GENMASK(7, 0) 142 143 /* 7074h */ 144 #define MAX_LINK_RATE GENMASK(7, 0) 145 146 #endif /* _MFD_MAX96745_H_ */ 147