xref: /OK3568_Linux_fs/kernel/include/linux/mfd/max96745.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Defining registers address and its bit definitions of MAX96745
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _MFD_MAX96745_H_
9*4882a593Smuzhiyun #define _MFD_MAX96745_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/bitfield.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct max96745 {
14*4882a593Smuzhiyun 	struct device *dev;
15*4882a593Smuzhiyun 	struct regmap *regmap;
16*4882a593Smuzhiyun 	struct i2c_mux_core *muxc;
17*4882a593Smuzhiyun 	struct gpio_desc *enable_gpio;
18*4882a593Smuzhiyun 	struct gpio_desc *pwdnb_gpio;
19*4882a593Smuzhiyun 	struct extcon_dev *extcon;
20*4882a593Smuzhiyun 	bool idle_disc;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define GPIO_A_REG(gpio)	(0x0200 + ((gpio) * 8))
24*4882a593Smuzhiyun #define GPIO_B_REG(gpio)	(0x0201 + ((gpio) * 8))
25*4882a593Smuzhiyun #define GPIO_C_REG(gpio)	(0x0202 + ((gpio) * 8))
26*4882a593Smuzhiyun #define GPIO_D_REG(gpio)	(0x0203 + ((gpio) * 8))
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* 0005h */
29*4882a593Smuzhiyun #define PU_LF3			BIT(3)
30*4882a593Smuzhiyun #define PU_LF2			BIT(2)
31*4882a593Smuzhiyun #define PU_LF1			BIT(1)
32*4882a593Smuzhiyun #define PU_LF0			BIT(0)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* 0010h */
35*4882a593Smuzhiyun #define RESET_ALL		BIT(7)
36*4882a593Smuzhiyun #define SLEEP			BIT(3)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* 0011h */
39*4882a593Smuzhiyun #define CXTP_B			BIT(2)
40*4882a593Smuzhiyun #define CXTP_A			BIT(0)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* 0013h */
43*4882a593Smuzhiyun #define LOCKED			BIT(3)
44*4882a593Smuzhiyun #define ERROR			BIT(2)
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* 0026h */
47*4882a593Smuzhiyun #define LF_0			GENMASK(2, 0)
48*4882a593Smuzhiyun #define LF_1			GENMASK(6, 4)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* 0027h */
51*4882a593Smuzhiyun #define LF_2			GENMASK(2, 0)
52*4882a593Smuzhiyun #define LF_3			GENMASK(6, 4)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* 0028h, 0032h */
55*4882a593Smuzhiyun #define LINK_EN			BIT(7)
56*4882a593Smuzhiyun #define TX_RATE			GENMASK(3, 2)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun /* 0029h, 0033h */
59*4882a593Smuzhiyun #define RESET_LINK		BIT(0)
60*4882a593Smuzhiyun #define RESET_ONESHOT		BIT(1)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* 002Ah, 0034h */
63*4882a593Smuzhiyun #define LINK_LOCKED		BIT(0)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* 0076h, 0086h */
66*4882a593Smuzhiyun #define DIS_REM_CC		BIT(7)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* 0100h */
69*4882a593Smuzhiyun #define VID_LINK_SEL		GENMASK(2, 1)
70*4882a593Smuzhiyun #define VID_TX_EN		BIT(0)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* 0101h */
73*4882a593Smuzhiyun #define BPP			GENMASK(5, 0)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* 0102h */
76*4882a593Smuzhiyun #define PCLKDET_A		BIT(7)
77*4882a593Smuzhiyun #define DRIFT_ERR_A		BIT(6)
78*4882a593Smuzhiyun #define OVERFLOW_A		BIT(5)
79*4882a593Smuzhiyun #define FIFO_WARN_A		BIT(4)
80*4882a593Smuzhiyun #define LIM_HEART		BIT(2)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /* 0107h */
83*4882a593Smuzhiyun #define VID_TX_ACTIVE_B		BIT(7)
84*4882a593Smuzhiyun #define VID_TX_ACTIVE_A		BIT(6)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /* 0108h */
87*4882a593Smuzhiyun #define PCLKDET_B		BIT(7)
88*4882a593Smuzhiyun #define DRIFT_ERR_B		BIT(6)
89*4882a593Smuzhiyun #define OVERFLOW_B		BIT(5)
90*4882a593Smuzhiyun #define FIFO_WARN_B		BIT(4)
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /* 0200h */
93*4882a593Smuzhiyun #define RES_CFG			BIT(7)
94*4882a593Smuzhiyun #define TX_COM_EN		BIT(5)
95*4882a593Smuzhiyun #define GPIO_OUT		BIT(4)
96*4882a593Smuzhiyun #define GPIO_IN			BIT(3)
97*4882a593Smuzhiyun #define GPIO_OUT_DIS		BIT(0)
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /* 0201h */
100*4882a593Smuzhiyun #define PULL_UPDN_SEL		GENMASK(7, 6)
101*4882a593Smuzhiyun #define OUT_TYPEC		BIT(5)
102*4882a593Smuzhiyun #define GPIO_TX_ID		GENMASK(4, 0)
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /* 0202h */
105*4882a593Smuzhiyun #define OVR_RES_CFG		BIT(7)
106*4882a593Smuzhiyun #define IO_EDGE_RATE		GENMASK(6, 5)
107*4882a593Smuzhiyun #define GPIO_RX_ID		GENMASK(4, 0)
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /* 0203h */
110*4882a593Smuzhiyun #define GPIO_IO_RX_EN		BIT(5)
111*4882a593Smuzhiyun #define GPIO_OUT_LGC		BIT(4)
112*4882a593Smuzhiyun #define GPIO_RX_EN_B		BIT(3)
113*4882a593Smuzhiyun #define GPIO_TX_EN_B		BIT(2)
114*4882a593Smuzhiyun #define GPIO_RX_EN_A		BIT(1)
115*4882a593Smuzhiyun #define GPIO_TX_EN_A		BIT(0)
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* 0750h */
118*4882a593Smuzhiyun #define FRCZEROPAD		GENMASK(7, 6)
119*4882a593Smuzhiyun #define FRCZPEN			BIT(5)
120*4882a593Smuzhiyun #define FRCSDGAIN		BIT(4)
121*4882a593Smuzhiyun #define FRCSDEN			BIT(3)
122*4882a593Smuzhiyun #define FRCGAIN			GENMASK(2, 1)
123*4882a593Smuzhiyun #define FRCEN			BIT(0)
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun /* 0751h */
126*4882a593Smuzhiyun #define FRCDATAWIDTH		BIT(3)
127*4882a593Smuzhiyun #define FRCASYNCEN		BIT(2)
128*4882a593Smuzhiyun #define FRCHSPOL		BIT(1)
129*4882a593Smuzhiyun #define FRCVSPOL		BIT(0)
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* 0752h */
132*4882a593Smuzhiyun #define FRCDCMODE		GENMASK(1, 0)
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /* 641Ah */
135*4882a593Smuzhiyun #define DPRX_TRAIN_STATE	GENMASK(7, 4)
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /* 7000h */
138*4882a593Smuzhiyun #define LINK_ENABLE		BIT(0)
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* 7070h */
141*4882a593Smuzhiyun #define MAX_LANE_COUNT		GENMASK(7, 0)
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun /* 7074h */
144*4882a593Smuzhiyun #define MAX_LINK_RATE		GENMASK(7, 0)
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #endif /* _MFD_MAX96745_H_ */
147