xref: /OK3568_Linux_fs/kernel/include/linux/mfd/max8998-private.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * max8998-private.h - Voltage regulator driver for the Maxim 8998
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2009-2010 Samsung Electrnoics
6*4882a593Smuzhiyun  *  Kyungmin Park <kyungmin.park@samsung.com>
7*4882a593Smuzhiyun  *  Marek Szyprowski <m.szyprowski@samsung.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef __LINUX_MFD_MAX8998_PRIV_H
11*4882a593Smuzhiyun #define __LINUX_MFD_MAX8998_PRIV_H
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define MAX8998_NUM_IRQ_REGS	4
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /* MAX 8998 registers */
16*4882a593Smuzhiyun enum {
17*4882a593Smuzhiyun 	MAX8998_REG_IRQ1,
18*4882a593Smuzhiyun 	MAX8998_REG_IRQ2,
19*4882a593Smuzhiyun 	MAX8998_REG_IRQ3,
20*4882a593Smuzhiyun 	MAX8998_REG_IRQ4,
21*4882a593Smuzhiyun 	MAX8998_REG_IRQM1,
22*4882a593Smuzhiyun 	MAX8998_REG_IRQM2,
23*4882a593Smuzhiyun 	MAX8998_REG_IRQM3,
24*4882a593Smuzhiyun 	MAX8998_REG_IRQM4,
25*4882a593Smuzhiyun 	MAX8998_REG_STATUS1,
26*4882a593Smuzhiyun 	MAX8998_REG_STATUS2,
27*4882a593Smuzhiyun 	MAX8998_REG_STATUSM1,
28*4882a593Smuzhiyun 	MAX8998_REG_STATUSM2,
29*4882a593Smuzhiyun 	MAX8998_REG_CHGR1,
30*4882a593Smuzhiyun 	MAX8998_REG_CHGR2,
31*4882a593Smuzhiyun 	MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
32*4882a593Smuzhiyun 	MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
33*4882a593Smuzhiyun 	MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
34*4882a593Smuzhiyun 	MAX8998_REG_ONOFF1,
35*4882a593Smuzhiyun 	MAX8998_REG_ONOFF2,
36*4882a593Smuzhiyun 	MAX8998_REG_ONOFF3,
37*4882a593Smuzhiyun 	MAX8998_REG_ONOFF4,
38*4882a593Smuzhiyun 	MAX8998_REG_BUCK1_VOLTAGE1,
39*4882a593Smuzhiyun 	MAX8998_REG_BUCK1_VOLTAGE2,
40*4882a593Smuzhiyun 	MAX8998_REG_BUCK1_VOLTAGE3,
41*4882a593Smuzhiyun 	MAX8998_REG_BUCK1_VOLTAGE4,
42*4882a593Smuzhiyun 	MAX8998_REG_BUCK2_VOLTAGE1,
43*4882a593Smuzhiyun 	MAX8998_REG_BUCK2_VOLTAGE2,
44*4882a593Smuzhiyun 	MAX8998_REG_BUCK3,
45*4882a593Smuzhiyun 	MAX8998_REG_BUCK4,
46*4882a593Smuzhiyun 	MAX8998_REG_LDO2_LDO3,
47*4882a593Smuzhiyun 	MAX8998_REG_LDO4,
48*4882a593Smuzhiyun 	MAX8998_REG_LDO5,
49*4882a593Smuzhiyun 	MAX8998_REG_LDO6,
50*4882a593Smuzhiyun 	MAX8998_REG_LDO7,
51*4882a593Smuzhiyun 	MAX8998_REG_LDO8_LDO9,
52*4882a593Smuzhiyun 	MAX8998_REG_LDO10_LDO11,
53*4882a593Smuzhiyun 	MAX8998_REG_LDO12,
54*4882a593Smuzhiyun 	MAX8998_REG_LDO13,
55*4882a593Smuzhiyun 	MAX8998_REG_LDO14,
56*4882a593Smuzhiyun 	MAX8998_REG_LDO15,
57*4882a593Smuzhiyun 	MAX8998_REG_LDO16,
58*4882a593Smuzhiyun 	MAX8998_REG_LDO17,
59*4882a593Smuzhiyun 	MAX8998_REG_BKCHR,
60*4882a593Smuzhiyun 	MAX8998_REG_LBCNFG1,
61*4882a593Smuzhiyun 	MAX8998_REG_LBCNFG2,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun /* IRQ definitions */
65*4882a593Smuzhiyun enum {
66*4882a593Smuzhiyun 	MAX8998_IRQ_DCINF,
67*4882a593Smuzhiyun 	MAX8998_IRQ_DCINR,
68*4882a593Smuzhiyun 	MAX8998_IRQ_JIGF,
69*4882a593Smuzhiyun 	MAX8998_IRQ_JIGR,
70*4882a593Smuzhiyun 	MAX8998_IRQ_PWRONF,
71*4882a593Smuzhiyun 	MAX8998_IRQ_PWRONR,
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	MAX8998_IRQ_WTSREVNT,
74*4882a593Smuzhiyun 	MAX8998_IRQ_SMPLEVNT,
75*4882a593Smuzhiyun 	MAX8998_IRQ_ALARM1,
76*4882a593Smuzhiyun 	MAX8998_IRQ_ALARM0,
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	MAX8998_IRQ_ONKEY1S,
79*4882a593Smuzhiyun 	MAX8998_IRQ_TOPOFFR,
80*4882a593Smuzhiyun 	MAX8998_IRQ_DCINOVPR,
81*4882a593Smuzhiyun 	MAX8998_IRQ_CHGRSTF,
82*4882a593Smuzhiyun 	MAX8998_IRQ_DONER,
83*4882a593Smuzhiyun 	MAX8998_IRQ_CHGFAULT,
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	MAX8998_IRQ_LOBAT1,
86*4882a593Smuzhiyun 	MAX8998_IRQ_LOBAT2,
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	MAX8998_IRQ_NR,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun /* MAX8998 various variants */
92*4882a593Smuzhiyun enum {
93*4882a593Smuzhiyun 	TYPE_MAX8998 = 0, /* Default */
94*4882a593Smuzhiyun 	TYPE_LP3974,	/* National version of MAX8998 */
95*4882a593Smuzhiyun 	TYPE_LP3979,	/* Added AVS */
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define MAX8998_IRQ_DCINF_MASK		(1 << 2)
99*4882a593Smuzhiyun #define MAX8998_IRQ_DCINR_MASK		(1 << 3)
100*4882a593Smuzhiyun #define MAX8998_IRQ_JIGF_MASK		(1 << 4)
101*4882a593Smuzhiyun #define MAX8998_IRQ_JIGR_MASK		(1 << 5)
102*4882a593Smuzhiyun #define MAX8998_IRQ_PWRONF_MASK		(1 << 6)
103*4882a593Smuzhiyun #define MAX8998_IRQ_PWRONR_MASK		(1 << 7)
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #define MAX8998_IRQ_WTSREVNT_MASK	(1 << 0)
106*4882a593Smuzhiyun #define MAX8998_IRQ_SMPLEVNT_MASK	(1 << 1)
107*4882a593Smuzhiyun #define MAX8998_IRQ_ALARM1_MASK		(1 << 2)
108*4882a593Smuzhiyun #define MAX8998_IRQ_ALARM0_MASK		(1 << 3)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define MAX8998_IRQ_ONKEY1S_MASK	(1 << 0)
111*4882a593Smuzhiyun #define MAX8998_IRQ_TOPOFFR_MASK	(1 << 2)
112*4882a593Smuzhiyun #define MAX8998_IRQ_DCINOVPR_MASK	(1 << 3)
113*4882a593Smuzhiyun #define MAX8998_IRQ_CHGRSTF_MASK	(1 << 4)
114*4882a593Smuzhiyun #define MAX8998_IRQ_DONER_MASK		(1 << 5)
115*4882a593Smuzhiyun #define MAX8998_IRQ_CHGFAULT_MASK	(1 << 7)
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define MAX8998_IRQ_LOBAT1_MASK		(1 << 0)
118*4882a593Smuzhiyun #define MAX8998_IRQ_LOBAT2_MASK		(1 << 1)
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define MAX8998_ENRAMP                  (1 << 4)
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun struct irq_domain;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun /**
125*4882a593Smuzhiyun  * struct max8998_dev - max8998 master device for sub-drivers
126*4882a593Smuzhiyun  * @dev: master device of the chip (can be used to access platform data)
127*4882a593Smuzhiyun  * @pdata: platform data for the driver and subdrivers
128*4882a593Smuzhiyun  * @i2c: i2c client private data for regulator
129*4882a593Smuzhiyun  * @rtc: i2c client private data for rtc
130*4882a593Smuzhiyun  * @iolock: mutex for serializing io access
131*4882a593Smuzhiyun  * @irqlock: mutex for buslock
132*4882a593Smuzhiyun  * @irq_base: base IRQ number for max8998, required for IRQs
133*4882a593Smuzhiyun  * @irq: generic IRQ number for max8998
134*4882a593Smuzhiyun  * @ono: power onoff IRQ number for max8998
135*4882a593Smuzhiyun  * @irq_masks_cur: currently active value
136*4882a593Smuzhiyun  * @irq_masks_cache: cached hardware value
137*4882a593Smuzhiyun  * @type: indicate which max8998 "variant" is used
138*4882a593Smuzhiyun  */
139*4882a593Smuzhiyun struct max8998_dev {
140*4882a593Smuzhiyun 	struct device *dev;
141*4882a593Smuzhiyun 	struct max8998_platform_data *pdata;
142*4882a593Smuzhiyun 	struct i2c_client *i2c;
143*4882a593Smuzhiyun 	struct i2c_client *rtc;
144*4882a593Smuzhiyun 	struct mutex iolock;
145*4882a593Smuzhiyun 	struct mutex irqlock;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	unsigned int irq_base;
148*4882a593Smuzhiyun 	struct irq_domain *irq_domain;
149*4882a593Smuzhiyun 	int irq;
150*4882a593Smuzhiyun 	int ono;
151*4882a593Smuzhiyun 	u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
152*4882a593Smuzhiyun 	u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS];
153*4882a593Smuzhiyun 	unsigned long type;
154*4882a593Smuzhiyun 	bool wakeup;
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun int max8998_irq_init(struct max8998_dev *max8998);
158*4882a593Smuzhiyun void max8998_irq_exit(struct max8998_dev *max8998);
159*4882a593Smuzhiyun int max8998_irq_resume(struct max8998_dev *max8998);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
162*4882a593Smuzhiyun extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count,
163*4882a593Smuzhiyun 		u8 *buf);
164*4882a593Smuzhiyun extern int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
165*4882a593Smuzhiyun extern int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count,
166*4882a593Smuzhiyun 		u8 *buf);
167*4882a593Smuzhiyun extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun #endif /*  __LINUX_MFD_MAX8998_PRIV_H */
170