xref: /OK3568_Linux_fs/kernel/include/linux/mfd/max8925.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Maxim8925 Interface
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2009 Marvell International Ltd.
6*4882a593Smuzhiyun  *	Haojian Zhuang <haojian.zhuang@marvell.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef __LINUX_MFD_MAX8925_H
10*4882a593Smuzhiyun #define __LINUX_MFD_MAX8925_H
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/mutex.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /* Unified sub device IDs for MAX8925 */
16*4882a593Smuzhiyun enum {
17*4882a593Smuzhiyun 	MAX8925_ID_SD1,
18*4882a593Smuzhiyun 	MAX8925_ID_SD2,
19*4882a593Smuzhiyun 	MAX8925_ID_SD3,
20*4882a593Smuzhiyun 	MAX8925_ID_LDO1,
21*4882a593Smuzhiyun 	MAX8925_ID_LDO2,
22*4882a593Smuzhiyun 	MAX8925_ID_LDO3,
23*4882a593Smuzhiyun 	MAX8925_ID_LDO4,
24*4882a593Smuzhiyun 	MAX8925_ID_LDO5,
25*4882a593Smuzhiyun 	MAX8925_ID_LDO6,
26*4882a593Smuzhiyun 	MAX8925_ID_LDO7,
27*4882a593Smuzhiyun 	MAX8925_ID_LDO8,
28*4882a593Smuzhiyun 	MAX8925_ID_LDO9,
29*4882a593Smuzhiyun 	MAX8925_ID_LDO10,
30*4882a593Smuzhiyun 	MAX8925_ID_LDO11,
31*4882a593Smuzhiyun 	MAX8925_ID_LDO12,
32*4882a593Smuzhiyun 	MAX8925_ID_LDO13,
33*4882a593Smuzhiyun 	MAX8925_ID_LDO14,
34*4882a593Smuzhiyun 	MAX8925_ID_LDO15,
35*4882a593Smuzhiyun 	MAX8925_ID_LDO16,
36*4882a593Smuzhiyun 	MAX8925_ID_LDO17,
37*4882a593Smuzhiyun 	MAX8925_ID_LDO18,
38*4882a593Smuzhiyun 	MAX8925_ID_LDO19,
39*4882a593Smuzhiyun 	MAX8925_ID_LDO20,
40*4882a593Smuzhiyun 	MAX8925_ID_MAX,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun enum {
44*4882a593Smuzhiyun 	/*
45*4882a593Smuzhiyun 	 * Charging current threshold trigger going from fast charge
46*4882a593Smuzhiyun 	 * to TOPOFF charge. From 5% to 20% of fasting charging current.
47*4882a593Smuzhiyun 	 */
48*4882a593Smuzhiyun 	MAX8925_TOPOFF_THR_5PER,
49*4882a593Smuzhiyun 	MAX8925_TOPOFF_THR_10PER,
50*4882a593Smuzhiyun 	MAX8925_TOPOFF_THR_15PER,
51*4882a593Smuzhiyun 	MAX8925_TOPOFF_THR_20PER,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun enum {
55*4882a593Smuzhiyun 	/* Fast charging current */
56*4882a593Smuzhiyun 	MAX8925_FCHG_85MA,
57*4882a593Smuzhiyun 	MAX8925_FCHG_300MA,
58*4882a593Smuzhiyun 	MAX8925_FCHG_460MA,
59*4882a593Smuzhiyun 	MAX8925_FCHG_600MA,
60*4882a593Smuzhiyun 	MAX8925_FCHG_700MA,
61*4882a593Smuzhiyun 	MAX8925_FCHG_800MA,
62*4882a593Smuzhiyun 	MAX8925_FCHG_900MA,
63*4882a593Smuzhiyun 	MAX8925_FCHG_1000MA,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* Charger registers */
67*4882a593Smuzhiyun #define MAX8925_CHG_IRQ1		(0x7e)
68*4882a593Smuzhiyun #define MAX8925_CHG_IRQ2		(0x7f)
69*4882a593Smuzhiyun #define MAX8925_CHG_IRQ1_MASK		(0x80)
70*4882a593Smuzhiyun #define MAX8925_CHG_IRQ2_MASK		(0x81)
71*4882a593Smuzhiyun #define MAX8925_CHG_STATUS		(0x82)
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /* GPM registers */
74*4882a593Smuzhiyun #define MAX8925_SYSENSEL		(0x00)
75*4882a593Smuzhiyun #define MAX8925_ON_OFF_IRQ1		(0x01)
76*4882a593Smuzhiyun #define MAX8925_ON_OFF_IRQ1_MASK	(0x02)
77*4882a593Smuzhiyun #define MAX8925_ON_OFF_STATUS		(0x03)
78*4882a593Smuzhiyun #define MAX8925_ON_OFF_IRQ2		(0x0d)
79*4882a593Smuzhiyun #define MAX8925_ON_OFF_IRQ2_MASK	(0x0e)
80*4882a593Smuzhiyun #define MAX8925_RESET_CNFG		(0x0f)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /* Touch registers */
83*4882a593Smuzhiyun #define MAX8925_TSC_IRQ			(0x00)
84*4882a593Smuzhiyun #define MAX8925_TSC_IRQ_MASK		(0x01)
85*4882a593Smuzhiyun #define MAX8925_TSC_CNFG1		(0x02)
86*4882a593Smuzhiyun #define MAX8925_ADC_SCHED		(0x10)
87*4882a593Smuzhiyun #define MAX8925_ADC_RES_END		(0x6f)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #define MAX8925_NREF_OK			(1 << 4)
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun /* RTC registers */
92*4882a593Smuzhiyun #define MAX8925_ALARM0_CNTL		(0x18)
93*4882a593Smuzhiyun #define MAX8925_ALARM1_CNTL		(0x19)
94*4882a593Smuzhiyun #define MAX8925_RTC_IRQ			(0x1c)
95*4882a593Smuzhiyun #define MAX8925_RTC_IRQ_MASK		(0x1d)
96*4882a593Smuzhiyun #define MAX8925_MPL_CNTL		(0x1e)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /* WLED registers */
99*4882a593Smuzhiyun #define MAX8925_WLED_MODE_CNTL		(0x84)
100*4882a593Smuzhiyun #define MAX8925_WLED_CNTL		(0x85)
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /* MAX8925 Registers */
103*4882a593Smuzhiyun #define MAX8925_SDCTL1			(0x04)
104*4882a593Smuzhiyun #define MAX8925_SDCTL2			(0x07)
105*4882a593Smuzhiyun #define MAX8925_SDCTL3			(0x0A)
106*4882a593Smuzhiyun #define MAX8925_SDV1			(0x06)
107*4882a593Smuzhiyun #define MAX8925_SDV2			(0x09)
108*4882a593Smuzhiyun #define MAX8925_SDV3			(0x0C)
109*4882a593Smuzhiyun #define MAX8925_LDOCTL1			(0x18)
110*4882a593Smuzhiyun #define MAX8925_LDOCTL2			(0x1C)
111*4882a593Smuzhiyun #define MAX8925_LDOCTL3			(0x20)
112*4882a593Smuzhiyun #define MAX8925_LDOCTL4			(0x24)
113*4882a593Smuzhiyun #define MAX8925_LDOCTL5			(0x28)
114*4882a593Smuzhiyun #define MAX8925_LDOCTL6			(0x2C)
115*4882a593Smuzhiyun #define MAX8925_LDOCTL7			(0x30)
116*4882a593Smuzhiyun #define MAX8925_LDOCTL8			(0x34)
117*4882a593Smuzhiyun #define MAX8925_LDOCTL9			(0x38)
118*4882a593Smuzhiyun #define MAX8925_LDOCTL10		(0x3C)
119*4882a593Smuzhiyun #define MAX8925_LDOCTL11		(0x40)
120*4882a593Smuzhiyun #define MAX8925_LDOCTL12		(0x44)
121*4882a593Smuzhiyun #define MAX8925_LDOCTL13		(0x48)
122*4882a593Smuzhiyun #define MAX8925_LDOCTL14		(0x4C)
123*4882a593Smuzhiyun #define MAX8925_LDOCTL15		(0x50)
124*4882a593Smuzhiyun #define MAX8925_LDOCTL16		(0x10)
125*4882a593Smuzhiyun #define MAX8925_LDOCTL17		(0x14)
126*4882a593Smuzhiyun #define MAX8925_LDOCTL18		(0x72)
127*4882a593Smuzhiyun #define MAX8925_LDOCTL19		(0x5C)
128*4882a593Smuzhiyun #define MAX8925_LDOCTL20		(0x9C)
129*4882a593Smuzhiyun #define MAX8925_LDOVOUT1		(0x1A)
130*4882a593Smuzhiyun #define MAX8925_LDOVOUT2		(0x1E)
131*4882a593Smuzhiyun #define MAX8925_LDOVOUT3		(0x22)
132*4882a593Smuzhiyun #define MAX8925_LDOVOUT4		(0x26)
133*4882a593Smuzhiyun #define MAX8925_LDOVOUT5		(0x2A)
134*4882a593Smuzhiyun #define MAX8925_LDOVOUT6		(0x2E)
135*4882a593Smuzhiyun #define MAX8925_LDOVOUT7		(0x32)
136*4882a593Smuzhiyun #define MAX8925_LDOVOUT8		(0x36)
137*4882a593Smuzhiyun #define MAX8925_LDOVOUT9		(0x3A)
138*4882a593Smuzhiyun #define MAX8925_LDOVOUT10		(0x3E)
139*4882a593Smuzhiyun #define MAX8925_LDOVOUT11		(0x42)
140*4882a593Smuzhiyun #define MAX8925_LDOVOUT12		(0x46)
141*4882a593Smuzhiyun #define MAX8925_LDOVOUT13		(0x4A)
142*4882a593Smuzhiyun #define MAX8925_LDOVOUT14		(0x4E)
143*4882a593Smuzhiyun #define MAX8925_LDOVOUT15		(0x52)
144*4882a593Smuzhiyun #define MAX8925_LDOVOUT16		(0x12)
145*4882a593Smuzhiyun #define MAX8925_LDOVOUT17		(0x16)
146*4882a593Smuzhiyun #define MAX8925_LDOVOUT18		(0x74)
147*4882a593Smuzhiyun #define MAX8925_LDOVOUT19		(0x5E)
148*4882a593Smuzhiyun #define MAX8925_LDOVOUT20		(0x9E)
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /* bit definitions */
151*4882a593Smuzhiyun #define CHG_IRQ1_MASK			(0x07)
152*4882a593Smuzhiyun #define CHG_IRQ2_MASK			(0xff)
153*4882a593Smuzhiyun #define ON_OFF_IRQ1_MASK		(0xff)
154*4882a593Smuzhiyun #define ON_OFF_IRQ2_MASK		(0x03)
155*4882a593Smuzhiyun #define TSC_IRQ_MASK			(0x03)
156*4882a593Smuzhiyun #define RTC_IRQ_MASK			(0x0c)
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun #define MAX8925_NAME_SIZE		(32)
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /* IRQ definitions */
161*4882a593Smuzhiyun enum {
162*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_DC_OVP,
163*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_DC_F,
164*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_DC_R,
165*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_THM_OK_R,
166*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_THM_OK_F,
167*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_SYSLOW_F,
168*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_SYSLOW_R,
169*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_RST,
170*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_DONE,
171*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_TOPOFF,
172*4882a593Smuzhiyun 	MAX8925_IRQ_VCHG_TMR_FAULT,
173*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_RSTIN,
174*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_MPL,
175*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_SW_3SEC,
176*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_EXTON_F,
177*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_EXTON_R,
178*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_SW_1SEC,
179*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_SW_F,
180*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_SW_R,
181*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_SYSCKEN_F,
182*4882a593Smuzhiyun 	MAX8925_IRQ_GPM_SYSCKEN_R,
183*4882a593Smuzhiyun 	MAX8925_IRQ_RTC_ALARM1,
184*4882a593Smuzhiyun 	MAX8925_IRQ_RTC_ALARM0,
185*4882a593Smuzhiyun 	MAX8925_IRQ_TSC_STICK,
186*4882a593Smuzhiyun 	MAX8925_IRQ_TSC_NSTICK,
187*4882a593Smuzhiyun 	MAX8925_NR_IRQS,
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun struct max8925_chip {
193*4882a593Smuzhiyun 	struct device		*dev;
194*4882a593Smuzhiyun 	struct i2c_client	*i2c;
195*4882a593Smuzhiyun 	struct i2c_client	*adc;
196*4882a593Smuzhiyun 	struct i2c_client	*rtc;
197*4882a593Smuzhiyun 	struct mutex		io_lock;
198*4882a593Smuzhiyun 	struct mutex		irq_lock;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	int			irq_base;
201*4882a593Smuzhiyun 	int			core_irq;
202*4882a593Smuzhiyun 	int			tsc_irq;
203*4882a593Smuzhiyun 	unsigned int            wakeup_flag;
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun struct max8925_backlight_pdata {
207*4882a593Smuzhiyun 	int	lxw_scl;	/* 0/1 -- 0.8Ohm/0.4Ohm */
208*4882a593Smuzhiyun 	int	lxw_freq;	/* 700KHz ~ 1400KHz */
209*4882a593Smuzhiyun 	int	dual_string;	/* 0/1 -- single/dual string */
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun struct max8925_touch_pdata {
213*4882a593Smuzhiyun 	unsigned int		flags;
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun struct max8925_power_pdata {
217*4882a593Smuzhiyun 	int		(*set_charger)(int);
218*4882a593Smuzhiyun 	unsigned	batt_detect:1;
219*4882a593Smuzhiyun 	unsigned	topoff_threshold:2;
220*4882a593Smuzhiyun 	unsigned	fast_charge:3;	/* charge current */
221*4882a593Smuzhiyun 	unsigned	no_temp_support:1; /* set if no temperature detect */
222*4882a593Smuzhiyun 	unsigned	no_insert_detect:1; /* set if no ac insert detect */
223*4882a593Smuzhiyun 	char		**supplied_to;
224*4882a593Smuzhiyun 	int		num_supplicants;
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun  * irq_base: stores IRQ base number of MAX8925 in platform
229*4882a593Smuzhiyun  * tsc_irq: stores IRQ number of MAX8925 TSC
230*4882a593Smuzhiyun  */
231*4882a593Smuzhiyun struct max8925_platform_data {
232*4882a593Smuzhiyun 	struct max8925_backlight_pdata	*backlight;
233*4882a593Smuzhiyun 	struct max8925_touch_pdata	*touch;
234*4882a593Smuzhiyun 	struct max8925_power_pdata	*power;
235*4882a593Smuzhiyun 	struct regulator_init_data	*sd1;
236*4882a593Smuzhiyun 	struct regulator_init_data	*sd2;
237*4882a593Smuzhiyun 	struct regulator_init_data	*sd3;
238*4882a593Smuzhiyun 	struct regulator_init_data	*ldo1;
239*4882a593Smuzhiyun 	struct regulator_init_data	*ldo2;
240*4882a593Smuzhiyun 	struct regulator_init_data	*ldo3;
241*4882a593Smuzhiyun 	struct regulator_init_data	*ldo4;
242*4882a593Smuzhiyun 	struct regulator_init_data	*ldo5;
243*4882a593Smuzhiyun 	struct regulator_init_data	*ldo6;
244*4882a593Smuzhiyun 	struct regulator_init_data	*ldo7;
245*4882a593Smuzhiyun 	struct regulator_init_data	*ldo8;
246*4882a593Smuzhiyun 	struct regulator_init_data	*ldo9;
247*4882a593Smuzhiyun 	struct regulator_init_data	*ldo10;
248*4882a593Smuzhiyun 	struct regulator_init_data	*ldo11;
249*4882a593Smuzhiyun 	struct regulator_init_data	*ldo12;
250*4882a593Smuzhiyun 	struct regulator_init_data	*ldo13;
251*4882a593Smuzhiyun 	struct regulator_init_data	*ldo14;
252*4882a593Smuzhiyun 	struct regulator_init_data	*ldo15;
253*4882a593Smuzhiyun 	struct regulator_init_data	*ldo16;
254*4882a593Smuzhiyun 	struct regulator_init_data	*ldo17;
255*4882a593Smuzhiyun 	struct regulator_init_data	*ldo18;
256*4882a593Smuzhiyun 	struct regulator_init_data	*ldo19;
257*4882a593Smuzhiyun 	struct regulator_init_data	*ldo20;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	int		irq_base;
260*4882a593Smuzhiyun 	int		tsc_irq;
261*4882a593Smuzhiyun };
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun extern int max8925_reg_read(struct i2c_client *, int);
264*4882a593Smuzhiyun extern int max8925_reg_write(struct i2c_client *, int, unsigned char);
265*4882a593Smuzhiyun extern int max8925_bulk_read(struct i2c_client *, int, int, unsigned char *);
266*4882a593Smuzhiyun extern int max8925_bulk_write(struct i2c_client *, int, int, unsigned char *);
267*4882a593Smuzhiyun extern int max8925_set_bits(struct i2c_client *, int, unsigned char,
268*4882a593Smuzhiyun 			unsigned char);
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun extern int max8925_device_init(struct max8925_chip *,
271*4882a593Smuzhiyun 				struct max8925_platform_data *);
272*4882a593Smuzhiyun extern void max8925_device_exit(struct max8925_chip *);
273*4882a593Smuzhiyun #endif /* __LINUX_MFD_MAX8925_H */
274*4882a593Smuzhiyun 
275